Re: [gem5-users] x86 floating point instruction

Hi Gabe, Jason, Are those x86 SIMD SSE arithmetic instructions take only one cycle as latency? I looked into the FuncUnitConfig.py and seems like the op lats for the SIMD functional units are not defined, so I assumed it takes value of 1 by default. I am not really familiar with x86 SIMD

Re: [gem5-users] Response for WritebackDirty packets (learning.gem5)

Dear Jason, Thkns for the response. Just another quick question. What if memory was busy when u call the "sendTiimingReq" for WritebackDirty packet. In insert() function, when you call memport.sendTimingReq for WritebackDirty blocks, you don't save them in blocked Packet, in case Memory is

Re: [gem5-users] RISCV ISA : "C" (compressed) extension supported?

Hi Jason, Alec, Just to provide some feedback on this issue, it seems that the processor is mistakenly identifying (add reg, reg, reg) in compressed format as a branch instruction. I'm running a kernel that looks like this (result from *riscv64-unknown-elf-objdump -D*) 0001019a :