[gem5-users] Re: Ask for HELP about SMT in FS mode

Hi, You shouldn't be concerned about the warnings you mentioned; those are quite common and they shouldn't affect the functional correctness of you simulation warn: instruction'csdb' unimplemented warn: GIC APRn write ignored because not implemented: 0xd0 About SMT: I am not aware of the

[gem5-users] How to add a new pcie device on GEM5

Hi All: Any one has experience on how to add ad new pcie device on GEM5? This device can be just a demo device which has only a few basic operation like read,write… So if I want to add a pcie device,any config I need to realize? Or any examples?

[gem5-users] Re: How to add a new pcie device on GEM5

Hi, I’d recommend having a look at the VirtIO device…. (I don’t know if there are better examples, more experienced people are welcome to chime in) Giacomo From: Liyichao via gem5-users Sent: 22 October 2020 11:51 To: gem5 users mailing list Cc: Liyichao Subject: [gem5-users] How to add a

[gem5-users] Re: Cache level 1 miss rate is the same with and without level 2 cache

On 10/22/2020 1:26 PM, Muhammad Aamir via gem5-users wrote: Hi, the miss rates are exactly the same when using the in-order CPU for both when using level 1 cache alone and using it with level 1 and 2 cache. For O3CPU, there is a very minor difference (i.e. a difference of 0.01) but almost the

[gem5-users] Re: Cache level 1 miss rate is the same with and without level 2 cache

Hi, I do not think that making the cache hierarchy deeper will have any effect on 1'st level cache hit/miss rate. Best regards, Abhishek On Thu, Oct 22, 2020 at 1:03 PM Abhishek Singh < abhishek.singh199...@gmail.com> wrote: > Hi, > > Does this happen with O3 CPU or just the in order CPU? >

[gem5-users] Re: Cache level 1 miss rate is the same with and without level 2 cache

Hi Eliot, I have a few questions, maybe unrelated, if you do not mind answering them as I am confused. Assuming I have an array of size 1million and where I access only 100 elements of it in a random manner using an LFSR generator. If I have only one level of cache of size 1kB my miss rate should

[gem5-users] Cache level 1 miss rate is the same with and without level 2 cache

Hi everyone, I have noticed that the stat: "system.cpu.dcache.overall_miss_rate::total" is the same if I only use 1 level of cache or use the system with a level 2 cache. As we know it should change but it remains exactly the same, how is this possible? Would someone be kind enough to explain

[gem5-users] Re: Cache level 1 miss rate is the same with and without level 2 cache

Hi, Does this happen with O3 CPU or just the in order CPU? On Thu, Oct 22, 2020 at 1:01 PM Muhammad Aamir via gem5-users < gem5-users@gem5.org> wrote: > Hi everyone, > > I have noticed that the stat: "system.cpu.dcache.overall_miss_rate::total" > is the same if I only use 1 level of cache or

[gem5-users] Re: Cache level 1 miss rate is the same with and without level 2 cache

Hi, the miss rates are exactly the same when using the in-order CPU for both when using level 1 cache alone and using it with level 1 and 2 cache. For O3CPU, there is a very minor difference (i.e. a difference of 0.01) but almost the same. This shouldn't be the case, if I only have one level of

[gem5-users] Re: Configure multi-bank cache in ruby ​mode with MESI coherence protocol

Hello Jason: Resource stall, you mean there is only one bank, but we use resource stall to implement interleaving bank? I want to config multi banks of L0 and L1 to improve the parallelism of cache，and the number of banks can point by defined L0_bank_number arguments in .py scripy，if I