[gem5-users] Re: How to enable KVM unitest on ARM server
Hi, I just grepped through all of gem5's source, and, even ignoring
capitalization, the string "KVM for" does not appear outside of a couple
comments. I have no idea where that string is coming from, but it doesn't
seem to be from gem5 itself.
Gabe
On Thu, Oct 28, 2021 at 8:04 PM Liyichao via gem5-users
wrote:
> Hi All:
>
> My GEM5 V21.1.0.2 running on aarch64 server, but when I compile
> bitunion.test.opt, the compilation print will show “Info: KVM for null not
> supported on arm host.”
>
>
>
> scons build/NULL/base/bitunion.test.opt -j120
>
> scons: Reading SConscript files ...
>
> Checking for linker -Wl,--as-needed support... (cached) yes
>
> Warning: While checking protoc version: [Errno 2] No such file or
> directory: 'protoc'
>
> Warning: Protocol buffer compiler (protoc) not found.
>
> Please install protobuf-compiler for tracing support.
>
> Checking for compiler -gz support... (cached) yes
>
> Checking for linker -gz support... (cached) yes
>
> Info: Using Python config: python3-config
>
> Checking for C header file Python.h... (cached) yes
>
> Checking for C library python3.8... (cached) yes
>
> Checking for C library crypt... (cached) yes
>
> Checking for C library pthread... (cached) yes
>
> Checking for C library dl... (cached) yes
>
> Checking for C library util... (cached) yes
>
> Checking for C library m... (cached) yes
>
> Checking Python version... (cached) 3.8.5
>
> Checking for accept(0,0,0) in C++ library None... (cached) yes
>
> Checking for zlibVersion() in C++ library z... (cached) yes
>
> Checking for C header file valgrind/valgrind.h... (cached) no
>
> Checking for clock_nanosleep(0,0,NULL,NULL) in C library None... (cached)
> yes
>
> Checking for timer_create(CLOCK_MONOTONIC, NULL, NULL) in C library
> None... (cached) no
>
> Checking for timer_create(CLOCK_MONOTONIC, NULL, NULL) in C library rt...
> (cached) yes
>
> Checking for C library tcmalloc... (cached) yes
>
> Checking for char temp; backtrace_symbols_fd((void *), 0, 0) in C
> library None... (cached) yes
>
> Checking for C header file fenv.h... (cached) yes
>
> Checking for C header file png.h... (cached) yes
>
> Checking for C header file linux/kvm.h... (cached) yes
>
> Checking for C header file linux/if_tun.h... (cached) yes
>
> Checking for member exclude_host in struct perf_event_attr...(cached) yes
>
> Checking for H5Fcreate("", 0, 0, 0) in C library hdf5... (cached) no
>
> Warning: Couldn't find any HDF5 C++ libraries. Disabling HDF5 support.
>
> Checking whether __i386__ is declared... (cached) no
>
> Checking whether __x86_64__ is declared... (cached) no
>
> Warning: Unrecognized architecture for systemc.
>
> Building in /home/l00515693/KSim_LightESL/build/NULL
>
> Variables file /home/l00515693/KSim_LightESL/build/variables/NULL not
> found,
>
> using defaults in /home/l00515693/KSim_LightESL/build_opts/NULL
>
> *Info: KVM for null not supported on arm host.*
>
> scons: done reading SConscript files.
>
> scons: Building targets ...
>
>
>
>
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[gem5-users] How to enable KVM unitest on ARM server
Hi All:
My GEM5 V21.1.0.2 running on aarch64 server, but when I compile
bitunion.test.opt, the compilation print will show "Info: KVM for null not
supported on arm host."
scons build/NULL/base/bitunion.test.opt -j120
scons: Reading SConscript files ...
Checking for linker -Wl,--as-needed support... (cached) yes
Warning: While checking protoc version: [Errno 2] No such file or directory:
'protoc'
Warning: Protocol buffer compiler (protoc) not found.
Please install protobuf-compiler for tracing support.
Checking for compiler -gz support... (cached) yes
Checking for linker -gz support... (cached) yes
Info: Using Python config: python3-config
Checking for C header file Python.h... (cached) yes
Checking for C library python3.8... (cached) yes
Checking for C library crypt... (cached) yes
Checking for C library pthread... (cached) yes
Checking for C library dl... (cached) yes
Checking for C library util... (cached) yes
Checking for C library m... (cached) yes
Checking Python version... (cached) 3.8.5
Checking for accept(0,0,0) in C++ library None... (cached) yes
Checking for zlibVersion() in C++ library z... (cached) yes
Checking for C header file valgrind/valgrind.h... (cached) no
Checking for clock_nanosleep(0,0,NULL,NULL) in C library None... (cached) yes
Checking for timer_create(CLOCK_MONOTONIC, NULL, NULL) in C library None...
(cached) no
Checking for timer_create(CLOCK_MONOTONIC, NULL, NULL) in C library rt...
(cached) yes
Checking for C library tcmalloc... (cached) yes
Checking for char temp; backtrace_symbols_fd((void *), 0, 0) in C library
None... (cached) yes
Checking for C header file fenv.h... (cached) yes
Checking for C header file png.h... (cached) yes
Checking for C header file linux/kvm.h... (cached) yes
Checking for C header file linux/if_tun.h... (cached) yes
Checking for member exclude_host in struct perf_event_attr...(cached) yes
Checking for H5Fcreate("", 0, 0, 0) in C library hdf5... (cached) no
Warning: Couldn't find any HDF5 C++ libraries. Disabling HDF5 support.
Checking whether __i386__ is declared... (cached) no
Checking whether __x86_64__ is declared... (cached) no
Warning: Unrecognized architecture for systemc.
Building in /home/l00515693/KSim_LightESL/build/NULL
Variables file /home/l00515693/KSim_LightESL/build/variables/NULL not found,
using defaults in /home/l00515693/KSim_LightESL/build_opts/NULL
Info: KVM for null not supported on arm host.
scons: done reading SConscript files.
scons: Building targets ...
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[gem5-users] Re: Working X86 multi-core full system config with caches?
Hey Antoine, First of all, multi-core TimingSimple with classic caches will not work, you have to use Ruby or run a single-core simulation. I think we have something in development which can help you out. You can run a full-system X86 Ubuntu simulation with the Ruby MESI Two Level protocol with the following: ``` git clone https://gem5.googlesource.com/public/gem5 cd gem5 git checkout develop scons build/X86_MESI_Two_Level/gem5.opt -j`nproc` ./build/X86_MESI_Two_Level/gem5.opt configs/example/gem5_library/x86-ubuntu-run.py ``` If you have KVM on your system this will boot Ubuntu with KVM then run a very simple script using the Timing Simple CPU. If you don't have KVM then you can alter the simulation at line 94 in the `configs/example/gem5_library/x86-ubuntu-run.py` file, and just run the whole boot with the Timing Simple CPU. The `x86-ubuntu-run.py` script builds upon our gem5 Python Library, which is still under development, but you can look into it (under `src/python/gem5`) to see how it all fits together and works. The `x86-ubuntu-run.py` script itself should be relatively self-explanatory, but please do not hesitate to get back to me if there's something you don't understand. Getting a full-system setup working is _tough_ if building a simulation from scratch which is part of the reason we're moving more towards providing a library for such things. Kind regards, Bobby -- Dr. Bobby R. Bruce Room 3050, Kemper Hall, UC Davis Davis, CA, 95616 web: https://www.bobbybruce.net On Thu, Oct 28, 2021 at 10:55 AM Antoine Kaufmann via gem5-users < gem5-users@gem5.org> wrote: > Hi Everyone, > > Do we have any known-working configurations for x86 multi-core full system > simulations with caches? > > We have successfully been using single core configs for more than a year > now, > but our attempts at anything multi-core have so far not been successful, > with > problems ranging from gem5 crashing to Linux getting stuck at boot. > > We have been using the TimingSimple CPU and tried both classic and ruby > with > various protocols. > > Does anyone have pointers to working configurations? Or is this something > that > is known to be fundamentally broken? > > Thanks in advance, > Antoine > > -- > Antoine Kaufmann > > ___ > gem5-users mailing list -- gem5-users@gem5.org > To unsubscribe send an email to gem5-users-le...@gem5.org > %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] Working X86 multi-core full system config with caches?
Hi Everyone, Do we have any known-working configurations for x86 multi-core full system simulations with caches? We have successfully been using single core configs for more than a year now, but our attempts at anything multi-core have so far not been successful, with problems ranging from gem5 crashing to Linux getting stuck at boot. We have been using the TimingSimple CPU and tried both classic and ruby with various protocols. Does anyone have pointers to working configurations? Or is this something that is known to be fundamentally broken? Thanks in advance, Antoine -- Antoine Kaufmann signature.asc Description: PGP signature ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] Re: Vector Instructions Support
Hello, For Arm, gem5 has SVE support and (some/most/all?) of the NEON instructions. For x86, we support most 128-bit SIMD instructions, but very few or no 256-bit or 512-bit SIMD instructions. I have heard of forks/groups that have implemented many of the x86 vector instructions, and I have heard that RISC-V vector extensions have been implemented. However, these implementations have not been made public or have not been pushed upstream. Cheers, Jason On Thu, Oct 28, 2021 at 4:08 AM nitesh--- via gem5-users < gem5-users@gem5.org> wrote: > Hi > > I am working on understanding VPUs and vector instructions, and am a bit > new to the gem5 environment. I aI wanted to know if there is any official > update on the vector instruction support for gem5 x86 and ARM? I see there > are some forked versions available in the community but I am skeptical > about their stability and version. Would like to know if anyone recommends > any such version. > > I also see In this link > https://www.gem5.org/documentation/general_docs/architecture_support/ > that gem5 has support for SSE in x86 but see little documentation regarding > that. Also no mention of ARM vector instruction support. > > Sorry if I am wrong regarding the things I have mentioned. > > So any guidance, help, or advice regarding this will be great!! > > Thanks > ___ > gem5-users mailing list -- gem5-users@gem5.org > To unsubscribe send an email to gem5-users-le...@gem5.org > %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s > ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] Vector Instructions Support
Hi I am working on understanding VPUs and vector instructions, and am a bit new to the gem5 environment. I aI wanted to know if there is any official update on the vector instruction support for gem5 x86 and ARM? I see there are some forked versions available in the community but I am skeptical about their stability and version. Would like to know if anyone recommends any such version. I also see In this link https://www.gem5.org/documentation/general_docs/architecture_support/ that gem5 has support for SSE in x86 but see little documentation regarding that. Also no mention of ARM vector instruction support. Sorry if I am wrong regarding the things I have mentioned. So any guidance, help, or advice regarding this will be great!! Thanks ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
