Dear, Varun.
In my opinion, you can make new class which inherit BaseCache or MemObject.
As I think, if you implement tag-less cache in conventional cache class,
you need to a flag which indicate tag-less cache and many conditional
sentence everywhere operate differently with a conventional
Hi,
I'm trying to implement a tag-less cache architecture only for the last
level cache. As I understand, there is only one implementation for all
levels of caches. How do I change only the implementation for the last
level cache, leaving other caches being accessed in a conventional manner.
Any
Hi Vitorio,
You should check the content of log.switch and why gem5 node simulating
switch cannot start. There can be so many reasons that a gem5 process fails
to run. If you print the content of switch.log here then I can help.
Regarding "distributed run", you first need to setup passwordless
Hi Yasir,
Honestly, I'm not exactly sure why. Here's a dump of what's going on:
7319000: system.membus.reqLayer2: The crossbar layer is now busy from tick
7319000 to 7319000
7319000: system.cpu.iew.lsq.thread0: Executing load PC
(0x409d9a=>0x409d9f).(0=>1), [sn:1627]
7319000:
Hello,
Please, what exactly do I need to run dist-gem5 with the --dist?
I'm trying, however it fails with "Failed ot start switch"
Also, what do I need in place for it start distributed acroos nodes, instead of
launching multiple/parallel runs in the 'localhost'.
Regards,
Vitorio.
Thanks for pointing this out!
There's a fix here:
https://gem5-review.googlesource.com/c/public/gem5/+/6421. Feel free to
review so it gets in as fast as possible :).
Cheers,
Jason
On Mon, Dec 4, 2017 at 11:33 PM 조해윤 wrote:
> Hi all,
>
> The recent commit for learning
Hi Jason,
Is there as specific reason as to why you can’t connect O3 ports directly to
the crossbar ? I have added Scratchpad memories at the same level as L1. I used
NonCoherent Xbar to connect the scratch pad and L1 and them connected the Xbar
to the CPU ports.
The system worked fine for