Re: [gem5-users] errors compiling gem5 with GCC 9.2.1 (Ubuntu 19.10)
I agree with Ciro, but will add that things should work with version 7 and boost is not supposed to be a dependency. The systemc standard *claims* that boost is not required, just specifying some macros that resolve to boost code. Unfortunately in reality, the Accellera implementation includes boost directly, and their tests (which we try to pass) break if we don't do that too. The headers are set up in such a way that that include *should* be isolated though, unless you've included one of the top level systemc includes like or . That way gem5 itself doesn't require boost, and if you're using systemc, you'd need it even if you were using Accellera instead. If you can identify where that include is coming from, we should fix that as soon as possible. Gabe On Mon, Nov 4, 2019 at 1:30 PM Ciro Santilli wrote: > On Mon, Nov 4, 2019 at 8:09 PM Andreas Brokalakis > wrote: > > > > Hi all, > > > > I am trying to compile gem5 cloned from the official repository on > Ubuntu 19.10 with gcc 9.2.1 installed. I keep on getting errors that make > practically the compilation process impossible. > > > > The first errors were about implicitly-declared things all over the > code. I managed to workaround them by adding the option > -Wno-error=deprecated-copy . Then there were errors all over the place > about redundant move in return statement. The only way I managed to > workaround this was by falling back on gcc 7. > > > > Things break for every new major GCC version due to more strict error > checking, patches that fix them without ignoring errors are welcome > :-) > > > After that there was an error about not finding boost/bind.hpp . > Installing boost is not a documented dependency and I only found this on > gem5-dev mailing list: > https://www.mail-archive.com/gem5-dev@gem5.org/msg28734.html > > > > From my understanding this is a dependency for when building something > that requires interaction with SystemC. Should it be there when building > mainline versions of GEM5? Also it is not documented and maybe instructions > on building gem5 should be updated (they are already very old). > > > > Previous discussion at: > https://www.mail-archive.com/gem5-dev@gem5.org/msg28730.html and I've > now updated the dependencies page: http://www.gem5.org/Dependencies > > > Best, > > Andreas > > ___ > > gem5-users mailing list > > gem5-users@gem5.org > > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > ___ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] errors compiling gem5 with GCC 9.2.1 (Ubuntu 19.10)
On Mon, Nov 4, 2019 at 8:09 PM Andreas Brokalakis wrote: > > Hi all, > > I am trying to compile gem5 cloned from the official repository on Ubuntu > 19.10 with gcc 9.2.1 installed. I keep on getting errors that make > practically the compilation process impossible. > > The first errors were about implicitly-declared things all over the code. I > managed to workaround them by adding the option -Wno-error=deprecated-copy . > Then there were errors all over the place about redundant move in return > statement. The only way I managed to workaround this was by falling back on > gcc 7. > Things break for every new major GCC version due to more strict error checking, patches that fix them without ignoring errors are welcome :-) > After that there was an error about not finding boost/bind.hpp . Installing > boost is not a documented dependency and I only found this on gem5-dev > mailing list: https://www.mail-archive.com/gem5-dev@gem5.org/msg28734.html > > From my understanding this is a dependency for when building something that > requires interaction with SystemC. Should it be there when building mainline > versions of GEM5? Also it is not documented and maybe instructions on > building gem5 should be updated (they are already very old). > Previous discussion at: https://www.mail-archive.com/gem5-dev@gem5.org/msg28730.html and I've now updated the dependencies page: http://www.gem5.org/Dependencies > Best, > Andreas > ___ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] errors compiling gem5 with GCC 9.2.1 (Ubuntu 19.10)
Hi all, I am trying to compile gem5 cloned from the official repository on Ubuntu 19.10 with gcc 9.2.1 installed. I keep on getting errors that make practically the compilation process impossible. The first errors were about implicitly-declared things all over the code. I managed to workaround them by adding the option -Wno-error=deprecated-copy . Then there were errors all over the place about redundant move in return statement. The only way I managed to workaround this was by falling back on gcc 7. After that there was an error about not finding boost/bind.hpp . Installing boost is not a documented dependency and I only found this on gem5-dev mailing list: https://www.mail-archive.com/gem5-dev@gem5.org/msg28734.html >From my understanding this is a dependency for when building something that requires interaction with SystemC. Should it be there when building mainline versions of GEM5? Also it is not documented and maybe instructions on building gem5 should be updated (they are already very old). Best, Andreas ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] devices.py
Hello Please see comments in-line. Tks JO > -Original Message- > From: Ciro Santilli [mailto:ciro.santi...@arm.com] > Sent: 04 November 2019 18:07 > To: gem5 users mailing list ; Javed Osmany > > Subject: Re: [gem5-users] devices.py > > > > On 10/29/19 12:44 PM, Javed Osmany wrote: > > Hello > > > > I am trying to model a simple system using the MinorCPU() model. > > > > In the Arm Research Starter kit documentation they give an example > > (page > > 17) where they make use of devices.L1I, devices.L1D, devices.WalkCache > > and devices.L2 to instantiate the L1I$, L1D$, L2$ cache subsystem. > > > > In my simple system model I wanted to make use of an L2 XBAR bus > > connection to connect the L1 and L2 caches. > > > > I assumed that the L2 XBAR would be defined in devices.py, but could > > not find it. The only references to L2XBAR I could find in devices.py > > are the following: > > > > def addL2(self, clk_domain): > > > > if self._l2_type is None: > > > > return > > > > self.toL2Bus = L2XBar(width=64, clk_domain=clk_domain) > > > > self.l2 = self._l2_type() > > > > for cpu in self.cpus: > > > > cpu.connectAllPorts(self.toL2Bus) > > > > self.toL2Bus.master = self.l2.cpu_side > > > > def addCaches(self, need_caches, last_cache_level): > > > > if not need_caches: > > > > # connect each cluster to the memory hierarchy > > > > for cluster in self._clusters: > > > > cluster.connectMemSide(self.membus) > > > > return > > > > cluster_mem_bus = self.membus > > > > assert last_cache_level >= 1 and last_cache_level <= 3 > > > > for cluster in self._clusters: > > > > cluster.addL1() > > > > if last_cache_level > 1: > > > > for cluster in self._clusters: > > > > cluster.addL2(cluster.clk_domain) > > > > if last_cache_level > 2: > > > > max_clock_cluster = max(self._clusters, > > > > key=lambda c: > > c.clk_domain.clock[0]) > > > > self.l3 = L3(clk_domain=max_clock_cluster.clk_domain) > > > > self.toL3Bus = L2XBar(width=64) > > > > self.toL3Bus.master = self.l3.cpu_side > > > > self.l3.mem_side = self.membus.slave > > > > cluster_mem_bus = self.toL3Bus > > > > Am I correct in thinking that the actual instantiation of the L2XBar > > bus is not done in devices.py? > > > > Do you mean definition of L2XBar, since the instantiation is "self.toL2Bus = > L2XBar(width=64, clk_domain=clk_domain)"? [JO: ] [JO: ] Okay, if this is the instantiation of L2XBAR, but I was not able to connect my L1$ and L2$ to the XBAR. Will revisit, given the information you have provided. > > About the definition, "git grep L2XBar" shows "src/mem/XBar.py:137:class > L2XBar(CoherentXBar):", isn't that the one? [JO: ] [JO: ] Yes, this the definition. The issue I was having was trying to connect to the instantiation of the L2XBAR. > > > Best regards > > > > J.Osmany > > > > > > ___ > > gem5-users mailing list > > gem5-users@gem5.org > > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > > > IMPORTANT NOTICE: The contents of this email and any attachments are > confidential and may also be privileged. If you are not the intended > recipient, > please notify the sender immediately and do not disclose the contents to any > other person, use it for any purpose, or store or copy the information in any > medium. Thank you. ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] system.cpu
On 10/28/19 3:13 PM, Javed Osmany wrote:
> Hello
>
> I have a simple system simulation configuration script where I set
> system.cpu:
>
> system.cpu = O3_ARM_v7a.O3_ARM_v7a_3()
>
> I then try to print this to confirm and then furthermore set the
> system.mem_mode depending upon the cpu type being used.
>
> However, when I try
>
> print ("System CPU type is: %s" % (system.cpu))
>
> I am getting
>
> *System CPU type is: .cpu **ç**Not able to access
> system.cpu ??*
>
I'm not sure why this is happening. For example, the following fs.py
patch does not show that message:
--- a/configs/example/fs.py
+++ b/configs/example/fs.py
@@ -143,6 +143,7 @@ def build_test_system(np):
# For now, assign all the CPUs to the same clock domain
test_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain,
cpu_id=i)
for i in range(np)]
+print ("System CPU type is: %s" % (test_sys.cpu))
gives:
System CPU type is: []
I would recommend comparing your script to the existing configs, and
using pdb to understand what is going on.
> This would then explain why further on the following check are not working:
>
> if (system.cpu == "AtomicSimpleCPU()"):
>
> system.mem_mode = 'atomic'
>
> else:
>
> system.mem_mode = 'timing'
>
> if (system.cpu == "O3_ARM_v7a.O3_ARM_v7a_3()"):
>
> print ("CPU model is O3_ARM_v7a\n")
>
> system.cpu.icache = O3_ARM_v7a.O3_ARM_v7a_ICache()
>
> system.cpu.dcache = O3_ARM_v7a.O3_ARM_v7a_DCache()
>
> system.cpu.PageTableWalkerCache = O3_ARM_v7a.O3_ARM_v7aWalkCache()
>
> system.l2cache = O3_ARM_v7a.O3_ARM_v7aL2()
>
> Any pointers?
>
> Tks in advance
>
> Best regards
>
> J.Osmany
>
>
> ___
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>
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Re: [gem5-users] devices.py
On 10/29/19 12:44 PM, Javed Osmany wrote: > Hello > > I am trying to model a simple system using the MinorCPU() model. > > In the Arm Research Starter kit documentation they give an example (page > 17) where they make use of devices.L1I, devices.L1D, devices.WalkCache > and devices.L2 to instantiate the L1I$, L1D$, L2$ cache subsystem. > > In my simple system model I wanted to make use of an L2 XBAR bus > connection to connect the L1 and L2 caches. > > I assumed that the L2 XBAR would be defined in devices.py, but could not > find it. The only references to L2XBAR I could find in devices.py are > the following: > > def addL2(self, clk_domain): > > if self._l2_type is None: > > return > > self.toL2Bus = L2XBar(width=64, clk_domain=clk_domain) > > self.l2 = self._l2_type() > > for cpu in self.cpus: > > cpu.connectAllPorts(self.toL2Bus) > > self.toL2Bus.master = self.l2.cpu_side > > def addCaches(self, need_caches, last_cache_level): > > if not need_caches: > > # connect each cluster to the memory hierarchy > > for cluster in self._clusters: > > cluster.connectMemSide(self.membus) > > return > > cluster_mem_bus = self.membus > > assert last_cache_level >= 1 and last_cache_level <= 3 > > for cluster in self._clusters: > > cluster.addL1() > > if last_cache_level > 1: > > for cluster in self._clusters: > > cluster.addL2(cluster.clk_domain) > > if last_cache_level > 2: > > max_clock_cluster = max(self._clusters, > > key=lambda c: > c.clk_domain.clock[0]) > > self.l3 = L3(clk_domain=max_clock_cluster.clk_domain) > > self.toL3Bus = L2XBar(width=64) > > self.toL3Bus.master = self.l3.cpu_side > > self.l3.mem_side = self.membus.slave > > cluster_mem_bus = self.toL3Bus > > Am I correct in thinking that the actual instantiation of the L2XBar bus > is not done in devices.py? > Do you mean definition of L2XBar, since the instantiation is "self.toL2Bus = L2XBar(width=64, clk_domain=clk_domain)"? About the definition, "git grep L2XBar" shows "src/mem/XBar.py:137:class L2XBar(CoherentXBar):", isn't that the one? > Best regards > > J.Osmany > > > ___ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
