[gem5-users] SE Mode crashing with multithread workload

[Farhad Yusufali via gem5-users]

Hi all,

My gem5 version is fa70478413e4650d0058cbfe81fd5ce362101994. I'm trying to run 
a multithreaded workload in SE mode, but it's crashing. Here is my very simple 
workload:


#include 

#include 

using namespace std;


int sum[4];


void* thread(void* sum) {

  for (int i = 0; i < 1000; i++)

*((int*)sum) += i;


  return 0;

}


int main() {

  sum[0] = sum[1] = sum[2] = sum[3] = 0;

  pthread_t threads[4];


  for (int tid = 0; tid < 4; tid++)

  pthread_create([tid], NULL, thread, [tid]);


  for (int tid = 0; tid < 4; tid++)

  pthread_join(threads[tid], NULL);


  cout << sum [0] << " " << sum[1] << " " << sum[2] << " " << sum[3] << endl;

  return 0;

}



When I run it with:

build/X86/gem5.opt --debug-flags=PseudoInst configs/example/se.py --cmd=./multi 
--num-cpus=4 --ruby --cpu-type=DerivO3CPU

I get:
panic: panic condition !clobber occurred: EmulationPageTable::allocate: addr 
0x7778d000 already mapped

I found an existing thread that discusses this but no update was posted: 
https://www.mail-archive.com/gem5-users@gem5.org/msg17926.html

Was this ever resolved?

Thanks,
Farhad
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[gem5-users] XBar on dcache port impacting BW?

[fisher.xue--- via gem5-users]

I am trying to connect the L1D to the CPU dcache port over an XBar (I intend to 
connect another memory to this XBar), however, when making this connection, I 
observe that the bandwidth to my L1 halves due  to XBar contention, however, I 
am modelling this as a 0-latency XBar with effectively infinite width. Does 
anyone have any idea what I could be doing wrong?
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[gem5-users] Re: Shared L2 with Mesh XY Topology

[Krishna, Tushar via gem5-users]

Private vs Shared L2 depends on the coherence protocol you use. The coherence 
protocol exposes the total number of controllers (L1/L2/Dir) which you can 
connect whatever way you want.
Similarly, if you have a shared L2, I think the coherence protocol can expose 
multiple NUCA slices or a single one. [I am not familiar with the latest in 
terms of the coherence protocols in gem5 today].

There does not need to be a one L2 per core — the Mesh_* is an example topology 
file which assumes there are equal number of L1s and L2s and connects them to 
all routers.
You can see MeshDirCorners_* where you can see how you can connect different 
number of L1s, L2s and Directories.

Cheers,
Tushar
On Oct 13, 2020, 1:16 PM -0400, Farhad Yusufali via gem5-users 
, wrote:
Hi all,

I'm trying to simulate a multicore system that uses a Mesh XY topology, and has 
a single shared L2. However, the documentation here 
(http://www.m5sim.org/Interconnection_Network) says the following:

Mesh_*: This topology requires the number of directories to be equal to the 
number of cpus. The number of routers/switches is equal to the number of cpus 
in the system. Each router/switch is connected to one L1, one L2 (if present), 
and one Directory. The number of rows in the mesh has to be specified by 
--mesh-rows. This parameter enables the creation of non-symmetrical meshes too.

Since there needs to be one L2 per core, I assume the L2s are private. (Unless 
I'm misunderstanding and these are just NUCA slices of one shared L2?).

How can I go about using a Mesh_XY topology with a shared L2 cache?

Thanks,
Farhad
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[gem5-users] Shared L2 with Mesh XY Topology

[Farhad Yusufali via gem5-users]

Hi all,

I'm trying to simulate a multicore system that uses a Mesh XY topology, and has 
a single shared L2. However, the documentation here 
(http://www.m5sim.org/Interconnection_Network) says the following:

Mesh_*: This topology requires the number of directories to be equal to the 
number of cpus. The number of routers/switches is equal to the number of cpus 
in the system. Each router/switch is connected to one L1, one L2 (if present), 
and one Directory. The number of rows in the mesh has to be specified by 
--mesh-rows. This parameter enables the creation of non-symmetrical meshes too.

Since there needs to be one L2 per core, I assume the L2s are private. (Unless 
I'm misunderstanding and these are just NUCA slices of one shared L2?).

How can I go about using a Mesh_XY topology with a shared L2 cache?

Thanks,
Farhad
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[gem5-users] How to Set ROI In Benchmark

[Tracy Mac via gem5-users]

Hi ALL!

I try to run spec2006 in gem5 full system mode under the arm architecture
.There are some regions of interest in the application.
1. I want to run them by gem5. I don't know where in gem5 can set the start
and end points of these ROIs and the number of commands between them.
2. I found some samples in
https://www.gem5.org/documentation/general_docs/checkpoints/, but only part
of the code, I don't know where to find a more detailed script.

I would appreciate it if you could help me !
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[gem5-users] 答复: How I can notify the NVMAIN model when I use “m5 resetstats” so that the NVMAIN model can also reset the stats in its model

[Liyichao via gem5-users]

Hi Gabe：

   Thank you for your advice.

   I have seen the “Stats::registerResetCallback function in 
base/statistics.hh”, before executing m5.reset, where could I call the 
“Stats::registerResetCallback” function to register an API provided by 
NVMAIN,or is the calling of “Stats::registerResetCallback” function need to be 
in NVMAIN init process code?

李翼超（Charlie）

华为技术有限公司 Huawei Technologies Co., Ltd.
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部门：计算系统与组件开发部 [云与计算BG]
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发件人: Gabe Black [mailto:gabebl...@google.com]
发送时间: 2020年10月13日 13:11
收件人: gem5 users mailing list 
抄送: Liyichao 
主题: Re: [gem5-users] How I can notify the NVMAIN model when I use “m5 
resetstats” so that the NVMAIN model can also reset the stats in its model

Hi Liyichao, you can register a callback with the Stats::registerResetCallback 
function in base/statistics.hh.

Gabe

On Mon, Oct 12, 2020 at 7:15 PM Liyichao via gem5-users 
mailto:gem5-users@gem5.org>> wrote:
Hi All:


   When I use gem5 + O3 based on armv8 with NVMAIN ddr4 model, I want to 
know how I can notify the NVMAIN model when I use “m5 resetstats” so that the 
NVMAIN model can also reset the stats in its model, e.g. bandwidth, latency, 
because I will first run warmup for a few instrutions, when warmup finished I 
reset stats in GEM5, and then go on running the simulation parts.


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