Re: [gem5-users] Getting CPU id
Hello Everyone, I checked that pkt->req->taskId() always returned 1024 (code for unknown) in handleFill and access functions, I checked the properties of cache_blk, packet and request and there is not a cpuId. Some body could guide me in the way I have to follow to add the cpu id in the memory requests, i need this for filter the blocks. Thanks in advance. Regards On Wed, Jan 22, 2020 at 4:39 PM Richard Brown wrote: > Hello everyone, > > I am working on cache filtering. So in an architecture with several cores > each of them with its private caches (L1 and L2) and one shared LLC (L3), I > need to identify the core from which a block that will be stored in L3 > comes. > > I thought that using the method pkt->req->taskId() I might know the core > id, but I'm not sure if this method tells me the core from which the block > comes from, especially in writebacks accesses. > > I am modifying the file src/mem/cache/base.cc. > > Thanks in advance. > > Rich > ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] Getting CPU id
Hello everyone, I am working on cache filtering. So in an architecture with several cores each of them with its private caches (L1 and L2) and one shared LLC (L3), I need to identify the core from which a block that will be stored in L3 comes. I thought that using the method pkt->req->taskId() I might know the core id, but I'm not sure if this method tells me the core from which the block comes from, especially in writebacks accesses. I am modifying the file src/mem/cache/base.cc. Thanks in advance. Rich ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Snoop filter panic when bypassing blocks to MM
Hi everyone,
I am getting similar issues with my implementation. I am getting a panic
error when I bypass a block from private level to main memory, I also
asumed a block is written to public level only from private level
victimizing and does not from main memory filling.
Any suggestion? Thanks in advance
Rich
On Sun, Sep 15, 2019 at 7:00 PM Esteban Badilla
wrote:
> Hello everyone,
>
> I'm trying to bypass a block from LLC (Last Level Cache, L3 in this case)
> to Main Memory with some known conditions. It means, passing directly from
> L2 [LP: Last Private Cache] to main memory, a dirty block is written a
> clean one is discarded.
>
> The main purpose is to reduce the amount of writes on the LLC, and write
> only blocks that meet a certain condition. If the condition is not met,
> the blocks are sent directly to main memory (MM).
>
> I'm using the gem5 classic memory model, setting up as "mostly exclusive".
> I am assuming that the cache memory is filled when victimizing, that is the
> blocks when going from main memory to the cache fill first the L1, when
> being victimized from L1 they are written to the L2 and finally to the L3
> when they are victimized from L2. My filter will decide based on a
> condition is the block is writting to L3 or bypassed to MM.
>
> I have modified the cache.cc file specifically the recvTimingReq function.
>
> void Cache::recvRDTimingReq(PacketPtr pkt)
> {
> if (pkt->meetCondition()) {
> DPRINTF(LPCache, "Packet %#x meet condition, forwarding it to L3\n",
> \
> pkt->getAddr());
> BaseCache::recvTimingReq(pkt);
> } else {
> assert(!pkt->cmd.isSWPrefetch());
> DPRINTF(LPCache, "Packet %#x has not meet condition, calling
> handleTimingReqMiss"\
> ", cmd: %s\n", pkt->getAddr(), pkt->cmd.toString());
> // anything that is merely forwarded pays for the forward latency and
> // the delay provided by the crossbar
>
> Cycles lat;
> CacheBlk *blk = nullptr;
>
> PacketList writebacks;
> // Note that lat is passed by reference here. The function
> // access() will set the lat value.
> access(pkt, blk, lat, writebacks);
> allocateBlock(pkt, writebacks);
> // After the evicted blocks are selected, they must be forwarded
> // to the write buffer to ensure they logically precede anything
> // happening below
> doWritebacks(writebacks, clockEdge(lat + forwardLatency));
> }
> }
>
> When I run the simulation I am getting a panic error from the
> snoop_filter.cc
>
> 172251000: system.cpu.l2cache: Sent request to RD for addr 0x422b40
> 172251000: system.cpu.l2cache: Packet 0x422b40 has not meet condition,
> calling handleTimingReqMiss, cmd: WritebackDirty
> 172505000: system.cpu.l2cache: Sent request to RD for addr 0x422b80
> 172505000: system.cpu.l2cache: Packet 0x422b80 has not meet condition,
> calling handleTimingReqMiss, cmd: WritebackDirty
> panic: panic condition (sf_item.holder & req_port).none() occurred:
> requester
> 0001
> is not a holder :( SF value
> .
> Memory Usage: 692524 KBytes
> Program aborted at tick 172525500
>
> The diagram that shows the system I am simulating is here:
> https://drive.google.com/file/d/1sZfTY4f0djUKwmyv1JDanwzO04wjwAB5/view?usp=sharing
>
> Thanks in advance for your help.
>
> --
> Regards,
> Esteban Badilla A.
> ___
> gem5-users mailing list
> gem5-users@gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
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[gem5-users] Bypassing blocks to LLC
Hello everyone, I am PhD student and new with gem5, I have a multicore system with 2 private cache levels (DL1, IL1 and L2) and 1 shared L3/LLC. I am using classic memory system, I know this model is non-inclusive, non-exclusive. For my research I need to bypass some blocks from L3, I mean when some blocks are read I want to write them to L1 and L2 and not write them in L3, and when some blocks are evicted from L2, if they are dirty, I want to write them to Main Memory and not to L3. Is it possible to bypass some blocks from L3 reading the accesses messages? I think I just need to change cache.cc, is it right? I really apreciate your help, thanks in advance. ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] Memory models possibilities
Hello everyone, I have been reading several posts in this forum and the gem5 documentation, I am new with gem5, I have to work with memory subsystem and I have already changed characteristics on main memory and cache memory as train. However I have some questions that I have not answered reading the forum: 1. gem5 has two memory models, i.e. classic and ruby. I need to change the read and write latencies, to be asymmetric for modeling an NVM memory. I know it is super easy in the classic model, but I also need to change the coherence protocol to avoid writes in some cache level, i.e the LLC is supposed to be an NVM so I do not want to always write on it. Is it possible to have asymmetric latencies with Ruby model? I tried it, but I got an error when I simulate in full-system mode, I added asymmetric latencies and stall the execution if the bank is busy, but many stalls caused an error. In classic model I do not have problems but the cache manage is fixed, I think it is a mess to change the cache manage to avoid writes in one level. 2. I need to access cache line, I need to count the modified bits. Is it possible to access cache line in both memory models? 3. I have read papers where people use NVMain with gem5, is possible to use it as cache memory only for LLC? L1 and L2 will be SRAM. 4. I have read some posts where people talk about an unified memory model for gem5, are there people working on it? Thanks in advance for any help. -- All the best Rich ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
