[gem5-users] Multiple Caches slow down simulation speed?
Hello All, I followed learning.gem5 to create an L1 cache. Than I created another (L2) cache using same code and connected the two caches using L2XBar. Now, For small test routines, the two cache configuration works perfectly. I tried to simulate kmeans (Axbench) with two cache ( L1, L2) version. I am not getting any error msgs but simulations speed is very slow for two cache version. Is it normal behavior i.e. two cache (L1, L2) version to run slower than one cache (L1) version. Muhammad Ali Akhtar Principal Design Engineer http://www.linkedin.com/in/muhammadakhtar ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Response for WritebackDirty packets (learning.gem5)
Dear Jason, Thkns for the response. Just another quick question. What if memory was busy when u call the "sendTiimingReq" for WritebackDirty packet. In insert() function, when you call memport.sendTimingReq for WritebackDirty blocks, you don't save them in blocked Packet, in case Memory is blocked and called 'sendReqRetry()" later. Muhammad Ali Akhtar Principal Design Engineer http://www.linkedin.com/in/muhammadakhtar On Tue, May 22, 2018 at 3:40 AM, Jason Lowe-Power wrote: > Hello, > > No. You should not have a response for WritebackDirty. In fact, most > (all?) writes do not have responses. See src/mem/packet.cc. ( > https://gem5.googlesource.com/public/gem5/+/master/src/mem/packet.cc#80) > Some commands have the "NeedsResponse" flag set. If so, this request will > be turned into a response by whatever memory object fulfills the request > (by calling pkt.makeResponse()). > > I hope this answers your question. > > Jason > > On Sat, May 19, 2018 at 11:38 PM Muhammad Ali Akhtar < > muhammadali...@gmail.com> wrote: > >> Hello All, >> >> Following jason's website, created my own cache. >> >> On Cache miss, I send the TimingReq to memory, and get the response, >> which I handle in "handleResponse". >> >> during HandleResponse, in case the insertion causes eviction (cache was >> full), the insert function generates another memPort.sendTimingReq(). This >> time, the pkt is WritebackDirty. However, For this TimingReq() to memory >> (WritebackDirty), we don't get any response from memory Write? >> >> My question is: >> >> Do we ever get a response from memory for packets of type >> "WritebackDirty". When I examine the simulator output, it seems that it >> moves on to next instrutions without waiting for response from memory for >> this particular request. >> >> >> Muhammad Ali Akhtar >> Principal Design Engineer >> http://www.linkedin.com/in/muhammadakhtar >> ___ >> gem5-users mailing list >> gem5-users@gem5.org >> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > > > ___ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] Response for WritebackDirty packets (learning.gem5)
Hello All, Following jason's website, created my own cache. On Cache miss, I send the TimingReq to memory, and get the response, which I handle in "handleResponse". during HandleResponse, in case the insertion causes eviction (cache was full), the insert function generates another memPort.sendTimingReq(). This time, the pkt is WritebackDirty. However, For this TimingReq() to memory (WritebackDirty), we don't get any response from memory Write? My question is: Do we ever get a response from memory for packets of type "WritebackDirty". When I examine the simulator output, it seems that it moves on to next instrutions without waiting for response from memory for this particular request. Muhammad Ali Akhtar Principal Design Engineer http://www.linkedin.com/in/muhammadakhtar ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] passing arguments to executable in SE mode.
Hello All, I am trying to run axbench on gem5 SE mode. The benchmarks (Kmeans, jpeg) require name of input / output files as command line arguments. The executable opens the input files and produces output files. In my configuration script, I don't know how to pass the arguements to my executable when I set the process.cmd *process.cmd = ['tests/test-progs/MyProgs/kmean.o']* I have tried various methods * process.cmd = ['tests/test-progs/MyProgs/kmean.o' ' 4.rgb' ' 4_out.rgb']* or * process.cmd = ['tests/test-progs/MyProgs/kmean.o 4.rgb 4_out.rgb']* but nothing seem to work Can anyone help? Muhammad Ali Akhtar Principal Design Engineer http://www.linkedin.com/in/muhammadakhtar ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] Profiling GEM5
As everyone knows, gem5 simulations take loong time. Can anyone comment on which parts of code in gem5 itself are most time consuming / computationally intensive?. e.g. Fetch Routines, Decode / Execute functions or what else? I am talking about TimingSimple x86 CPU. -- Muhammad Ali Akhtar Principal Design Engineer http://www.linkedin.com/in/muhammadakhtar ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] How to distinguish b/w Instruction and Data in L2
Hello All, My understanding of L2 / Last Level Cache is that it contains BOTH Instructions and Data. If I want to have a separate storage in L2 for Instructions and Data, any ideas how to do that? Data in L2 comes comes from RAM in form of blocks. Is there any way to distinguish the data and instruction blocks? Muhammad Ali Akhtar Principal Design Engineer http://www.linkedin.com/in/muhammadakhtar ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] Confusion about Memory Address in GEM5
Hello All, I have been following Part-II of Jason's Book, where we create a simple MemObject. In the code, our Debug flag prints out the Address of Each Memory request in the from. "Got Request for Address", pkt->Address. I created my own binary (not hello world) and using it as a process.cmd. In my binary, I am printing out the address of a variable (using printf). When I run this binary in GEM5, without any debug-flags, GEM5 successfully executes and My binary prints out the address of variable. This address remains same in multiple execution runs ( I compiled the binary as static). However, when I run the binary with debug-flags=SimpleMemobj, I was expecting that CPU will generate the request for the same Address where my variable is. But I never see my variable's address at all in "Got Request for Address", pkt->Address. Is the CPU not fetching the variables in my binary at all? if yes, than how come my binary is executing in GEM5?. Muhammad Ali Akhtar Principal Design Engineer http://www.linkedin.com/in/muhammadakhtar ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
