bootscript.rcS is the default m5 readfile file that fs_bigLITTLE.py sets at:
https://github.com/gem5/gem5/blob/05c4c2b566ce351ab217b2bd7035562aa7a76570/configs/example/arm/fs_bigLITTLE.py#L64
panic: could not open file is just the default message that gem5 gives when
that file is not found.
So,
;
> On Wed, Apr 25, 2018 at 8:51 AM, Ciro Santilli
> wrote:
>>
>> Ah, forgot to CC you.
>>
>>
>> -- Forwarded message --
>> From: Ciro Santilli
>> Date: Wed, Apr 25, 2018 at 10:15 AM
>> Subject: Re: [gem5-users] ARM big.LITTLE sim
I will be trying to reproduce this soon I hope, but in the meantime,
can you check things like:
- does /proc/cpuinfo show multiple cpus?
- do kernel boot messages show multiple cpus being brought up?
- does the problem happen for other content, or just PARSEC? E.g. you
could try to install and run
Hello,
I ran the blackscholes PARSEC benchmark on an ARM big.LITTLE configuration
with 2 big cores and 2 small cores. It seems cpus0 in the bigCluster is the
only one that has cache data according to stats.txt. The relevant entries
for the other CPUs are either missing or NaN. Do you have any ide
Hello,
I am new to GEM5 and I am wondering how to simulate an ARM big.LITTLE
architecture correctly: will using the fs.py with the big.little dtb file
simulate the architecture or should we use fs_big.LITTLE.py? If the latter,
where do we find the default bootscript.rcS file that the python script
Hi Felipe,
I'm not super familiar with the ARM model (and these weird dtb files), but
I believe the rcS file that the simulator is looking for is actually on the
host. This somewhat describes how FS simualation works:
http://gem5.org/Running_gem5#Basic_Operation. The rcS file is a script
which is
Hi everyone,
I saw a commit form 3 weeks ago "arm, config: Add an example ARM big.LITTLE(tm)
configuration script" and tried to run it.I create the
armv8_gem5_v1_big_little_2_2.dtb and compiled the vmlinux for the kernel 4.3
as instructed here:
http://www.gem5.org/ARM_Linux_Kernel
I use this co
