Hello,
I am trying to compile a PIMProcess function in gem5-based PIMSim. The function
includes takeOverFrom() which is supposed to let PIM cores take over all the
contents from host-side CPU.
These are the lines for pim_cpu configuration in the memory, where I have added
an interrupt
Hi all,
I'm writing because I'm trying to run a relatively simple, but
memory-intensive C microbenchmark in SE mode. In particular, it allocates
and randomly fills a 2MB array, then performs *n* random accesses to the
array and increments the value.
The program outputs that it is increasing the
Hello,
I am using repository cloned from https://gem5.googlesource.com/public/gem5 as
of 17/06/21.
I am using the following command:
./build/X86/gem5.opt configs/example/se.py --num-cpus=16 --num-dir=16
--cpu-type=DerivO3CPU --sys-clock=2GHz --topology=Mesh_XY --mesh-rows=4
--num-l2caches=16
Hi Deepak,
I guess, if you care about more accurate implementation you might have to
add new instruction in the ISA or maybe adding a new gem5 pseudo
instruction will be easier.
Also, according to my understanding, you might be able to use the cache
invalidation/flushing related functionality in
Hi,
I'm doing some experiments using gem5 FS mode for x86.
In the FS mode I'm running a custom OS written for the requirements of
my experiment. I have added a PIO device to the x86 system which
responds to reads and writes to an address range. In the OS I have
mapped this device to a range in
Hi Zhang,
I have not tested but perhaps using one of the --cpu-type options listed in the
error message would fix your issue:
"(choose from 'O3_ARM_v7a_3', 'TimingSimpleCPU', 'ex5_big', 'DerivO3CPU',
'TraceCPU')"
O3_ARM_v7a_3 or DerivO3CPU are the closest options to "O3CPU".
Best,
Gabriel
