[gem5-users] How to configure three level caches with different cache line size?

etween the cache line size of gem5 system and that of each level cache. I would appreciate if some one can shed some light on this. Best regards, Will = $ build/ARM/gem5.opt configs/example/BCse.py --caches --l1i_size=4kB --l1i

[gem5-users] Could cache connected without bus?

Hello, I'v attempted to connect two caches without bus but I got error. Does anybody knows whether I could connect two memory objects directly, i.e without bus? I would appreciate if some one can shed some light on this. Best regards, Will___ gem5-

Re: [gem5-users] Could cache connected without bus?

es the way of using ports and packet best fits into my situation? I'm new to gem5 and many thanks. Best regrads, Will At 2015-07-16 22:59:14, "Andreas Hansson" wrote: Hi Will, In general you should be fine to connect two caches back to back. The question is, why would

[gem5-users] Cache model in gem5

Hi all, I'm trying to model a new cache with a separate tagging mechanism. Does someone knows whether I could use the cache model of gem5 as a RAM only and totally ignore the tag function? I'm wondering which will be done faster, modify the current cache model or rewrite it.

[gem5-users] How to add additional port to memory?

Hello, I've managed to add an additional port to the cache memory but failed. Does anybody knows how to add additional port to memory and assemble it in the configuration script? I would appreciate if some one can shed some light on this. Best regards,

[gem5-users] Problem in building cross compiler for MIPS using crosstools-ng

appreciate if some one can shed some light on this. Best regards, Will == $ build/MIPS/gem5.debug configs/example/se.py -c ~/hello gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright

[gem5-users] CPI in TimingSimpleCPU model with memory systems

incredibly high, 2.6 for 403.gcc and 5.8 for 429.mcf, for example. Did I miscalculated the CPI which was total cycles divided by sim_ops? If so, what is the right way to estimate the CPI with cache system? I would appreciate for your answer. Regards, Will

[gem5-users] Branch Predictor

Hello, I need a group of statistics about performance of ARM under different cache size but I don't know much more about the branch predictor. I wonder what is the reasonable configuration for BTB and branch predictor in ARM. Does anyone has some ideas upon that? I would appreciate for your ans

[gem5-users] About Prefetchers in Cache

cache systems? For example, what is the reasonalbe queue_size in QueuedPrefetcher with 4K and 32K L1 cache respectively. Besides, I wonder about the hardware overheads of these prefetchers, such as how much additional memory will be used, and whether there exists some reference material about

[gem5-users] About Benchmarking

Hello, I use SPEC2006 for performance evaluation these days and I'd to ask what is the proper server benchmark suite using gem5. Your reply will be higly appreciated! Thanks, Wil___ gem5-users mailing list gem5-users@gem5.org http://m5sim.or

[gem5-users] Problem about simulating Moby benchmarks

Hi, I have downloaded the Moby benchmarks and all necessary files including andriod kernel, disk image, sd-card image and boot scripts. However, the gem5 just outputs following warning messages after simulating for a really long time. The telnet/m5term shown nothing. The terminal keeps these f

Re: [gem5-users] Problem about simulating Moby benchmarks

er. In the next week or so we should also be able to upload instructions for Marshmallow. Andreas From: gem5-users on behalf of Will Reply-To: gem5 users mailing list Date: Saturday, 8 October 2016 at 03:30 To: gem5-users Subject: [gem5-users] Problem about simulating Moby benchmarks Hi

[gem5-users] Timing about Branch Instruction in MinorCPU

Hello, I'v been trying to conduct some simulation using MinorCPU and got confused about the timing when branch taken. In default configuration, I found that there are about 5 clcok cycles idle when a branch prediction is correct, while there are about 11 clcok cycles idle when a branch predi

[gem5-users] Source and Destination Registers in StaticInst

Hello, I am doing some instruction dependency check related work using the decoder and static inst. in gem5 (built for ARM). However, I found that for some instructions, the member `_destRegIdx` and `_srcRegIdx` in `class StaticInst` can't give the right destination and source registers. For e