-users] [ARM system] Question about the cleassic cache system
Assymetric cache hierachies should work in the classic memory system.
The problem you run into is data corruption (the reported addresses are most
likely invalid) but it's hard to say anything about the cause of it without
more info
Assymetric cache hierachies should work in the classic memory system.
The problem you run into is data corruption (the reported addresses are
most likely invalid) but it's hard to say anything about the cause of it
without more info.
One quick way to test your assymetric memory hierarchy would
Hi, Ciro
Thank you for sharing this.
I saw Jason initiated a code review for Tiago's update last month.
So I guess this work will be added to the main repository soon.
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I'm not sure about the cache hierarchy issue.
But about Ruby support, I don't think there's any known ARM specific problem,
and ARM contributors have been specifically pushing Ruby recently, see e.g. see
Tiago's CHI announcement: https://www.gem5.org/2020/05/29/flexible-cache.html
