[gem5-users] Re: [ARM system] Question about the cleassic cache system
HI, Nikos Thank you very much. I will try to use these two configuration files to test my cache structures. Best Regards Boya -Original Message- From: Nikos Nikoleris [mailto:nikos.nikole...@arm.com] Sent: 2020年8月24日 10:48 To: gem5 users mailing list Cc: chenboya Subject: Re: [gem5-users] [ARM system] Question about the cleassic cache system Assymetric cache hierachies should work in the classic memory system. The problem you run into is data corruption (the reported addresses are most likely invalid) but it's hard to say anything about the cause of it without more info. One quick way to test your assymetric memory hierarchy would be to use memcheck and memtest. In configs/example you will find 2 example scripts memcheck.py and memtest.py that simulate systems with any cache hierachy and traffic generators while performing basic tests (e.g., correct false sharing). It would be interesting to see if both memtest and memcheck work when configured with a cache hierarchy that ressembles yours. To run memcheck you could use ./build/ARM/gem5.opt configs/example/memcheck.py but you will need to change the cache hierarchy (-c argument) and the number of testers (-t argument) to make it look more like your system. Nikos On 21/08/2020 12:50, chenboya via gem5-users wrote: > > Hi, ALL > > I'm doing some design space exploration work using GEM5. > My work is exploring the different cache structures, using ARM cores, classic > cache structure, and use parsec-3.0 to simulate the multi-core performance. > My system has 4-level caches, every level using L2XBar to connect. Use big > little clusters, every cluster has the L2 cache shared by cores in the > cluster. > > Now I meet some problems in the cache structure as below: > > 1. If I connect all the clusters to one L3 cache then connect to one L4 > cache, then the full system run is OK. > > 2. If I connect big clusters directly to L4 cache, other clusters connect to > one L3 cache then connect to L4 cache, will see the error below (in > system.terminal): > > /home/root/parsec-3.0 > [0.831546] Unable to handle kernel paging request at virtual address > aaecd674a901 > [0.831563] Unable to handle kernel paging request at virtual address > aaecde551e41 > [0.831573] Unable to handle kernel paging request at virtual address > aaecde527e41 > > 3. If I connect big clusters to one L3, other clusters to another L3, and > these two L3 caches connect to L4 cache, will have SAME error. > > If change all cores to Atomic CPU, will not have the page fault error. > > All the 3 experiments use same image (the aarch64-ubuntu-trusty-headless.img > add parsec), and use automatically generated dtb file. > When instantiation, the 3 structures can be generated successfully. > > So are there any limits about classic mode memory system for ARM? For > example, cannot support more than one L3 caches or asymmetry hierarchies? > Should I using Ruby to replace it? > > In Andreas Hansson's 2015 slides, he said Ruby has some compatibility > problems for ARM. > FSConfig.py also warns that Ruby on ARM is not working properly yet. Has > those problems solved now? > > > -Original Message- > From: gem5-users-requ...@gem5.org [mailto:gem5-users-requ...@gem5.org] > Sent: 2020年8月21日 8:23 > To: gem5-users@gem5.org > Subject: gem5-users Digest, Vol 169, Issue 52 > > Send gem5-users mailing list submissions to > gem5-users@gem5.org > > To subscribe or unsubscribe via email, send a message with subject or body > 'help' to > gem5-users-requ...@gem5.org > > You can reach the person managing the list at > gem5-users-ow...@gem5.org > > When replying, please edit your Subject line so it is more specific than "Re: > Contents of gem5-users digest..." > > Today's Topics: > > 1. Re: KVM does not work (chenboya) > 2. Re: Functional read failed while using pthread lock in program >(Jason Lowe-Power) > 3. Packet request send directly to memory without searching in cache >(Muhammad Aamir) > 4. issues in FS mode with TimingSimpleCPU+Multicore (JASPINDER > KAUR) > > > -- > > Date: Thu, 20 Aug 2020 14:55:05 + > From: chenboya > Subject: [gem5-users] Re: KVM does not work > To: "gem5-users@gem5.org" > Message-ID: > Content-Type: text/plain; charset="utf-8" > > There are some GIC issues about running the KVM mode, fortunately an engineer > had given the solution. > Here are some discussions about the KVM mode for ARM. > > https://gem5.atlassian.net/browse/GEM5-547 > > > -Original Message- > From: gem5-users-req
[gem5-users] Re: [ARM system] Question about the cleassic cache system
Assymetric cache hierachies should work in the classic memory system. The problem you run into is data corruption (the reported addresses are most likely invalid) but it's hard to say anything about the cause of it without more info. One quick way to test your assymetric memory hierarchy would be to use memcheck and memtest. In configs/example you will find 2 example scripts memcheck.py and memtest.py that simulate systems with any cache hierachy and traffic generators while performing basic tests (e.g., correct false sharing). It would be interesting to see if both memtest and memcheck work when configured with a cache hierarchy that ressembles yours. To run memcheck you could use ./build/ARM/gem5.opt configs/example/memcheck.py but you will need to change the cache hierarchy (-c argument) and the number of testers (-t argument) to make it look more like your system. Nikos On 21/08/2020 12:50, chenboya via gem5-users wrote: Hi, ALL I'm doing some design space exploration work using GEM5. My work is exploring the different cache structures, using ARM cores, classic cache structure, and use parsec-3.0 to simulate the multi-core performance. My system has 4-level caches, every level using L2XBar to connect. Use big little clusters, every cluster has the L2 cache shared by cores in the cluster. Now I meet some problems in the cache structure as below: 1. If I connect all the clusters to one L3 cache then connect to one L4 cache, then the full system run is OK. 2. If I connect big clusters directly to L4 cache, other clusters connect to one L3 cache then connect to L4 cache, will see the error below (in system.terminal): /home/root/parsec-3.0 [0.831546] Unable to handle kernel paging request at virtual address aaecd674a901 [0.831563] Unable to handle kernel paging request at virtual address aaecde551e41 [0.831573] Unable to handle kernel paging request at virtual address aaecde527e41 3. If I connect big clusters to one L3, other clusters to another L3, and these two L3 caches connect to L4 cache, will have SAME error. If change all cores to Atomic CPU, will not have the page fault error. All the 3 experiments use same image (the aarch64-ubuntu-trusty-headless.img add parsec), and use automatically generated dtb file. When instantiation, the 3 structures can be generated successfully. So are there any limits about classic mode memory system for ARM? For example, cannot support more than one L3 caches or asymmetry hierarchies? Should I using Ruby to replace it? In Andreas Hansson's 2015 slides, he said Ruby has some compatibility problems for ARM. FSConfig.py also warns that Ruby on ARM is not working properly yet. Has those problems solved now? -Original Message- From: gem5-users-requ...@gem5.org [mailto:gem5-users-requ...@gem5.org] Sent: 2020年8月21日 8:23 To: gem5-users@gem5.org Subject: gem5-users Digest, Vol 169, Issue 52 Send gem5-users mailing list submissions to gem5-users@gem5.org To subscribe or unsubscribe via email, send a message with subject or body 'help' to gem5-users-requ...@gem5.org You can reach the person managing the list at gem5-users-ow...@gem5.org When replying, please edit your Subject line so it is more specific than "Re: Contents of gem5-users digest..." Today's Topics: 1. Re: KVM does not work (chenboya) 2. Re: Functional read failed while using pthread lock in program (Jason Lowe-Power) 3. Packet request send directly to memory without searching in cache (Muhammad Aamir) 4. issues in FS mode with TimingSimpleCPU+Multicore (JASPINDER KAUR) -- Date: Thu, 20 Aug 2020 14:55:05 + From: chenboya Subject: [gem5-users] Re: KVM does not work To: "gem5-users@gem5.org" Message-ID: Content-Type: text/plain; charset="utf-8" There are some GIC issues about running the KVM mode, fortunately an engineer had given the solution. Here are some discussions about the KVM mode for ARM. https://gem5.atlassian.net/browse/GEM5-547 -Original Message- From: gem5-users-requ...@gem5.org [mailto:gem5-users-requ...@gem5.org] Sent: 2020年8月12日 9:46 To: gem5-users@gem5.org Subject: gem5-users Digest, Vol 169, Issue 31 Send gem5-users mailing list submissions to gem5-users@gem5.org To subscribe or unsubscribe via email, send a message with subject or body 'help' to gem5-users-requ...@gem5.org You can reach the person managing the list at gem5-users-ow...@gem5.org When replying, please edit your Subject line so it is more specific than "Re: Contents of gem5-users digest..." Today's Topics: 1. KVM does not work (毛允飞) 2. Re: KVM does not work (Giacomo Travaglini) -- Date: Wed, 12 Aug 2020 16:40:48 +0800 From: 毛允飞 Subject: [gem5-users] KVM does not work To: gem5-users@gem5.org Message-ID: Content-Type:
[gem5-users] Re: [ARM system] Question about the cleassic cache system
Hi, Ciro Thank you for sharing this. I saw Jason initiated a code review for Tiago's update last month. So I guess this work will be added to the main repository soon. ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] Re: [ARM system] Question about the cleassic cache system
I'm not sure about the cache hierarchy issue. But about Ruby support, I don't think there's any known ARM specific problem, and ARM contributors have been specifically pushing Ruby recently, see e.g. see Tiago's CHI announcement: https://www.gem5.org/2020/05/29/flexible-cache.html From: chenboya via gem5-users Sent: Friday, August 21, 2020 10:50 AM To: gem5-users@gem5.org Cc: chenboya Subject: [gem5-users] [ARM system] Question about the cleassic cache system Hi, ALL I'm doing some design space exploration work using GEM5. My work is exploring the different cache structures, using ARM cores, classic cache structure, and use parsec-3.0 to simulate the multi-core performance. My system has 4-level caches, every level using L2XBar to connect. Use big little clusters, every cluster has the L2 cache shared by cores in the cluster. Now I meet some problems in the cache structure as below: 1. If I connect all the clusters to one L3 cache then connect to one L4 cache, then the full system run is OK. 2. If I connect big clusters directly to L4 cache, other clusters connect to one L3 cache then connect to L4 cache, will see the error below (in system.terminal): /home/root/parsec-3.0 [0.831546] Unable to handle kernel paging request at virtual address aaecd674a901 [0.831563] Unable to handle kernel paging request at virtual address aaecde551e41 [0.831573] Unable to handle kernel paging request at virtual address aaecde527e41 3. If I connect big clusters to one L3, other clusters to another L3, and these two L3 caches connect to L4 cache, will have SAME error. If change all cores to Atomic CPU, will not have the page fault error. All the 3 experiments use same image (the aarch64-ubuntu-trusty-headless.img add parsec), and use automatically generated dtb file. When instantiation, the 3 structures can be generated successfully. So are there any limits about classic mode memory system for ARM? For example, cannot support more than one L3 caches or asymmetry hierarchies? Should I using Ruby to replace it? In Andreas Hansson's 2015 slides, he said Ruby has some compatibility problems for ARM. FSConfig.py also warns that Ruby on ARM is not working properly yet. Has those problems solved now? -Original Message- From: gem5-users-requ...@gem5.org [mailto:gem5-users-requ...@gem5.org] Sent: 2020年8月21日 8:23 To: gem5-users@gem5.org Subject: gem5-users Digest, Vol 169, Issue 52 Send gem5-users mailing list submissions to gem5-users@gem5.org To subscribe or unsubscribe via email, send a message with subject or body 'help' to gem5-users-requ...@gem5.org You can reach the person managing the list at gem5-users-ow...@gem5.org When replying, please edit your Subject line so it is more specific than "Re: Contents of gem5-users digest..." Today's Topics: 1. Re: KVM does not work (chenboya) 2. Re: Functional read failed while using pthread lock in program (Jason Lowe-Power) 3. Packet request send directly to memory without searching in cache (Muhammad Aamir) 4. issues in FS mode with TimingSimpleCPU+Multicore (JASPINDER KAUR) -- Date: Thu, 20 Aug 2020 14:55:05 + From: chenboya Subject: [gem5-users] Re: KVM does not work To: "gem5-users@gem5.org" Message-ID: Content-Type: text/plain; charset="utf-8" There are some GIC issues about running the KVM mode, fortunately an engineer had given the solution. Here are some discussions about the KVM mode for ARM. https://gem5.atlassian.net/browse/GEM5-547 -Original Message- From: gem5-users-requ...@gem5.org [mailto:gem5-users-requ...@gem5.org] Sent: 2020年8月12日 9:46 To: gem5-users@gem5.org Subject: gem5-users Digest, Vol 169, Issue 31 Send gem5-users mailing list submissions to gem5-users@gem5.org To subscribe or unsubscribe via email, send a message with subject or body 'help' to gem5-users-requ...@gem5.org You can reach the person managing the list at gem5-users-ow...@gem5.org When replying, please edit your Subject line so it is more specific than "Re: Contents of gem5-users digest..." Today's Topics: 1. KVM does not work (毛允飞) 2. Re: KVM does not work (Giacomo Travaglini) -- Date: Wed, 12 Aug 2020 16:40:48 +0800 From: 毛允飞 Subject: [gem5-users] KVM does not work To: gem5-users@gem5.org Message-ID: Content-Type: multipart/alternative; boundary="c0216705acaa2553" --c0216705acaa2553 Content-Type: text/plain; charset="UTF-8" Hi All I run the fs_bigLITTLE.py script in gem5, but there is no information in the m5term console. I don't know what went wrong, INFO: Global frequency set at 1 ticks per second info: Simulated platform: VExpress_GEM5_V1 info: kernel located at:
