Re: [Ghdl-discuss] Huge simulation speed slowdown

2016-03-09 Thread Tristan Gingold
On 09/03/16 21:37, Adrien Prost-Boucle wrote: Hi, I have a VHDL design that GHDL simulates at a speed of only one or 2 clock cycles per second. The same design, same VHDL files, is simulated by Xilinx Vivado 2015.3 at a speed of 400 clock cycles per second. For all other designs I have and/or

Re: [Ghdl-discuss] Huge simulation speed slowdown (with llvm)

2016-03-09 Thread David Koontz
> On 10/03/2016, at 10:50 am, Lehmann, Patrick > wrote: > > Hello Adrien, > > Can you give some information on your used GHDL installation? > - version number or source code checkout date > - backend: gcc, llvm, mcode > > Are you exporting the simulation

Re: [Ghdl-discuss] Huge simulation speed slowdown

2016-03-09 Thread Lehmann, Patrick
Hello Adrien, Please compare it to the LLVM backend, because LLVM has several good optimization options. I just wanted to make sure that your GHDL is an almost up-to-date 0.34dev built and not 0.31 or so :). I think xSim can use multi-threading in simulation, too. Otherwise I cannot explain,

Re: [Ghdl-discuss] Huge simulation speed slowdown

2016-03-09 Thread jim
Does it have Xilinx cores or memory models which may get special handling in Xilinx tools Sent from my Sprint Samsung Galaxy Note5. Original message From: Adrien Prost-Boucle Date: 3/10/2016 6:11 AM (GMT+07:00) To: ghdl-discuss@gna.org

Re: [Ghdl-discuss] Huge simulation speed slowdown

2016-03-09 Thread Adrien Prost-Boucle
Hi Patrick, Good questions, sorry for having forgotten that. I used both gcc and mcode backends. mcode pulled from git this afternoon, gcc older by a few weeks. I don't have the exact commit IDs right now, that's in the lab. I can provide them if needed and test with latest gcc and llvm backends

Re: [Ghdl-discuss] Huge simulation speed slowdown

2016-03-09 Thread Lehmann, Patrick
Hello Adrien, Can you give some information on your used GHDL installation? - version number or source code checkout date - backend: gcc, llvm, mcode Are you exporting the simulation results as a waveform dump file? E.g. vcd, fst, ghw, ... => This has a high performance impact, caused by string

[Ghdl-discuss] Huge simulation speed slowdown

2016-03-09 Thread Adrien Prost-Boucle
Hi, I have a VHDL design that GHDL simulates at a speed of only one or 2 clock cycles per second. The same design, same VHDL files, is simulated by Xilinx Vivado 2015.3 at a speed of 400 clock cycles per second. For all other designs I have and/or generate, GHDL is always noticeably faster that