Hi,
Thanks Tristan, GHDL no longer chokes on my dirty design.
That rocks!
Simulation speed:
1740 cycles/s with gcc backend, default settings
2450 cycles/s vith -O2 (+35s analysis/elabo time, -91s simu time)
1560 cycles/s with llvm backend, default settings
1560 cycles/s with -O2 (no change???
On 15/03/16 00:40, Adrien Prost-Boucle wrote:
Hi,
Waow.
I know this isn't the best mux code ever, but I didn't imagine it could
be that painful...
Adrien,
this issue is now fixed by my latest patches.
There was a threshold effect that prevented memory reuse and therefore
slowed down
Hi,
I'm answering to David's message from the webmail in the hope that my message
is sent correctly this way...
Thanks a lot David for your analysis of the VHDL code I sent.
I can comment on several points.
1) About possibility to reduce the number of remaining concatenantions
The current
I had gone through and characterized your design looking for anomalies, also
looked at the previous one you had reported and Tristan responded to about
ghdl's slow-ish concatenation. The idea was to look for things before the
effort of profiling.
I found those 5,204 input vectors (bytes) that
On Tue, 2016-03-15 at 00:40 +0100, Adrien Prost-Boucle wrote:
> Hi,
>
> I had another idea.
>
> Re-evaluating the entire mux expressions is a heavy task.
> So would it be possible to re-evaluate only the sub-expressions that
> have changed? Including, for function calls, only those that have no
On 09/03/16 21:37, Adrien Prost-Boucle wrote:
Hi,
I have a VHDL design that GHDL simulates at a speed of only one or 2
clock cycles per second. The same design, same VHDL files, is simulated
by Xilinx Vivado 2015.3 at a speed of 400 clock cycles per second.
For all other designs I have and/or
On 09/03/16 21:37, Adrien Prost-Boucle wrote:
Hi,
I have a VHDL design that GHDL simulates at a speed of only one or 2
clock cycles per second. The same design, same VHDL files, is simulated
by Xilinx Vivado 2015.3 at a speed of 400 clock cycles per second.
For all other designs I have and/or
oun...@gna.org] On Behalf Of Adrien
> Prost-Boucle
> Sent: Wednesday, March 09, 2016 9:38 PM
> To: GHDL discuss list <ghdl-discuss@gna.org>
> Subject: [Ghdl-discuss] Huge simulation speed slowdown
>
> Hi,
>
> I have a VHDL design that GHDL simulates at a speed of
016 12:12 AM
To: ghdl-discuss@gna.org
Subject: Re: [Ghdl-discuss] Huge simulation speed slowdown
Hi Patrick,
Good questions, sorry for having forgotten that.
I used both gcc and mcode backends.
mcode pulled from git this afternoon, gcc older by a few weeks.
I don't have the exact commit IDs
na.org Subject: Re:
[Ghdl-discuss] Huge simulation speed slowdown
Hi Patrick,
Good questions, sorry for having forgotten that.
I used both gcc and mcode backends.
mcode pulled from git this afternoon, gcc older by a few weeks.
I don't have the exact commit IDs right now, that's in the lab.
I can p
ssage-
> From: Ghdl-discuss [mailto:ghdl-discuss-boun...@gna.org] On Behalf Of Adrien
> Prost-Boucle
> Sent: Wednesday, March 09, 2016 9:38 PM
> To: GHDL discuss list <ghdl-discuss@gna.org>
> Subject: [Ghdl-discuss] Huge simulation speed slowdown
>
> Hi,
&g
uss [mailto:ghdl-discuss-boun...@gna.org] On Behalf Of Adrien
Prost-Boucle
Sent: Wednesday, March 09, 2016 9:38 PM
To: GHDL discuss list <ghdl-discuss@gna.org>
Subject: [Ghdl-discuss] Huge simulation speed slowdown
Hi,
I have a VHDL design that GHDL simulates at a speed of only one or 2 clock
cycles p
Hi,
I have a VHDL design that GHDL simulates at a speed of only one or 2
clock cycles per second. The same design, same VHDL files, is simulated
by Xilinx Vivado 2015.3 at a speed of 400 clock cycles per second.
For all other designs I have and/or generate, GHDL is always noticeably
faster that
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