AW: Re: Why would LE not trap?

>> isn't there a third place where LE options come from? > >Yes, absolutely, there are installation defaults. Several sets: CICS, POSIX, I >have forgotten what all. I guess that is part of my question here: aren't they >defaults? Is there any way installation "stuff" of some sort overrides

Re: Can AMODE 31 C/C++ get a signal on a S0C1/4 in AMODE 64 assembler?

Once again: is my understanding correct, that LE cannot handle the 64 bit situation in the SDWA correctly, and you repair this by modifying the contents of the SDWA in your ESTAE routine, before percolating to LE, that is: you are "fooling" LE, this way repairing (?) the problem that LE has?

Re: SPF Panels for TCP/IP (was HSM Query command) - EZANS RFE

On 8/23/2017 1:27 AM, Mike Wawiorko wrote: This is my RFE. Currently 75 votes supporting it but only uncommitted candidate. Can we get it to over a hundred votes? What happens when you reach 100 votes? -- Phoenix Software International Edward E. Jaffe Chief Technology Officer 831 Parkview

Re: Why would LE not trap?

That is my impression also. I was wondering if anyone here knew anything different, or perhaps a fourth source that overrode the other three. Charles -Original Message- From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On Behalf Of Peter Hunkeler Sent: Sunday, August

Re: Can AMODE 31 C/C++ get a signal on a S0C1/4 in AMODE 64 assembler?

There is only one apparent "error" -- the original S0C4 in AMODE 64 assembler. LE is silent as to what its problem is. There is no LE error message, just the usual sorts of S0C4 messages from MVS. Yeah, my own LE error handler might help ... I am thinking of trying setting AMODE 31 in the SDWA

Re: Why would LE not trap?

And to close the loop: Why would LE not trap? Because it's AMODE 31 LE and the S0C4 happened in AMODE 64. Charles -Original Message- From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On Behalf Of Charles Mills Sent: Friday, August 25, 2017 4:08 PM To:

Re: Can AMODE 31 C/C++ get a signal on a S0C1/4 in AMODE 64 assembler?

Yes, your understanding is correct. Just to clarify one thing, the assembler routine is not AMODE 64 at the module level. It is always entered and exits (assuming no S0C4s!) in AMODE 31. But it uses SAM64 to access above the bar storage, and then SAM31 to get back again. Everything I am doing

Re: Create subtask w/out a load module?

As has been mentioned, IDENTIFY can do what is asked for. So can binding the load module with appropriate alias(es). But also so can writing code so that you attach the same entry name but the parameter data passed to the attached module tells the code where to branch to (whether by a code or

Re: Can AMODE 31 C/C++ get a signal on a S0C1/4 in AMODE 64 assembler?

> I am thinking of trying setting AMODE 31 in the SDWA PSW16 (going back to my > own ESTAE ahead of LE's) and seeing if that helps. It does indeed! Seems to solve the problem. LE is happy. It interprets all of the registers as 31-bit addresses, but most of them are anyway. Need to work on this

Re: Can AMODE 31 C/C++ get a signal on a S0C1/4 in AMODE 64 assembler?

can the AMODE 64 Assembler routine establish its own ESTAE routine which takes precedence over LE? Don't know, if there is already ESPIE / ESTAE support for the 64 bit case (don't know much about AMODE 64 altogether). I believe that with AMODE 31 this should be possible (establishing another

Re: Cobol Help

David, All, I have to think about hardening a COBOL written STC performing security calls. This my main reason for the question regarding the I/O error handler, it makes sense to move the I/O into an assembler module or C.. Scott On Fri, Aug 25, 2017 at 12:07 AM David Crayford

Re: Why would LE not trap?

> But why do you want your ESTAE to do when the abend is unrecoverable Short answer: to free some system-owned ECSA that we allocated. Charles -Original Message- From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On Behalf Of Binyamin Dissen Sent: Saturday, August

Re: Why would LE not trap?

Well, I now know a little more and am a little mystified. I had this sudden thought that perhaps the difference at the one customer was that the two S0C4's we have experienced there would have happened in assembler code running AMODE 64. (The C++ code is all AMODE 31.) So today I coded up some

Re: Why would LE not trap?

Sorry. I meant "In what AMODE will a percolation routine be entered?" but I guess the answer is "in the AMODE of its ESTAE (but not 24)." Charles -Original Message- From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On Behalf Of Jim Mulder Sent: Sunday, August 27,

Re: z14 and zBX

On 8/22/2017 4:27 AM, R.S. wrote: The above is some simplification, however I heard A LOT OF zBX, saw a lot of presentations, and  IBMers never ever convinced me the zBX is something more than LAN-attached rack. zBX was a mistake. Every company makes them. -- Phoenix Software International

Re: z14 and zBX

edja...@phoenixsoftware.com (Ed Jaffe) writes: > On 8/22/2017 4:27 AM, R.S. wrote: >> >> The above is some simplification, however I heard A LOT OF zBX, saw >> a lot of presentations, and  IBMers never ever convinced me the zBX >> is something more than LAN-attached rack. > > zBX was a mistake.

Re: Message IRX0006I running an edit macro CLIST

One last comment. We run the same software and have not had an issue in three different SYSPLEX environments. I looked to the most recent versions of the software we have. The JEM CLIST is shipped that way from the vendor. Very interesting. BROWSESYSI.JOBSCAN.R790.AJJSCLST.HS(JEM) -

AW: Re: Why would LE not trap?

is it possible to Set the Amode to 31 in the estae Routine? the estae Routine should be able to detect that the Problem occured while executing in Amode 64?? Gesendet mit der Telekom Mail App

Re: Why would LE not trap?

The recovery routine is entered in the AMODE of the ESTAE(X) macro. Yes, it should be able to determine the AMODE of the error from the z/Arch PSW but I have not tried that yet. A retry routine is entered -- not sure of the default -- but you can control the AMODE with SETRP. A percolation

Re: Why would LE not trap?

AMODE ESTAE-type recovery exits receive control in the AMODE that was current at the time-of-set (time-of-PC AMODE for ARRs) with the following exceptions: ?ARR, IEAARR, and ESTAEX exits receive control in AMODE 31 instead of AMODE 24 when established for AMODE 24 programs Jim Mulder z/OS

Can AMODE 31 C/C++ get a signal on a S0C1/4 in AMODE 64 assembler?

Starting a new thread. Here is the fundamental problem. (If you were following the other thread -- I am now testing without my own ESTAE, just vanilla LE.) An AMODE 31 C++ program provides a signal handler. It will get driven for your basic S0C1 or S0C4. But if the C++ program calls an assembler

Re: Message IRX0006I running an edit macro CLIST

I never knew of this restriction on edit macros. Looking through the same library for others, I find a few other CLISTs that have 'PROC' at the top; most do not. It looks like JEM was constructed to allow an alternate load library to be specified on invocation for testing purposes. I removed

Re: z14 and zBX

l...@garlic.com (Anne & Lynn Wheeler) writes: > Old email about doing CP (vm370) internals class and > meetings with NSF about connecting NSF supercomputer centers > http://www.garlic.com/~lynn/2011h.html#email850930 > http://www.garlic.com/~lynn/2011h.html#email851114 >

Re: Looking for mainframe shops Lexington/Cincinnati

Fifth Third Bank is one of the biggest in Cincinnati, as well as their spin-off Vantiv Corp., up in the northeastern suburbs. LexisNexis is further north, near Dayton. sas On Sat, Aug 26, 2017 at 10:59 PM, Joel M Ivey wrote: > Would appreciate info on zos shops in Lexington

Re: Why would LE not trap?

Then you cannot completely rely on ESTAE(X). I would suggest reading on RESMGR. On Sun, 27 Aug 2017 12:59:20 -0400 Charles Mills wrote: :>> But why do you want your ESTAE to do when the abend is unrecoverable :> :>Short answer: to free some system-owned ECSA that we

AW: Can AMODE 31 C/C++ get a signal on a S0C1/4 in AMODE 64 assembler?

is my understsnding correct that the LE Error handler is activated but has Problems because of the 64 Bit Situation in the Ceecib and then the non handled 0c4 occurs? If so, would it help if you used your own LE Error handler? or modify the Ceecib contents in a sensible way before percolating

Re: Message IRX0006I running an edit macro CLIST

There are two parms for this Clist: DSJNAME and PARMSTR. How is JEM invoked? (E.g. it could be invoked as "TSO JEM HLQ.DSJN1.THEREST MACPARM2".) On 27/08/2017 18:25, Feller, Paul wrote: > One last comment. We run the same software and have not had an issue in > three different SYSPLEX

Re: SPF Panels for TCP/IP (was HSM Query command) - EZANS RFE

> On Aug 27, 2017, at 5:10 PM, Ed Jaffe wrote: > > On 8/23/2017 1:27 AM, Mike Wawiorko wrote: >> This is my RFE. >> >> Currently 75 votes supporting it but only uncommitted candidate. >> Can we get it to over a hundred votes? > > What happens when you reach 100

Re: Message IRX0006I running an edit macro CLIST

Typically the user is EDITing a PDS Member with JCL and enters JEM on the command line Lizette > -Original Message- > From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On > Behalf Of CM Poncelet > Sent: Sunday, August 27, 2017 7:11 PM > To: IBM-MAIN@LISTSERV.UA.EDU

Re: Message IRX0006I running an edit macro CLIST

The reason Clist comments do not need '*/' closing chars is that Clist lines ending with only a space imply 'end-of-line'. They would need to end with a '+' or '-' char to indicate they continued on to next line. REXX requires both '/*' and '*/' to indicate start and end of comments (same as in