== Series Details ==
Series: series starting with [1/3] drm/rect: Return scaling factor and error
code separately
URL : https://patchwork.freedesktop.org/series/66935/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6922_full -> Patchwork_14458_full
tree: git://anongit.freedesktop.org/drm-intel drm-intel-next-queued
head: 4bb6a9d5d9a8289673c4cb0786d44be8a63c21db
commit: 1af22383829864299102ca0c2eab458f755a9971 [5/7] drm/i915/display:
Extract i9xx_read_luts()
If you fix the issue, kindly add following tag
Reported-by: kbuild test robot
== Series Details ==
Series: video/hdmi: Fix AVI bar unpack
URL : https://patchwork.freedesktop.org/series/66930/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6920_full -> Patchwork_14456_full
Summary
---
== Series Details ==
Series: drm/i915/selftests: Exercise CS TLB invalidation (rev2)
URL : https://patchwork.freedesktop.org/series/66718/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6920_full -> Patchwork_14455_full
== Series Details ==
Series: series starting with [CI,v2,1/6] drm/i915/display/icl: Save Master
transcoder in slave's crtc_state for Transcoder Port Sync
URL : https://patchwork.freedesktop.org/series/66956/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6925 ->
== Series Details ==
Series: series starting with [CI,v2,1/6] drm/i915/display/icl: Save Master
transcoder in slave's crtc_state for Transcoder Port Sync
URL : https://patchwork.freedesktop.org/series/66956/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.6.0
== Series Details ==
Series: series starting with [CI,1/2] drm/i915/uc: Update HuC firmware naming
convention and load latest HuC
URL : https://patchwork.freedesktop.org/series/66955/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6925 -> Patchwork_14466
On Thu, Sep 19, 2019 at 03:16:34PM -0700, Sripada, Radhakrishna wrote:
> Hi Matt,
> > -Original Message-
> > From: Roper, Matthew D
> > Sent: Tuesday, September 17, 2019 2:53 PM
> > To: Sripada, Radhakrishna
> > Cc: intel-gfx@lists.freedesktop.org; Pandiyan, Dhinakaran
> > ; Syrjala,
== Series Details ==
Series: series starting with [CI,1/2] drm/i915/uc: Update HuC firmware naming
convention and load latest HuC
URL : https://patchwork.freedesktop.org/series/66955/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
c63f361673b5 drm/i915/uc: Update HuC firmware
Quoting Patchwork (2019-09-19 23:31:43)
> * igt@gem_workarounds@basic-read:
> - {fi-tgl-u}: [PASS][1] -> [FAIL][2]
>[1]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/fi-tgl-u/igt@gem_workarou...@basic-read.html
>[2]:
>
== Series Details ==
Series: drm/i915/tgl: Move the SAMPLER_MODE setup into the context
URL : https://patchwork.freedesktop.org/series/66954/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6925 -> Patchwork_14465
Summary
Hi Matt,
> -Original Message-
> From: Roper, Matthew D
> Sent: Tuesday, September 17, 2019 2:53 PM
> To: Sripada, Radhakrishna
> Cc: intel-gfx@lists.freedesktop.org; Pandiyan, Dhinakaran
> ; Syrjala, Ville ;
> Sharma, Shashank ; Antognolli, Rafael
> ; Chery, Nanley G
> Subject: Re:
== Series Details ==
Series: drm/i915/dp: Support for DP HDR outputs (rev9)
URL : https://patchwork.freedesktop.org/series/65656/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6925 -> Patchwork_14464
Summary
---
On Wed, Sep 18, 2019 at 04:34:45PM +0300, Stanislav Lisovskiy wrote:
> Added bandwidth calculation algorithm and checks,
> similar way as it was done for ICL, some constants
> were corrected according to BSpec.
BSpec: 53998
>
> Signed-off-by: Stanislav Lisovskiy
S-o-b should be last tag, so
On Thu, 2019-09-19 at 14:27 -0700, Lucas De Marchi wrote:
> On Wed, Sep 18, 2019 at 5:07 PM José Roberto de Souza
> wrote:
> > Extending ICL mg calculations to also support dkl calculations.
> >
> > BSpec: 49204
> >
> > Signed-off-by: Vandita Kulkarni
> > Signed-off-by: José Roberto de Souza
On Thu, Sep 19, 2019 at 12:47 PM Chris Wilson wrote:
>
> Quoting Patchwork (2019-09-19 03:30:43)
> > * igt@i915_selftest@live_workarounds:
> > - {fi-tgl-u}: NOTRUN -> [DMESG-FAIL][1]
> >[1]:
> >
On Wed, Sep 18, 2019 at 5:07 PM José Roberto de Souza
wrote:
>
> Extending ICL mg calculations to also support dkl calculations.
>
> BSpec: 49204
>
> Signed-off-by: Vandita Kulkarni
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 29 +++-
>
== Series Details ==
Series: adding gamma state checker for icl+ platforms (rev3)
URL : https://patchwork.freedesktop.org/series/66811/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6925 -> Patchwork_14463
Summary
---
On 8/21/19 8:20 AM, Daniel Vetter wrote:
On Wed, Aug 21, 2019 at 3:55 PM Ville Syrjälä
wrote:
On Tue, Aug 20, 2019 at 01:57:44PM -0700, Daniele Ceraolo Spurio wrote:
On 8/20/19 12:54 PM, Daniel Vetter wrote:
The cpu (de)tiler hw is gone, this stopped being useful. Plus it never
== Series Details ==
Series: adding gamma state checker for icl+ platforms (rev3)
URL : https://patchwork.freedesktop.org/series/66811/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
f22d03d7e022 drm/i915/color: Fix formatting issues
9f36da572c33 drm/i915/color: Extract
== Series Details ==
Series: drm/i915: Create dumb buffer from LMEM
URL : https://patchwork.freedesktop.org/series/66950/
State : failure
== Summary ==
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
DESCEND objtool
CHK include/generated/compile.h
AR
As per the display enable sequence, we need to follow the enable sequence
for slaves first with DP_TP_CTL set to Idle and configure the transcoder
port sync register to select the corersponding master, then follow the
enable sequence for master leaving DP_TP_CTL to idle.
At this point the
In the transcoder port sync mode, the slave transcoders mask their vblanks
until master transcoder's vblank so while disabling them, make
sure slaves are disabled first and then the masters.
v4:
* Obtain slave state from master (Maarten)
v3:
* Rebase
v2:
* Use the intel_old_crtc_state_disables()
After the state is committed, we readout the HW registers and compare
the HW state with the SW state that we just committed.
For Transcdoer port sync, we add master_transcoder and the
salves bitmask to the crtc_state, hence we need to read those during
the HW state readout to avoid pipe state
This clears the transcoder port sync bits of the TRANS_DDI_FUNC_CTL2
register during crtc_disable().
v2:
* Directly write the trans_port_sync reg value (Maarten)
Cc: Ville Syrjälä
Cc: Maarten Lankhorst
Cc: Matt Roper
Cc: Jani Nikula
Signed-off-by: Manasi Navare
Reviewed-by: Maarten
In case of tiled displays where different tiles are displayed across
different ports, we need to synchronize the transcoders involved.
This patch implements the transcoder port sync feature for
synchronizing one master transcoder with one or more slave
transcoders. This is only enbaled in slave
In case of tiled displays when the two tiles are sent across two CRTCs
over two separate DP SST connectors, we need a mechanism to synchronize
the two CRTCs and their corresponding transcoders.
So use the master-slave mode where there is one master corresponding
to last horizontal and vertical
== Series Details ==
Series: drm/i915/tgl: Suspend pre-parser across GTT invalidations (rev2)
URL : https://patchwork.freedesktop.org/series/66703/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6925 -> Patchwork_14461
On Thu, 2019-09-19 at 23:25 +0300, Imre Deak wrote:
> On Thu, Sep 19, 2019 at 10:25:33PM +0300, Imre Deak wrote:
> > On Wed, Sep 18, 2019 at 05:07:23PM -0700, José Roberto de Souza
> > wrote:
> > > New step added for TGL, required for us to check the TC
> > > microcontroller health after power on
On Thu, Sep 19, 2019 at 10:25:33PM +0300, Imre Deak wrote:
> On Wed, Sep 18, 2019 at 05:07:23PM -0700, José Roberto de Souza wrote:
> > New step added for TGL, required for us to check the TC
> > microcontroller health after power on TC aux.
> >
> > BSpec: 49294
> >
> > Signed-off-by: José
== Series Details ==
Series: dma-buf: Implement simple read/write vfs ops
URL : https://patchwork.freedesktop.org/series/66941/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6925 -> Patchwork_14460
Summary
---
Quoting Chris Wilson (2019-07-18 09:02:03)
> The log is not flushed from inside the irq, but from a worker spawned by
> the interrupt. Flushing an on-going interrupt (intel_synchronize_irq)
> does not flush a concurrent intel_guc_log_handle_flush_event() and
> instead we must flush the
From: Anusha Srivatsa
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_params.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_params.h
b/drivers/gpu/drm/i915/i915_params.h
index d29ade3b7de6..f9fbb1f2fabf 100644
---
From: Anusha Srivatsa
Make both GuC and HuC to use "." as the separator. Hardcode
the separator in MAKE_UC_FW_PATH. Remove the usage of "ver" from HuC.
The current convention being:
_uc_..patch.bin
Update the versions of HuC being loaded of the platforms.
SKL - v2.0.0
BXT - v2.0.0
KBL -
== Series Details ==
Series: series starting with [v2,1/3] drm/i915: Mark i915_request.timeline as a
volatile, rcu pointer
URL : https://patchwork.freedesktop.org/series/66923/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6919_full -> Patchwork_14454_full
On 9/14/19 4:06 PM, Patchwork wrote:
== Series Details ==
Series: series starting with [CI,1/2] drm/i915/uc: Update HuC firmware naming
convention and load latest HuC
URL : https://patchwork.freedesktop.org/series/66685/
State : failure
== Summary ==
CI Bug Log - changes from
Quoting Ramalingam C (2019-09-19 19:04:33)
> When LMEM is supported, dumb buffer preferred to be created from LMEM.
>
> This is developed on top of v3 LMEM series
> https://patchwork.freedesktop.org/series/56683/.
>
> Signed-off-by: Ramalingam C
> cc: Matthew Auld
> ---
>
SAMPLER_MODE is a context saved/restored register and needs to be loaded
into a context for it to be preserved across a GPU reset -- as has been
done on the previous generations of the same register.
Fixes: 7f0cc34b5349 ("drm/i915/tgl: Implement Wa_1406941453")
Signed-off-by: Chris Wilson
Cc:
It attaches HDR metadata property to DP connector on GLK+.
It enables HDR metadata infoframe sdp on GLK+ to be used to send
HDR metadata to DP sink.
v2: Minor style fix
Signed-off-by: Gwan-gyeong Mun
Reviewed-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_dp.c | 5 +
1 file
It attaches the colorspace connector property to a DisplayPort connector.
Based on colorspace change, modeset will be triggered to switch to a new
colorspace.
And in order to distinguish colorspace bwtween DP and HDMI connector, it
adds a handling of drm_mode_create_dp_colorspace_property() to
Because between HDMI and DP have different colorspaces, it adds
drm_mode_create_dp_colorspace_property() function for creating of DP
colorspace property.
v3: Addressed review comments from Ville
- Add new colorimetry options for DP 1.4a spec.
- Separate set of colorimetry enum values for
When BT.2020 Colorimetry output is used for DP, we should program BT.2020
Colorimetry to MSA and VSC SDP. In order to handle colorspace of
drm_connector_state, it moves a calling of intel_ddi_set_pipe_settings()
function into intel_ddi_pre_enable_dp(). And it also rename
Support for HDR10 video was introduced in DisplayPort 1.4.
On GLK+ platform, in order to use DisplayPort HDR10, we need to support
BT.2020 colorimetry and HDR Static metadata.
It implements the CTA-861-G standard for transport of static HDR metadata.
It enables writing of HDR metadata infoframe
According to Bspec, GEN11 and prior GEN11 have different register size for
HDR Metadata Infoframe SDP packet. It adds new VIDEO_DIP_GMP_DATA_SIZE for
GEN11. And it makes handle different register size for
HDMI_PACKET_TYPE_GAMUT_METADATA on hsw_dip_data_size() for each GEN
platforms. It addresses
Function intel_dp_setup_hdr_metadata_infoframe_sdp handles Infoframe SDP
header and data block setup for HDR Static Metadata. It enables writing of
HDR metadata infoframe SDP to panel. Support for HDR video was introduced
in DisplayPort 1.4. It implements the CTA-861-G standard for transport of
It refactors and renames a function which handled vsc sdp header and data
block setup for supporting colorimetry format.
Function intel_dp_setup_vsc_sdp handles vsc sdp header and data block
setup for pixel encoding / colorimetry format.
In order to use colorspace information of a connector, it
As between HDMI and DP have different colorspaces, in order to distinguish
colorspace of DP and HDMI, it renames drm_mode_create_colorspace_property()
function to drm_mode_create_hdmi_colorspace_property() function for HDMI
connector.
In order to apply changed drm api, i915 driver has channged.
On Wed, 2019-09-18 at 17:13 +0300, Ville Syrjälä wrote:
> On Mon, Sep 16, 2019 at 10:11:49AM +0300, Gwan-gyeong Mun wrote:
> > Function intel_dp_setup_hdr_metadata_infoframe_sdp handles
> > Infoframe SDP
> > header and data block setup for HDR Static Metadata. It enables
> > writing of
> > HDR
On Wed, 2019-09-18 at 17:08 +0300, Ville Syrjälä wrote:
> On Mon, Sep 16, 2019 at 10:11:46AM +0300, Gwan-gyeong Mun wrote:
> > Because between HDMI and DP have different colorspaces, it renames
> > drm_mode_create_colorspace_property() function to
> > drm_mode_create_hdmi_colorspace_property()
On Wed, 2019-09-18 at 17:15 +0300, Ville Syrjälä wrote:
> On Mon, Sep 16, 2019 at 10:11:45AM +0300, Gwan-gyeong Mun wrote:
> > When BT.2020 Colorimetry output is used for DP, we should program
> > BT.2020
> > Colorimetry to MSA and VSC SDP. It adds output_colorspace to
> > intel_crtc_state struct
Quoting Patchwork (2019-09-19 03:30:43)
> * igt@i915_selftest@live_workarounds:
> - {fi-tgl-u}: NOTRUN -> [DMESG-FAIL][1]
>[1]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14448/fi-tgl-u/igt@i915_selftest@live_workarounds.html
> - {fi-tgl-u2}:[PASS][2] ->
On Thu, Sep 19, 2019 at 11:56:27AM -0700, Lucas De Marchi wrote:
> On Thu, Sep 19, 2019 at 10:21 AM Imre Deak wrote:
> >
> > On Wed, Sep 18, 2019 at 05:07:14PM -0700, José Roberto de Souza wrote:
> > > From: Clinton A Taylor
> > >
> > > Step 4.b was complete missed because it is only required to
On Thu, 2019-09-19 at 20:20 +0300, Imre Deak wrote:
> On Wed, Sep 18, 2019 at 05:07:14PM -0700, José Roberto de Souza
> wrote:
> > From: Clinton A Taylor
> >
> > Step 4.b was complete missed because it is only required to TC and
> > TBT.
> >
> > Bspec: 49190
> > Signed-off-by: Clinton A Taylor
On Wed, Sep 18, 2019 at 05:07:23PM -0700, José Roberto de Souza wrote:
> New step added for TGL, required for us to check the TC
> microcontroller health after power on TC aux.
>
> BSpec: 49294
>
> Signed-off-by: José Roberto de Souza
Reviewed-by: Imre Deak
> ---
>
== Series Details ==
Series: Docs: fix incorrect use of kernel-doc format in structure description.
URL : https://patchwork.freedesktop.org/series/66922/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6919_full -> Patchwork_14453_full
On Wed, Sep 18, 2019 at 5:07 PM José Roberto de Souza
wrote:
>
> From: Lucas De Marchi
>
> The disable function can be the same as for MG phy since the same
> registers are used. The others are different as registers changed,
> also adding a empty dkl_pll_write() to be implemented later.
>
> v2:
On Wed, Sep 18, 2019 at 5:07 PM José Roberto de Souza
wrote:
>
> From: Vandita Kulkarni
>
> These are the registers needed to program Dekel phy. Some register
> definitions will be reused from MG PHY definitions, so adding a
> comment on those.
>
> Bspec: 49295
>
> Signed-off-by: Vandita
== Series Details ==
Series: drm/i915: Extract GT render sleep (rc6) management
URL : https://patchwork.freedesktop.org/series/66937/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6923 -> Patchwork_14459
Summary
---
On Thu, Sep 19, 2019 at 10:21 AM Imre Deak wrote:
>
> On Wed, Sep 18, 2019 at 05:07:14PM -0700, José Roberto de Souza wrote:
> > From: Clinton A Taylor
> >
> > Step 4.b was complete missed because it is only required to TC and TBT.
> >
> > Bspec: 49190
> > Signed-off-by: Clinton A Taylor
> >
On Wed, Sep 18, 2019 at 01:42:09PM +, Lisovskiy, Stanislav wrote:
> On Mon, 2019-07-08 at 15:53 +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Allow drivers to call drm_atomic_helper_check_modeset() without
> > having the crtc helper funcs specified. i915 doesn't need those
> >
== Series Details ==
Series: drm/i915: Extract GT render sleep (rc6) management
URL : https://patchwork.freedesktop.org/series/66937/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
9821d2bbba09 drm/i915: Extract GT render sleep (rc6) management
-:73: WARNING:FILE_PATH_CHANGES:
Only to print hw and sw lut values/channel.
Signed-off-by: Swati Sharma
---
drivers/gpu/drm/i915/display/intel_color.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers/gpu/drm/i915/display/intel_color.c
index ad548ce..a7a2fa0 100644
---
For icl+, have hw read out to create hw blob of gamma
lut values. icl+ platforms supports multi segmented gamma
mode by default, add hw lut creation for this mode.
This will be used to validate gamma programming using dsb
(display state buffer) which is a tgl specific feature.
Following are the
Fixed few formatting issues in multi-segmented load_lut().
v3: -style nitting [Jani]
-balanced parentheses moved from patch 2 to 1 [Jani]
-subject prefix change [Jani]
-added commit message [Jani]
Signed-off-by: Swati Sharma
---
drivers/gpu/drm/i915/display/intel_color.c | 34
In this patch series, added state checker to validate gamma lut values
for icelake+ platforms. It's extension of the
patch series https://patchwork.freedesktop.org/patch/328246/?series=58039
which enabled the basic infrastructure and state checker for
legacy platforms.
Major changes done in patch
When LMEM is supported, dumb buffer preferred to be created from LMEM.
This is developed on top of v3 LMEM series
https://patchwork.freedesktop.org/series/56683/.
Signed-off-by: Ramalingam C
cc: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem.c | 18 ++
1 file changed, 14
== Series Details ==
Series: series starting with [1/3] drm/rect: Return scaling factor and error
code separately
URL : https://patchwork.freedesktop.org/series/66935/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6922 -> Patchwork_14458
Quoting Tvrtko Ursulin (2019-09-19 18:11:14)
>
> On 19/09/2019 14:26, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2019-09-19 14:02:19)
> >>
> >> On 19/09/2019 12:19, Chris Wilson wrote:
> >>> +static struct intel_timeline *get_timeline(struct i915_request *rq)
> >>> +{
> >>> + struct
On 9/19/2019 10:08 PM, Jani Nikula wrote:
On Wed, 18 Sep 2019, Animesh Manna wrote:
DSB can program large set of data through indexed register write
(opcode 0x9) in one shot. DSB feature can be used for bulk register
programming e.g. gamma lut programming, HDR meta data programming.
v1:
On 19-Sep-19 6:01 PM, Jani Nikula wrote:
On Wed, 18 Sep 2019, "Sharma, Swati2" wrote:
On 18-Sep-19 3:31 PM, Jani Nikula wrote:
On Tue, 17 Sep 2019, Swati Sharma wrote:
For icl+, have hw read out to create hw blob of gamma
lut values. icl+ platforms supports multi segmented gamma
mode, add
== Series Details ==
Series: drm/i915: modeset probe/remove path refactoring
URL : https://patchwork.freedesktop.org/series/66933/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6922 -> Patchwork_14457
Summary
---
== Series Details ==
Series: series starting with [1/3] drm/rect: Return scaling factor and error
code separately
URL : https://patchwork.freedesktop.org/series/66935/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
d1d7588e302a drm/rect: Return scaling factor and error code
On Wed, Sep 18, 2019 at 05:07:14PM -0700, José Roberto de Souza wrote:
> From: Clinton A Taylor
>
> Step 4.b was complete missed because it is only required to TC and TBT.
>
> Bspec: 49190
> Signed-off-by: Clinton A Taylor
> Signed-off-by: José Roberto de Souza
> ---
>
On 19/09/2019 14:26, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-09-19 14:02:19)
On 19/09/2019 12:19, Chris Wilson wrote:
+static struct intel_timeline *get_timeline(struct i915_request *rq)
+{
+ struct intel_timeline *tl;
+
+ /*
+ * Even though we are holding the
== Series Details ==
Series: drm/i915: modeset probe/remove path refactoring
URL : https://patchwork.freedesktop.org/series/66933/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
37407ee77e3d drm/i915: add i915_driver_modeset_remove()
5016ea3f0226 drm/i915: pass i915 to
On Wed, 18 Sep 2019, Animesh Manna wrote:
> DSB can program large set of data through indexed register write
> (opcode 0x9) in one shot. DSB feature can be used for bulk register
> programming e.g. gamma lut programming, HDR meta data programming.
>
> v1: initial version.
> v2: simplified code by
From: Ville Syrjälä
Just access both halves of the motion vector thing
directly instead of doung the cast to uint and deref.
Signed-off-by: Ville Syrjälä
---
src/legacy/i810/xvmc/I810XvMC.c | 48 -
1 file changed, 24 insertions(+), 24 deletions(-)
diff --git
From: Ville Syrjälä
The compiler seems to think src/mask xoff/yoff can be used
uninitialized. Zero them to make sure.
Signed-off-by: Ville Syrjälä
---
src/sna/fb/fbpict.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/src/sna/fb/fbpict.c b/src/sna/fb/fbpict.c
index
From: Ville Syrjälä
Use a cast to avoid the "left shift of negative value
[-Wshift-negative-value]" warning, and get rid of the
suppression.
Signed-off-by: Ville Syrjälä
---
src/sna/meson.build | 1 -
src/sna/sna_trapezoids_mono.c | 2 +-
2 files changed, 1 insertion(+), 2
From: Ville Syrjälä
Fix the sign comparison warnings by changing some types, and
using a few casts.
Signed-off-by: Ville Syrjälä
---
tools/backlight_helper.c | 2 +-
tools/meson.build| 2 --
tools/virtual.c | 18 +-
3 files changed, 10 insertions(+), 12
From: Ville Syrjälä
Deal with xserver commit 8e3b26ceaa86 ("Make PixmapDirtyUpdateRec::src
a DrawablePtr")
Not sure this is still correct though. Is this stuff limited to
pixmaps anymore?
Signed-off-by: Ville Syrjälä
---
src/sna/sna_accel.c | 20 +++-
1 file changed, 19
From: Ville Syrjälä
The minimum CS URB entry size is 1. Let's use that
instead of 0 so that we don't end up left shifting
a -1.
Signed-off-by: Ville Syrjälä
---
src/uxa/i965_render.c | 2 +-
src/uxa/i965_video.c | 2 +-
src/uxa/meson.build | 1 -
3 files changed, 2 insertions(+), 3
From: Ville Syrjälä
The compiler seems incapable of deducing whether something
is used uninitialized or not.
Signed-off-by: Ville Syrjälä
---
src/sna/meson.build | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/sna/meson.build b/src/sna/meson.build
index 9e4b69f45e55..7408f63c82db
From: Ville Syrjälä
Just access the xGlyphInfo members directly to avoid the
compiler getting upset about strict aliasing violations.
Signed-off-by: Ville Syrjälä
---
src/sna/sna_glyphs.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/src/sna/sna_glyphs.c
From: Ville Syrjälä
Replace the cast+deref with memcpy() so that we don't upset
the compiler's strict aliasing rules.
Signed-off-by: Ville Syrjälä
---
src/sna/fb/fbspan.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/src/sna/fb/fbspan.c b/src/sna/fb/fbspan.c
index
From: Ville Syrjälä
../src/intel_device.c: In function ‘__intel_open_device__pci.isra.6’:
../src/intel_device.c:321:25: warning: ‘%s’ directive writing up to 255 bytes
into a region of size 247 [-Wformat-overflow=]
sprintf(path + base, "%s", de->d_name);
Signed-off-by: Ville Syrjälä
---
From: Ville Syrjälä
../src/sna/sna_display.c: In function ‘sna_covering_crtc’:
../src/sna/sna_display.c:8235:34: warning: dereferencing type-punned pointer
will break strict-aliasing rules [-Wstrict-aliasing]
if (*(const uint64_t *)box == *(uint64_t *)>bounds) {
Signed-off-by: Ville Syrjälä
From: Ville Syrjälä
Avoid -Wno-missing-field-initializers by using named
initializers.
Signed-off-by: Ville Syrjälä
---
src/sna/meson.build | 1 -
src/sna/sna_composite.c | 2 +-
src/sna/sna_display.c| 6 +++---
src/sna/sna_display_fake.c | 2 +-
From: Ville Syrjälä
Silence the compiler warning about missing initializers
by using named initializers.
Signed-off-by: Ville Syrjälä
---
src/uxa/intel_display.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/uxa/intel_display.c b/src/uxa/intel_display.c
index
From: Ville Syrjälä
Refactor the BR13 color depth setup to common helper. This
eliminates a bunch of implicit fall through warns.
Signed-off-by: Ville Syrjälä
---
src/sna/kgem.c| 10 +++--
src/sna/sna.h | 19
src/sna/sna_blt.c | 56
From: Ville Syrjälä
Duplicate a bit of code in FbDoLeftMaskByteRRop() switch statement
to avoid the fall through.
And while at it sort the cases based on the left byte and length.
Makes the pattern matcher in my brain much happier.
Signed-off-by: Ville Syrjälä
---
src/sna/fb/fb.h | 6 --
From: Ville Syrjälä
Sprinkle fall through comments where needed.
Signed-off-by: Ville Syrjälä
---
src/intel_module.c| 1 +
src/sna/blt.c | 2 ++
src/sna/gen2_render.c | 21 +
src/sna/gen3_render.c | 24 ++--
src/sna/sna_accel.c | 3 +++
From: Ville Syrjälä
Use an empty {} as the terminator in intel_device_match[] to avoid
the warning about missing initlizers.
Signed-off-by: Ville Syrjälä
---
src/intel_module.c | 2 +-
src/meson.build| 1 -
2 files changed, 1 insertion(+), 2 deletions(-)
diff --git a/src/intel_module.c
From: Ville Syrjälä
gcc doesn't like extra stuff in the fall through comments.
Replace them with the standard form.
Signed-off-by: Ville Syrjälä
---
src/sna/gen4_render.c | 6 +++---
src/sna/gen5_render.c | 6 +++---
src/sna/gen6_render.c | 6 +++---
src/sna/gen7_render.c | 6 +++---
From: Ville Syrjälä
Random smattering of patches to eliminate compiler warnings.
Some I just suppressed out of lazyness, others I tried to
silence by adjusting the code a bit.
Afterwards the build is clean on my gcc 8.3, though with
a bunch of stuff still suppressed I'm not 100% sure that's
a
From: Ville Syrjälä
Avoid the compiler gettings upset about us redefining
FontSetPrivate().
Signed-off-by: Ville Syrjälä
---
src/sna/sna_accel.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/sna/sna_accel.c b/src/sna/sna_accel.c
index 7fd00b9af679..934c8f662bea 100644
---
From: Ville Syrjälä
Suppress more compiler warnings.
Signed-off-by: Ville Syrjälä
---
src/sna/meson.build | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/sna/meson.build b/src/sna/meson.build
index 4af181f37b29..b1276ab3aa6e 100644
--- a/src/sna/meson.build
+++
From: Ville Syrjälä
../src/sna/sna_composite.c:567:11: warning: variable ‘sx’ might be clobbered by
‘longjmp’ or ‘vfork’ [-Wclobbered]
int16_t sx = src_x + tx - (dst->pDrawable->x + dst_x);
^~
etc.
I had a quick look at a few of the cases and they seemed fine to me,
so feels like
On Thu, Sep 19, 2019 at 5:53 PM Chris Wilson wrote:
>
> Quoting Daniel Vetter (2019-09-19 16:28:41)
> > On Thu, Sep 19, 2019 at 5:09 PM Chris Wilson
> > wrote:
> > >
> > > It is expected that processes will pass dma-buf fd between drivers, and
> > > only using the fd themselves for mmaping and
Quoting Daniel Vetter (2019-09-19 16:28:41)
> On Thu, Sep 19, 2019 at 5:09 PM Chris Wilson wrote:
> >
> > It is expected that processes will pass dma-buf fd between drivers, and
> > only using the fd themselves for mmaping and synchronisation ioctls.
> > However, it may be convenient for an
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