On Thu, 2022-05-05 at 13:45 +0300, Jani Nikula wrote:
> On Wed, 04 May 2022, José Roberto de Souza wrote:
> > This feature is supported from display 9 to display 12 and was
> > incorrectly being applied to DG2 and Alderlake-P.
> >
> > While at is also taking the oportunity to drop it from
> >
On Mon, 2022-05-02 at 09:34 -0700, Matt Roper wrote:
> From: Lucas De Marchi
>
> The new Link Copy engines in PVC may be fused off according to the
> mslice_mask. Each bit of the MEML3_EN_MASK we read from the
> GEN10_MIRROR_FUSE3 register disables a pair of link copy engines.
Reviewed-by: José
On Mon, 2022-05-02 at 09:34 -0700, Matt Roper wrote:
> From: John Harrison
>
> PVC adds extra blitter engines (in the following patch). The reset
> selftest has a local array on the stack which is sized by the number
> of engines. The increase pushes the size of this array to the point
> where
On Mon, 2022-05-02 at 09:34 -0700, Matt Roper wrote:
> This patch adds the basic definitions needed to support
> new copy engines. Also updating the cmd_info to accommodate
> new engines, as the engine id's of legacy engines have been
> changed.
Reviewed-by: José Roberto de Souza
>
>
On Mon, 2022-05-02 at 09:34 -0700, Matt Roper wrote:
> This patch adds the reset support for new copy engines
> in PVC.
Reviewed-by: José Roberto de Souza
>
> Bspec: 52549
> Original-author: CQ Tang
> Signed-off-by: Matt Roper
> ---
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 8 +
>
On Mon, 2022-05-02 at 09:34 -0700, Matt Roper wrote:
> From: Lucas De Marchi
>
> As we have more copy engines now, mask all of them from aux table
> invalidate.
Reviewed-by: José Roberto de Souza
>
> Cc: Prathap Kumar Valsan
> Signed-off-by: Lucas De Marchi
> Signed-off-by: Matt Roper
>
On Fri, 2022-04-29 at 19:00 +0300, Ville Syrjälä wrote:
> On Thu, Apr 28, 2022 at 02:10:56PM -0700, José Roberto de Souza wrote:
> > Frontbuffer updates were scheduling the execution of DRRS work thread
> > even if DRRS is not active.
> > There was no issues with it because
On Tue, 2022-04-26 at 21:08 +0300, Ville Syrjälä wrote:
> On Thu, Apr 21, 2022 at 12:22:03PM -0700, José Roberto de Souza wrote:
> > Intel hardware supports change between modes with different refresh
> > rates without any glitches or visual artifacts, that feature is called
> > seamless DRRS.
> >
On Mon, 2022-04-25 at 14:55 +0300, Jani Nikula wrote:
> On Thu, 21 Apr 2022, José Roberto de Souza wrote:
> > Will be adding some additional control options to DRRS that will
> > require to have the DRRS downclock mode stored in the crtc_state.
> >
> > So to optimize memory usage a bit here
On Thu, 2022-04-21 at 19:22 +0300, Imre Deak wrote:
> Fix typo in the _SEL_FETCH_PLANE_BASE_1_B register base address.
>
Reviewed-by: José Roberto de Souza
> Fixes: a5523e2ff074a5 ("drm/i915: Add PSR2 selective fetch registers")
> References:
On Thu, 2022-04-21 at 15:17 +0300, Ville Syrjälä wrote:
> On Mon, Apr 18, 2022 at 01:52:20PM -0700, José Roberto de Souza wrote:
> > Instead of keep the DRRS status of all connectors/pipe into a single
> > i915_drrs_status what makes user-space parsing terrible moving
> > each eDP connector status
On Wed, 2022-04-20 at 15:49 +, Patchwork wrote:
Patch Details
Series: series starting with [v2,1/2] drm/i915/display: Add workaround
22014263786 (rev3)
URL:https://patchwork.freedesktop.org/series/102835/
State: success
Details:
On Tue, 2022-04-19 at 20:25 +, Patchwork wrote:
Patch Details
Series: series starting with [v2,1/2] drm/i915/display: Add workaround
22014263786 (rev2)
URL:https://patchwork.freedesktop.org/series/102835/
State: failure
Details:
On Mon, 2022-04-18 at 17:09 +0200, Hans de Goede wrote:
> Commit 428cb15d5b00 ("drm/i915: Clean up pre-skl primary plane registers")
> introduced DISP_POS_Y and DISP_HEIGHT defines but accidentally set these
> their masks to REG_GENMASK(31, 0) instead of REG_GENMASK(31, 16).
>
> This breaks the
On Wed, 2022-04-13 at 16:28 +0530, Tejas Upadhyay wrote:
> ADL-N and ADL-P stepping are different, thus we
> need to add check for ADL-N in IS_ADLP_DISPLAY_STEP().
>
> Signed-off-by: Tejas Upadhyay
> ---
> drivers/gpu/drm/i915/i915_drv.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
On Thu, 2022-04-14 at 11:13 +, Hogander, Jouni wrote:
> On Wed, 2022-04-13 at 09:43 -0700, José Roberto de Souza wrote:
> > Alderlake-P don't have PSR2_MAN_TRK_CTL_ENABLE bit, instead it have
> > ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE in the same bit but
> > this
> > bit is clearead
On Thu, 2022-04-14 at 11:08 +, Hogander, Jouni wrote:
> On Wed, 2022-04-13 at 15:59 +0000, Souza, Jose wrote:
> > On Wed, 2022-04-13 at 07:27 +, Hogander, Jouni wrote:
> > > Hello Jose,
> > >
> > > See my comment below.
> > >
> > > On
On Wed, 2022-04-13 at 07:27 +, Hogander, Jouni wrote:
> Hello Jose,
>
> See my comment below.
>
> On Tue, 2022-04-12 at 13:55 -0700, José Roberto de Souza wrote:
> > After commit 805f04d42a6b ("drm/i915/display/psr: Use continuos full
> > frame to handle frontbuffer invalidations") was
On Thu, 2022-04-07 at 21:01 +, Patchwork wrote:
Patch Details
Series: drm/i915/display: Fix warnings about PSR lock not held (rev3)
URL:https://patchwork.freedesktop.org/series/102298/
State: failure
Details:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22818/index.html
CI
On Tue, 2022-04-05 at 21:50 +, Patchwork wrote:
Patch Details
Series: series starting with [CI,1/3] drm/i915/display/psr: Set partial frame
enable when forcing full frame fetch
URL:https://patchwork.freedesktop.org/series/102209/
State: failure
Details:
On Mon, 2022-04-04 at 07:41 +, Hogander, Jouni wrote:
> Hello,
>
> Couple of questions below.
> On Fri, 2022-04-01 at 15:29 -0700, José Roberto de Souza wrote:
> > Frontbuffer rendering and page flips can race with each other
> > and this can potentialy cause issues with PSR2 selective fetch.
On Wed, 2022-03-30 at 19:29 +, Patchwork wrote:
Patch Details
Series: series starting with [CI,v3,1/3] drm/i915/display/tgl+: Set default
values for all registers in PIPE_MBUS_DBOX_CTL
URL:https://patchwork.freedesktop.org/series/101965/
State: failure
Details:
On Wed, 2022-03-30 at 15:54 +, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [CIv2,1/4] drm/i915/display/tgl+: Set default
> values for all registers in PIPE_MBUS_DBOX_CTL
> URL : https://patchwork.freedesktop.org/series/101963/
> State : failure
>
> == Summary
On Tue, 2022-03-29 at 21:14 +0300, Ville Syrjälä wrote:
> On Mon, Mar 28, 2022 at 12:16:15PM -0700, José Roberto de Souza wrote:
> > From: Caz Yokoyama
> >
> > B credits set by IFWI do not match with specification default, so here
> > programming the right value.
> >
> > Also while at it,
On Tue, 2022-03-29 at 16:10 +0300, Lisovskiy, Stanislav wrote:
> On Tue, Mar 22, 2022 at 03:36:10PM +0200, Souza, Jose wrote:
> > On Tue, 2022-03-22 at 09:49 +0200, Lisovskiy, Stanislav wrote:
> > > On Mon, Mar 21, 2022 at 07:01:27PM +0200, Souza, Jose wrote:
> > > &g
On Tue, 2022-03-29 at 00:00 +, Patchwork wrote:
Patch Details
Series: docs: gpu: i915.rst: Fix DRRS documentation (rev2)
URL:https://patchwork.freedesktop.org/series/101806/
State: success
Details:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22699/index.html
CI Bug Log -
On Fri, 2022-03-25 at 14:21 +, Hogander, Jouni wrote:
> Hello Jose,
>
> See my comments below.
>
> On Thu, 2022-03-24 at 11:13 -0700, José Roberto de Souza wrote:
> > Instead of exit PSR when a frontbuffer invalidation happens, we can
> > enable the PSR2 selective fetch continuous full
On Thu, 2022-03-24 at 13:30 +0200, Ville Syrjälä wrote:
> On Tue, Mar 22, 2022 at 02:46:15PM -0700, José Roberto de Souza wrote:
> > PIPE_MBUS_DBOX_CTL was only being programmed when a pipe is being
> > enabled but that could potentially cause issues as it could have
> > mismatching values while
Hi Mark
See comment below.
On Tue, 2022-03-22 at 10:23 -0400, Mark Pearson wrote:
> Thanks Stanislav,
>
> On 3/22/22 10:18, Lisovskiy, Stanislav wrote:
> > On Tue, Mar 22, 2022 at 09:55:35AM -0400, Mark Pearson wrote:
> > > Hi,
> > >
> > > On 3/21/22 06:49, Stanislav Lisovskiy wrote:
> > > >
On Tue, 2022-03-22 at 14:58 -0700, Caz Yokoyama wrote:
>
>
> On Tue, Mar 22, 2022 at 2:45 PM José Roberto de Souza
> wrote:
> > skl_compute_ddb() will for a modeset in all pipes when MBUS joining
> > changes between states, so all pipes will be disabled, have all
> > MBUS related registers
On Fri, 2022-03-18 at 23:28 +0200, Ville Syrjälä wrote:
> On Fri, Mar 18, 2022 at 12:55:22PM -0700, José Roberto de Souza wrote:
> > PIPE_MBUS_DBOX_CTL was only being programmed when a pipe is being
> > enabled leaving other pipes with a wrong A_CREDIT value in cases
> > like when going from one
On Tue, 2022-03-22 at 09:49 +0200, Lisovskiy, Stanislav wrote:
> On Mon, Mar 21, 2022 at 07:01:27PM +0200, Souza, Jose wrote:
> > On Mon, 2022-03-21 at 12:49 +0200, Stanislav Lisovskiy wrote:
> > > We are currently getting FIFO underruns, in particular
> > > when
On Tue, 2022-03-22 at 15:30 +0200, Lisovskiy, Stanislav wrote:
> On Tue, Mar 22, 2022 at 03:16:41PM +0200, Souza, Jose wrote:
> > On Tue, 2022-03-22 at 09:48 +0200, Lisovskiy, Stanislav wrote:
> > > On Mon, Mar 21, 2022 at 06:58:39PM +0200, Souza, Jose wrote:
> > > &g
On Tue, 2022-03-22 at 09:48 +0200, Lisovskiy, Stanislav wrote:
> On Mon, Mar 21, 2022 at 06:58:39PM +0200, Souza, Jose wrote:
> > On Mon, 2022-03-21 at 12:49 +0200, Stanislav Lisovskiy wrote:
> > > We are currently getting FIFO underruns, in particular
> > > when
On Tue, 2022-03-15 at 22:23 +0200, Ville Syrjälä wrote:
> On Tue, Mar 15, 2022 at 06:54:21PM +0000, Souza, Jose wrote:
> > On Tue, 2022-03-15 at 15:27 +0200, Ville Syrjala wrote:
> > > From: Ville Syrjälä
> > >
> > > Rename the DRRS functiosn to say &quo
On Mon, 2022-03-21 at 12:49 +0200, Stanislav Lisovskiy wrote:
> We are currently getting FIFO underruns, in particular
> when PSR2 is enabled. There seem to be no existing workaround
> or patches, which can fix that issue(were expecting some recent
> selective fetch update and DBuf bw/SAGV fixes
On Mon, 2022-03-21 at 12:49 +0200, Stanislav Lisovskiy wrote:
> We are currently getting FIFO underruns, in particular
> when PSR2 is enabled. There seem to be no existing workaround
> or patches, which can fix that issue(were expecting some recent
> selective fetch update and DBuf bw/SAGV fixes
On Fri, 2022-03-18 at 16:22 +0200, Lisovskiy, Stanislav wrote:
> On Fri, Mar 18, 2022 at 02:27:53PM +0200, Souza, Jose wrote:
> > On Fri, 2022-03-18 at 05:22 -0700, José Roberto de Souza wrote:
> > > On Fri, 2022-03-18 at 10:52 +0200, Stanislav Lisovskiy wrote:
> > >
On Fri, 2022-03-18 at 16:19 +0200, Lisovskiy, Stanislav wrote:
> On Fri, Mar 18, 2022 at 02:21:10PM +0200, Souza, Jose wrote:
> > On Fri, 2022-03-18 at 10:52 +0200, Stanislav Lisovskiy wrote:
> > > We are currently getting FIFO underruns, in particular
> > > when
On Fri, 2022-03-18 at 05:22 -0700, José Roberto de Souza wrote:
> On Fri, 2022-03-18 at 10:52 +0200, Stanislav Lisovskiy wrote:
> > We are currently getting FIFO underruns, in particular
> > when PSR2 is enabled. There seem to be no existing workaround
> > or patches, which can fix that issue(were
On Fri, 2022-03-18 at 10:52 +0200, Stanislav Lisovskiy wrote:
> We are currently getting FIFO underruns, in particular
> when PSR2 is enabled. There seem to be no existing workaround
> or patches, which can fix that issue(were expecting some recent
> selective fetch update and DBuf bw/SAGV fixes
On Wed, 2022-03-16 at 16:45 -0700, Lucas De Marchi wrote:
> From: Matthew Brost
>
> Add logical mapping for VDBOXs. This mapping is required for
> split-frame workloads, which otherwise fail with
>
> -F8C53528: [GUC] 0441-INVALID_ENGINE_SUBMIT_MASK
>
> ... if the application is
On Wed, 2022-03-16 at 16:45 -0700, Lucas De Marchi wrote:
> Earlier versions of commit a5b7ef27da60 ("drm/i915: Add struct to hold
> IP version") named "ver" as "arch" and then when it was renamed it
> missed the rename on MEDIA_VER_FULL() since it it's currently not used.
Reviewed-by: José
On Tue, 2022-03-15 at 15:27 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Rename the DRRS functiosn to say "(de)activate" rather than
> "enable/disable". This let's us differentiate between the
> logically enabled vs. actually currently active cases.
>
> Signed-off-by: Ville Syrjälä
>
On Tue, 2022-03-15 at 15:27 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Let's just do a full DRRS disable/enable across all pipe updates.
> This guarantees that the DRRS work doesn't interfere with anything
> while the atomic commit is busy reprogramming the pipe.
>
> Needed so that
On Tue, 2022-03-15 at 15:27 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> With static DRRS the user might ask for the lowest possible refresh
> rate of the panel, in which case we're not going to find a suitable
> downclock mode for it and we should not try to enable seamless DRRS.
>
On Tue, 2022-03-15 at 15:27 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Schedule the DRRS downclock work already from intel_drrs_enable()
> instead of waiting around for a frontbuffer flush that may or
> may not ever come.
Reviewed-by: José Roberto de Souza
>
> Signed-off-by: Ville
On Tue, 2022-03-15 at 15:27 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Skip all the DRRS work cancel/schedule stuff if the pipe's
> frontbuffer bits were not among those affected by the frontbuffer
> rendering.
Reviewed-by: José Roberto de Souza
>
> Signed-off-by: Ville Syrjälä
>
On Tue, 2022-03-15 at 15:27 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Pre-determine the frontbuffer_bits for the each pipe during
> intel_drrs_enable(). Will become useful for bigjoiner use cases
> soon.
Reviewed-by: José Roberto de Souza
>
> Signed-off-by: Ville Syrjälä
> ---
>
On Tue, 2022-03-15 at 15:27 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Now that DRRS can operate on multiple pipes we need to make sure
> one pipe doesn't throw away the other pipe's frontbuffer_bits before
> said pipe can handle them.
>
Reviewed-by: José Roberto de Souza
>
On Tue, 2022-03-15 at 15:27 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> The DRRS refresh rate should be indented by one tab like the
> other per-crtc DRRS stuff.
>
Reviewed-by: José Roberto de Souza
> Signed-off-by: Ville Syrjälä
> ---
>
On Mon, 2022-03-14 at 16:42 -0700, Matt Roper wrote:
> Add a new 'steering' node in each gt's debugfs directory that tells
> whether we're using explicit steering for various types of MCR ranges
> and, if so, what MMIO ranges it applies to.
>
> We're going to be transitioning away from implicit
On Mon, 2022-03-14 at 19:08 -0700, Matt Roper wrote:
> From: John Harrison
>
> sseu_dev_info is already a pretty large structure which will likely
> continue to grow when future platforms increase potential DSS and EU
> counts. Let's switch the stack placement of this structure in debugfs
>
On Thu, 2022-03-10 at 23:52 +0200, Ville Syrjälä wrote:
> On Thu, Mar 10, 2022 at 12:05:17PM -0800, José Roberto de Souza wrote:
> > Commit 13ea6db2cf24 ("drm/i915/edp: Ignore short pulse when panel
> > powered off") completely broke short pulse handling for eDP as it is
> > usually generated by
On Thu, 2022-03-10 at 02:47 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Get rid of the ugly intel_dp dependency, and one more crtc->config
> usage by storing the DRRS state under intel_crtc. intel_drrs_enable()
> copies what it needs from the crtc state, after which DRRS can be
>
On Wed, 2022-03-09 at 13:51 +, Hogander, Jouni wrote:
> Hello Jose,
>
> See my question/comment below.
>
> On Tue, 2022-03-08 at 07:41 -0800, José Roberto de Souza wrote:
> > If a error happens and sink_not_reliable is set, PSR should be
> > disabled
> > for good but that is not happening.
>
On Sun, 2022-02-27 at 05:27 +, Patchwork wrote:
Patch Details
Series: drm/i915/psr: Set "SF Partial Frame Enable" also on full update (rev5)
URL:https://patchwork.freedesktop.org/series/100633/
State: success
Details:
On Thu, 2022-02-24 at 17:39 +0200, Ville Syrjälä wrote:
> On Thu, Feb 24, 2022 at 01:49:36PM +0000, Souza, Jose wrote:
> > On Thu, 2022-02-24 at 15:25 +0200, Ville Syrjälä wrote:
> > > On Thu, Feb 24, 2022 at 01:17:35PM +, Souza, Jose wrote:
> > > > On Thu, 20
+ Rodrigo
On Thu, 2022-02-24 at 15:11 +0200, Ville Syrjälä wrote:
> On Thu, Feb 24, 2022 at 03:06:30PM +0200, Ville Syrjälä wrote:
> > On Thu, Feb 24, 2022 at 01:01:24PM +0000, Souza, Jose wrote:
> > > On Thu, 2022-02-24 at 12:12 +0200, Ville Syrjälä wrote:
> > > >
On Thu, 2022-02-24 at 15:25 +0200, Ville Syrjälä wrote:
> On Thu, Feb 24, 2022 at 01:17:35PM +0000, Souza, Jose wrote:
> > On Thu, 2022-02-24 at 12:20 +0200, Ville Syrjälä wrote:
> > > On Wed, Feb 23, 2022 at 12:55:51PM -0800, José Roberto de Souza wrote:
> >
On Thu, 2022-02-24 at 12:20 +0200, Ville Syrjälä wrote:
> On Wed, Feb 23, 2022 at 12:55:51PM -0800, José Roberto de Souza wrote:
>
> > + union {
> > + /* icl+ TC */
> > + struct {
> > + u32 mg_refclkin_ctl;
> > + u32
On Thu, 2022-02-24 at 12:12 +0200, Ville Syrjälä wrote:
> On Wed, Feb 23, 2022 at 11:41:03AM -0800, José Roberto de Souza wrote:
> > Some users are suffering with PSR2 issues that are under debug or
> > issues that were root caused to panel firmware, to make life of those
> > users easier here
On Wed, 2022-02-23 at 21:58 +0200, Imre Deak wrote:
> On Tue, Feb 22, 2022 at 06:20:45AM -0800, José Roberto de Souza wrote:
> [...]
> > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > index ba2fdfce15792..4360e1c9266d8 100644
> >
On Sat, 2022-02-19 at 17:35 +, Patchwork wrote:
Patch Details
Series: drm/i915/rps/tgl+: Remove RPS interrupt support
URL:https://patchwork.freedesktop.org/series/100426/
State: success
Details:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22336/index.html
CI Bug Log -
On Wed, 2022-02-23 at 14:48 +0200, Jouni Högander wrote:
> Currently we are observing occasional screen flickering when
> PSR2 selective fetch is enabled. More specifically glitch seems
> to happen on full frame update when cursor moves to coords
> x = -1 or y = -1.
>
> According to Bspec SF
On Wed, 2022-02-23 at 11:03 +, Patchwork wrote:
Patch Details
Series: drm/i915/tgl: Simply subplatform detection (rev2)
URL:https://patchwork.freedesktop.org/series/100517/
State: failure
Details:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22354/index.html
CI Bug Log -
On Fri, 2022-02-18 at 14:31 +0200, Imre Deak wrote:
> Add display workaround # 1309179469 , which fixes a PHY hang when
> switching from TBT mode to DP-alt/legacy mode. The workaround also
> requires an IFWI/PHY firmware change, before that this change has no
> effect (the DKL_PCS_DW5/SOFTRESET
On Fri, 2022-02-18 at 01:54 -0800, Lucas De Marchi wrote:
> PORT_TC1 is still not being initialized - that is the port that uses phy
> E. However the intel_phy_is_snps() reports that phy as being present,
> which causes warnings about unclaimed access to the PHY_MISC register.
> Even with some
On Fri, 2022-02-11 at 00:04 +, Patchwork wrote:
Patch Details
Series: series starting with [1/2] drm/i915/display: Group PSR2 prog sequences
and workarounds
URL:https://patchwork.freedesktop.org/series/99989/
State: success
Details:
On Thu, 2022-02-17 at 13:32 +, Patchwork wrote:
Patch Details
Series: drm/i915/display/tgl+: Implement new PLL programming step (rev3)
URL:https://patchwork.freedesktop.org/series/99867/
State: failure
Details:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22296/index.html
CI
On Thu, 2022-02-17 at 17:22 +0200, Imre Deak wrote:
> BIOS may leave a TypeC PHY in a connected state even though the
> corresponding port is disabled. This will prevent any hotplug events
> from being signalled (after the monitor deasserts and then reasserts its
> HPD) until the PHY is
On Tue, 2022-02-15 at 12:31 +, Hogander, Jouni wrote:
> On Thu, 2022-02-10 at 10:52 -0800, José Roberto de Souza wrote:
> > PSR2 workaround required when mode has delayed vblank.
> >
> > BSpec: 52890
> > BSpec: 49421
> > Cc: Jouni Högander
> > Signed-off-by: José Roberto de Souza
> > ---
>
On Tue, 2022-02-15 at 15:47 +0200, Lisovskiy, Stanislav wrote:
> On Thu, Feb 10, 2022 at 10:52:23AM -0800, José Roberto de Souza wrote:
> > PSR2 workaround required when mode has delayed vblank.
> >
> > BSpec: 52890
> > BSpec: 49421
> > Cc: Jouni Högander
> > Signed-off-by: José Roberto de Souza
On Mon, 2022-02-07 at 16:38 -0500, Lyude Paul wrote:
> As we've unfortunately started to come to expect from PSR on Intel
> platforms, PSR2 selective fetch is not at all ready to be enabled on
> Tigerlake as it results in severe flickering issues - at least on this
> ThinkPad X1 Carbon 9th
On Mon, 2022-01-31 at 08:59 -0800, Lucas De Marchi wrote:
> Following what was done in drm_cache.c, when the stub for
> remap_io_mapping() was added in commit 67c430bbaae1 ("drm/i915: Skip
> remap_io_mapping() for non-x86 platforms"), it included a log message
> with pr_err(). However just the
On Mon, 2022-01-31 at 08:59 -0800, Lucas De Marchi wrote:
> Only x86 and in some cases PPC have support added in drm_cache.c for the
> clflush class of functions. However warning once is sufficient to taint
> the log instead of spamming it with "Architecture has no drm_cache.c
> support" every few
On Mon, 2022-01-31 at 08:59 -0800, Lucas De Marchi wrote:
> Architectures others than x86 have a stub implementation calling
> WARN_ON_ONCE(). The appropriate headers need to be included, otherwise
> the header-test target will fail with:
>
> HDRTEST drivers/gpu/drm/i915/i915_mm.h
> In file
On Wed, 2022-01-26 at 12:43 +0200, Imre Deak wrote:
> The TCSS_DDI_STATUS register is indexed by tc_port not by the FIA port
> index, fix this up. This only caused an issue on TC#3/4 ports in legacy
> mode, as in all other cases the two indices either match (on TC#1/2) or
> the
On Fri, 2022-01-21 at 13:30 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Use REG_BIT() & co. for the pre-skl primary plane registers.
> Also give everything a consistent namespace.
>
> v2: s/DSP/DISP/ to avoid confusion (José)
> Use DISP_WIDTH rather than DISP_POS_X for DSPSIZE
On Tue, 2022-01-18 at 02:55 +0200, Ville Syrjälä wrote:
> On Wed, Jan 12, 2022 at 08:12:31PM +0000, Souza, Jose wrote:
> > On Wed, 2021-12-01 at 17:25 +0200, Ville Syrjala wrote:
> > > @@ -427,9 +427,9 @@ static void i9xx_plane_update_noarm(struct
> &
On Wed, 2021-12-01 at 17:25 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Use REG_BIT() & co. to polish the cursor plane registers.
Reviewed-by: José Roberto de Souza
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_cursor.c | 25 ---
>
On Wed, 2021-12-01 at 17:25 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Use REG_BIT() & co. to polish the g4x+ sprite plane registers.
Reviewed-by: José Roberto de Souza
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_sprite.c | 12 ++--
>
On Wed, 2021-12-01 at 17:25 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Use REG_BIT() & co. to polish the vlv/chv sprite plane registers.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_sprite.c | 9 +-
> drivers/gpu/drm/i915/i915_reg.h |
On Wed, 2021-12-01 at 17:25 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Use REG_BIT() & co. to polish the ivb+ sprite plane registers.
Reviewed-by: José Roberto de Souza
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_sprite.c | 20 +++--
>
On Thu, 2022-01-13 at 19:59 +, Patchwork wrote:
Patch Details
Series: drm/i915/display/adlp: Implement new step in the TC voltage swing prog
sequence
URL:https://patchwork.freedesktop.org/series/98853/
State: success
Details:
On Thu, 2022-01-13 at 17:56 +, Patchwork wrote:
Patch Details
Series: drm/i915/display/ehl: Update voltage swing table
URL:https://patchwork.freedesktop.org/series/98844/
State: failure
Details:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21994/index.html
CI Bug Log -
On Wed, 2021-12-01 at 17:25 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Use REG_BIT() & co. for the pre-skl primary plane registers.
> Also give everything a consistent namespace.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/i9xx_plane.c| 99
On Thu, 2021-12-02 at 13:57 +0200, Ville Syrjälä wrote:
> On Wed, Dec 01, 2021 at 05:26:50PM +0000, Souza, Jose wrote:
> > On Wed, 2021-12-01 at 17:25 +0200, Ville Syrjala wrote:
> > > From: Ville Syrjälä
> > >
> > > Polish the skl+ universal plane register d
On Wed, 2021-12-01 at 17:25 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> There's no need to have separate masks for the stride bitfield
> in PLANE_STRIDE for different platforms. All the extra bits
> are hardcoded to zero anyway.
>
> Also the masks we're using now don't even match the
On Wed, 2022-01-12 at 16:00 +0200, Jouni Högander wrote:
> Now as we have has_psr2_sel_fetch flag we can rely that
> instead of checking each platform separately.
>
> Signed-off-by: Jouni Högander
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 7 ---
> drivers/gpu/drm/i915/i915_drv.h
On Wed, 2022-01-12 at 13:27 +0200, Jani Nikula wrote:
> The lines_to_wait info from VBT is never used. Remove.
>
Reviewed-by: José Roberto de Souza
> Cc: José Roberto de Souza
> Cc: Jouni Högander
> Cc: Ville Syrjälä
> Signed-off-by: Jani Nikula
>
> ---
>
> Not exactly a v2, but rather a
-Original Message-
From: Souza, Jose mailto:jose.so...@intel.com>>
Sent: Monday, January 10, 2022 8:14 PM
To: Schweikhardt, Markus
mailto:markus.schweikha...@intel.com>>;
intel-gfx@lists.freedesktop.org<mailto:intel-gfx@lists.freedesktop.org>
Subject: Re: [Intel
On Mon, 2022-01-10 at 15:45 -0800, clinton.a.tay...@intel.com wrote:
> From: Clint Taylor
>
> Updated new values from BSPEC.
>
> BSPEC: 53920
>
Reviewed-by: José Roberto de Souza
> Cc: Jani Nikula
> Cc: José Roberto de Souza
> Cc: Imre Deak
> Signed-off-by: Clint Taylor
> ---
>
On Mon, 2022-01-10 at 18:56 +, Schweikhardt, Markus wrote:
> Hi all,
>
> I would like to monitor the frequency of the iGPU of my TGL platform while
> running glmark2 in bursts which means glmark2 is 5secrunning and 5sec not
> running.I disabled RC6 by echo 0 >
On Tue, 2022-01-04 at 21:21 +0530, Manna, Animesh wrote:
> Hi,
>
> > -Original Message-
> > From: Souza, Jose
> > Sent: Wednesday, November 24, 2021 1:19 AM
> > To: dri-de...@lists.freedesktop.org; Manna, Animesh
> > ; intel-gfx@lists.freedesktop.o
On Thu, 2021-12-02 at 13:56 +0200, Ville Syrjälä wrote:
> On Wed, Dec 01, 2021 at 05:18:54PM +0000, Souza, Jose wrote:
> > On Wed, 2021-12-01 at 17:25 +0200, Ville Syrjala wrote:
> > > From: Ville Syrjälä
> > >
> > > Replace the "sizes are 0 based&qu
On Fri, 2021-12-03 at 15:13 +0200, Jani Nikula wrote:
> Localize HOBL and low vswing VBT lookups to a couple of small helpers,
> and get rid of a bunch of local variables.
Reviewed-by: José Roberto de Souza
>
> Signed-off-by: Jani Nikula
> ---
> .../drm/i915/display/intel_ddi_buf_trans.c
On Wed, 2021-12-01 at 16:30 -0800, Lucas De Marchi wrote:
> PAT can be disabled on boot with "nopat" in the command line. Replace
> one x86-ism with another, which is slightly more correct to prepare for
> supporting other architectures.
Reviewed-by: José Roberto de Souza
>
> Cc: Matt Roper
>
On Wed, 2021-12-01 at 02:33 -0800, Anusha Srivatsa wrote:
> Add the PCH ID for RPL-S.
>
> v2: Self contained commit message (Jani)
Reviewed-by: José Roberto de Souza
>
> Cc: Jani Nikula
> Cc: Swathi Dhanavanthri
> Signed-off-by: Anusha Srivatsa
> ---
> drivers/gpu/drm/i915/intel_pch.c | 1
On Wed, 2021-12-01 at 02:33 -0800, Anusha Srivatsa wrote:
> Raptor Lake S(RPL-S) is a version 12
> Display, Media and Render. For all i915
> purposes it is the same as Alder Lake S (ADL-S).
>
> Introduce RPL-S as a subplatform
> of ADL-S. This patch adds PCI ids for RPL-S.
>
> v2: Update PCI
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