On Wed, Mar 18, 2015 at 09:00:20AM +0100, Daniel Vetter wrote:
On Tue, Mar 17, 2015 at 09:20:11PM +, Konduru, Chandra wrote:
-Original Message-
From: Roper, Matthew D
Sent: Tuesday, March 17, 2015 9:13 AM
To: Konduru, Chandra
Cc: intel-gfx@lists.freedesktop.org;
On Wednesday 18 March 2015 01:48 PM, Deepak S wrote:
On Friday 06 March 2015 08:36 PM, Chris Wilson wrote:
If we hit a vblank and see that have a pageflip queue but not yet
processed, ensure that the GPU is running at maximum in order to clear
the backlog. Pageflips are only queued for the
On Wed, Mar 18, 2015 at 10:37:16AM +0100, Paul Bolle wrote:
Imre Deak schreef op ma 02-03-2015 om 13:04 [+0200]:
Bjørn reported that his machine hang during hibernation and eventually
bisected the problem to the following commit:
commit da2bc1b9db3351addd293e5b82757efe1f77ed1d
Author:
On Wednesday 18 March 2015 03:18 PM, Daniel Vetter wrote:
On Wed, Mar 18, 2015 at 01:42:58PM +0530, Deepak S wrote:
I guess your empty reply wasn't intentional?
-Daniel
Sorry, that was not intentional :)
On Friday 06 March 2015 08:36 PM, Chris Wilson wrote:
Reuse the same reclocking
On Wednesday 18 March 2015 03:18 PM, Chris Wilson wrote:
Reuse the same reclocking strategy for Baytail as on its bigger brethren,
Sandybridge and Ivybridge. In particular, this makes the device quicker
to reclock (both up and down) though the tendency now is to downclock
more aggressively to
In the original code then if WARN_ON(i915_is_ggtt(vm) != !!ggtt_view)
was true then we leak vma. Presumably that doesn't happen often but
static checkers complain and this bug is easy to fix.
Fixes: c3bbb6f2825d ('drm/i915: Do not use ggtt_view with (aliasing) PPGTT')
Signed-off-by: Dan
On Wed, Mar 18, 2015 at 12:26:49PM +0530, Deepak S wrote:
On Friday 06 March 2015 08:36 PM, Chris Wilson wrote:
I think we should modify adj in GEN6_PM_RP_UP_EI_EXPIRED?
if not not we might request higher freq since we add adj to new_delay before
request freq.
Oh yeah. That branch didn't
On Wed, Mar 18, 2015 at 12:26:49PM +0530, Deepak S wrote:
On Friday 06 March 2015 08:36 PM, Chris Wilson wrote:
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/i915_irq.c | 27 ---
1 file changed, 12 insertions(+), 15 deletions(-)
On ke, 2015-03-18 at 09:37 +0100, Daniel Vetter wrote:
On Tue, Mar 17, 2015 at 04:22:33PM +0200, Imre Deak wrote:
On ti, 2015-03-17 at 14:51 +0100, Daniel Vetter wrote:
On Tue, Mar 17, 2015 at 11:40:01AM +0200, Imre Deak wrote:
From: Jesse Barnes jbar...@virtuousgeek.org
Broxton
On Tue, Mar 17, 2015 at 04:22:33PM +0200, Imre Deak wrote:
On ti, 2015-03-17 at 14:51 +0100, Daniel Vetter wrote:
On Tue, Mar 17, 2015 at 11:40:01AM +0200, Imre Deak wrote:
From: Jesse Barnes jbar...@virtuousgeek.org
Broxton has the same panel fitter registers as Skylake.
Hi Dave,
Another drm-misch pull request. Mostly the fbdev sizes deconfusion series
from Rob, everything else is small stuff all over. And the large i2c over
aux transfers patch, too.
Cheers, Daniel
The following changes since commit 7eb5f302bbe78b88da8b2008c502c1975e75db05:
drm: Check in
On Wednesday 18 March 2015 02:50 PM, Chris Wilson wrote:
On Wed, Mar 18, 2015 at 12:26:49PM +0530, Deepak S wrote:
On Friday 06 March 2015 08:36 PM, Chris Wilson wrote:
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/i915_irq.c | 27
On Friday 06 March 2015 08:36 PM, Chris Wilson wrote:
Use both up/down manual ei calcuations for symmetry and greater
flexibility for reclocking, instead of faking the down interrupt based
on a fixed integer number of up interrupts.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
On Wed, 18 Mar 2015, Steven Rostedt rost...@goodmis.org wrote:
On Tue, 17 Mar 2015 08:53:21 +0100
Daniel Vetter dan...@ffwll.ch wrote:
Can you please cherry pick 42a7b088127f (\drm/i915: Make sure the primary
plane is enabled before reading out the fb state\) from -next to 4.0-rc
to test
On Friday 06 March 2015 08:36 PM, Chris Wilson wrote:
With boosting for missed pageflips, we have a much stronger indication
of when we need to (temporarily) boost GPU frequency to ensure smooth
delivery of frames. So now only allow each client to perform one RPS boost
in each period of GPU
On Tue, Mar 17, 2015 at 03:36:51PM +, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
This makes the interface consistent to old i915_gem_obj_ggtt_pin.
Signed-off-by: Tvrtko Ursulin tvrtko.ursu...@intel.com
Cc: Joonas Lahtinen joonas.lahti...@linux.intel.com
Ok our
On Wed, Mar 18, 2015 at 11:53:16AM +0900, Michel Dänzer wrote:
drm_vblank_count_and_time() doesn't return the correct sequence number
while the vblank interrupt is disabled, does it? It returns the sequence
number from the last time vblank_disable_and_save() was called (when the
vblank
Rewrite commit 31685c258e0b0ad6aa486c5ec001382cf8a64212
Author: Deepak S deepa...@linux.intel.com
Date: Thu Jul 3 17:33:01 2014 -0400
drm/i915/vlv: WA for Turbo and RC6 to work together.
Other than code clarity, the major improvement is to disable the extra
interrupts generated when idle.
If we hit a vblank and see that have a pageflip queue but not yet
processed, ensure that the GPU is running at maximum in order to clear
the backlog. Pageflips are only queued for the following vblank, if we
miss it, there will be a visible stutter. Boosting the GPU frequency
doesn't prevent us
The issue is that by computing the last_adj value after applying the
clamping, we can end up with a bogus value for feeding into the next RPS
autotuning step.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
Cc: Daniel Vetter daniel.vet...@ffwll.ch
Cc: Deepak S deepa...@linux.intel.com
Reuse the same reclocking strategy for Baytail as on its bigger brethren,
Sandybridge and Ivybridge. In particular, this makes the device quicker
to reclock (both up and down) though the tendency now is to downclock
more aggressively to compensate for the RPS boosts.
v2: Rebase
Signed-off-by:
A few r-bs and suggestions from Deepak rebased onto -nightly.
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
We were missing a convenience stub to aquire the right mutex whilst
dropping the request, so add it.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/i915_drv.h | 13 +
drivers/gpu/drm/i915/i915_gem.c | 8 ++--
2 files changed, 15 insertions(+), 6
On Tue, Mar 17, 2015 at 02:19:18PM +, Tvrtko Ursulin wrote:
Hi,
On 03/16/2015 12:11 PM, Joonas Lahtinen wrote:
GGTT views are only applicable when dealing with GGTT. Change the code to
reject ggtt_view where it should not be used and require it when it should
be.
v2:
- Dropped
On Wed, Mar 18, 2015 at 10:48:36AM +0100, Daniel Vetter wrote:
On Wed, Mar 18, 2015 at 01:42:58PM +0530, Deepak S wrote:
I guess your empty reply wasn't intentional?
I heard This needs to be rebased against -nightly.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
On Wed, Mar 18, 2015 at 02:23:01PM +0530, Ramalingam C wrote:
cc += intel-gfx
On Wednesday 18 March 2015 02:12 PM, Ramalingam C wrote:
Hi,
Is there anyway I can test the front buffer tracking?
On latest drm-intel-nightly, I am observing that when ubuntu bootsup after
few secs (like
Reduce default number of repeats a lot. High repeat count is only
useful for microbenchmarking, not that much for regression testing.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=87131
Signed-off-by: Daniel Vetter daniel.vet...@intel.com
---
tests/gem_exec_lut_handle.c | 38
On Tue, Mar 17, 2015 at 08:43:02PM +, Konduru, Chandra wrote:
-Original Message-
From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel
Vetter
Sent: Tuesday, March 17, 2015 7:22 AM
To: Konduru, Chandra
Cc: intel-gfx@lists.freedesktop.org; Conselvan De
On Wed, 18 Mar 2015, Dan Carpenter dan.carpen...@oracle.com wrote:
In the original code then if WARN_ON(i915_is_ggtt(vm) != !!ggtt_view)
was true then we leak vma. Presumably that doesn't happen often but
static checkers complain and this bug is easy to fix.
Fixes: c3bbb6f2825d ('drm/i915:
On Wed, Mar 18, 2015 at 11:14:15AM +0530, Deepak S wrote:
@@ -4761,6 +4762,8 @@ static void cherryview_init_gt_powersave(struct
drm_device *dev)
I think we missed initializing idle_freq in valleyview init platform?
Indeed, I did.
Thanks,
-Chris
--
Chris Wilson, Intel Open Source
On 3/3/2015 11:48 AM, akash goel wrote:
On Fri, Feb 20, 2015 at 11:15 PM, Michel Thierry
michel.thie...@intel.com wrote:
From: Ben Widawskybenjamin.widaw...@intel.com
This transitional patch doesn't do much for the existing code. However,
it should make upcoming patches to use the full 48b
On 3/3/2015 12:16 PM, akash goel wrote:
On Fri, Feb 20, 2015 at 11:15 PM, Michel Thierry
michel.thie...@intel.com wrote:
From: Ben Widawskybenjamin.widaw...@intel.com
Up until now, ppgtt-pdp has always been the root of our page tables.
Legacy 32b addresses acted like it had 1 PDP with 4
On Wed, Mar 18, 2015 at 04:45:08PM +0530, Deepak S wrote:
+if (val != dev_priv-rps.cur_freq) {
vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
+gen6_set_rps_thresholds(dev_priv, val);
I think gen6_set_rps_thresholds should be under baytrail specific with
On Friday 06 March 2015 08:36 PM, Chris Wilson wrote:
Reuse the same reclocking strategy for Baytail as on its bigger brethren,
Sandybridge and Ivybridge. In particular, this makes the device quicker
to reclock (both up and down) though the tendency now is to downclock
more aggressively to
cc += intel-gfx
On Wednesday 18 March 2015 02:12 PM, Ramalingam C wrote:
Hi,
Is there anyway I can test the front buffer tracking?
On latest drm-intel-nightly, I am observing that when ubuntu bootsup
after few secs (like ~15Secs)
there no call from intel_fb_obj_invalidate() to invalidate
On Wed, Mar 18, 2015 at 10:46:04AM +0100, Daniel Vetter wrote:
Two code changes:
- Extract i915_gem_shrinker_init.
- Inline i915_gem_object_is_purgeable since we open-code it everywhere
else too.
This already has the benefit of pulling all the shrinker code
together, next patch adds a
On Wed, Mar 18, 2015 at 10:46:05AM +0100, Daniel Vetter wrote:
+/**
+ * i915_gem_shrink - Shrink buffer object caches
+ * @dev_priv: i915 device
+ * @target: memory space to make available, in pages
Not memory space, too similar to VM address space.
@target: Amount of memory to make
On Wednesday 18 March 2015 03:18 PM, Chris Wilson wrote:
When we idle, we set the GPU frequency to the hardware minimum (not user
minimum). We introduce a new variable to distinguish between the
different roles, and to allow easy tuning of the idle frequency without
impacting over aspects of
For the atomic conversion, the mode set paths need to be changed to rely
on an atomic state instead of using the staged config. By using an
atomic state for the legacy code, we will be able to convert the code
base in small chunks.
v2: Squash patch that adds stat argument to intel_set_mode().
On Friday 06 March 2015 08:36 PM, Chris Wilson wrote:
Rewrite commit 31685c258e0b0ad6aa486c5ec001382cf8a64212
Author: Deepak S deepa...@linux.intel.com
Date: Thu Jul 3 17:33:01 2014 -0400
drm/i915/vlv: WA for Turbo and RC6 to work together.
Other than code clarity, the major
On Tue, Mar 17, 2015 at 09:20:11PM +, Konduru, Chandra wrote:
-Original Message-
From: Roper, Matthew D
Sent: Tuesday, March 17, 2015 9:13 AM
To: Konduru, Chandra
Cc: intel-gfx@lists.freedesktop.org; Vetter, Daniel; Conselvan De Oliveira,
Ander
Subject: Re: [PATCH
On Tue, Mar 17, 2015 at 06:54:30PM +, Konduru, Chandra wrote:
-Original Message-
From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel
Vetter
Sent: Tuesday, March 17, 2015 7:20 AM
To: Konduru, Chandra
Cc: intel-gfx@lists.freedesktop.org; Conselvan De
On Sun, Mar 15, 2015 at 6:55 AM, Chandra Konduru
chandra.kond...@intel.com wrote:
+ /*
+* check for rect size:
+* min sizes in case of scaling involved
+* max sizes in all cases
+*/
+ if ((need_scaling
+ (src_w
On Tue, Mar 17, 2015 at 06:40:18PM +0200, Ville Syrjälä wrote:
On Tue, Mar 17, 2015 at 05:18:54PM +0200, Jani Nikula wrote:
Allow for a larger receive data size, and check if the receiver returned
the number of bytes written. Without this, we've basically skipped all
the unwritten bytes for
On Wed, Mar 18, 2015 at 10:36:45AM +0200, Jani Nikula wrote:
On Wed, 18 Mar 2015, Dan Carpenter dan.carpen...@oracle.com wrote:
In the original code then if WARN_ON(i915_is_ggtt(vm) != !!ggtt_view)
was true then we leak vma. Presumably that doesn't happen often but
static checkers complain
Imre Deak schreef op ma 02-03-2015 om 13:04 [+0200]:
Bjørn reported that his machine hang during hibernation and eventually
bisected the problem to the following commit:
commit da2bc1b9db3351addd293e5b82757efe1f77ed1d
Author: Imre Deak imre.d...@intel.com
Date: Thu Oct 23 19:23:26 2014
On 3/3/2015 12:23 PM, akash goel wrote:
On Fri, Feb 20, 2015 at 11:15 PM, Michel Thierry
michel.thie...@intel.com wrote:
From: Ben Widawskybenjamin.widaw...@intel.com
Note that there is no gen8 ppgtt debug_dump function yet.
Signed-off-by: Ben Widawskyb...@bwidawsk.net
Signed-off-by: Michel
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 5981
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -1 268/268
On Wednesday 18 March 2015 03:18 PM, Chris Wilson wrote:
If we hit a vblank and see that have a pageflip queue but not yet
processed, ensure that the GPU is running at maximum in order to clear
the backlog. Pageflips are only queued for the following vblank, if we
miss it, there will be a
On Wed, Mar 18, 2015 at 11:19:32AM +0100, Daniel Vetter wrote:
Reduce default number of repeats a lot. High repeat count is only
useful for microbenchmarking, not that much for regression testing.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=87131
This just to hide the regression
And remove one bogus * from i915_gem_gtt.c since that's not a
kerneldoc there.
Signed-off-by: Daniel Vetter daniel.vet...@intel.com
---
Documentation/DocBook/drm.tmpl | 13 +++-
drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
drivers/gpu/drm/i915/i915_gem_shrinker.c | 34
Two code changes:
- Extract i915_gem_shrinker_init.
- Inline i915_gem_object_is_purgeable since we open-code it everywhere
else too.
This already has the benefit of pulling all the shrinker code
together, next patch adds a bit of kerneldoc.
Signed-off-by: Daniel Vetter daniel.vet...@intel.com
On ke, 2015-03-18 at 09:41 +0100, Daniel Vetter wrote:
On Wed, Mar 18, 2015 at 10:36:45AM +0200, Jani Nikula wrote:
On Wed, 18 Mar 2015, Dan Carpenter dan.carpen...@oracle.com wrote:
In the original code then if WARN_ON(i915_is_ggtt(vm) != !!ggtt_view)
was true then we leak vma.
On ti, 2015-03-17 at 15:45 +, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
It will be used in a later patch and also convert all height parameters
from int to unsigned int.
v2: Rebased for fb modifiers.
v3: Fixed v2 rebase.
v4:
* Height should be unsigned
On Wednesday 18 March 2015 04:53 PM, Chris Wilson wrote:
On Wed, Mar 18, 2015 at 04:45:08PM +0530, Deepak S wrote:
+ if (val != dev_priv-rps.cur_freq) {
vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
+ gen6_set_rps_thresholds(dev_priv, val);
I
On Fri, 13 Mar 2015, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
When an i2c WRITE gets an i2c defer or short i2c ack reply, we are
supposed to switch the request from I2C_WRITE to I2C_WRITE_STATUS_UPDATE
when we continue to poll for the completion
On Mon, Mar 16, 2015 at 5:42 AM, Shobhit Kumar shobhit.ku...@intel.com wrote:
The CRC (Crystal Cove) PMIC, controls the panel enable and disable
signals for BYT for dsi panels. This is indicated in the VBT fields. Use
that to initialize and use GPIO based control for these signals.
v2: Use
On ti, 2015-03-17 at 15:45 +, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
To support frame buffer rotation we need to be able to pass on the information
on what kind of GGTT view is required for display.
This patch just adds the parameter and makes all the
On Wed, Mar 18, 2015 at 12:50:51PM +0100, Linus Walleij wrote:
On Thu, Mar 12, 2015 at 4:06 PM, Kumar, Shobhit shobhit.ku...@intel.com
wrote:
On Mon, 2015-03-09 at 18:15 +0100, Linus Walleij wrote:
On Fri, Mar 6, 2015 at 5:23 PM, Kumar, Shobhit shobhit.ku...@intel.com
wrote:
There
And remove one bogus * from i915_gem_gtt.c since that's not a
kerneldoc there.
v2: Review from Chris:
- Clarify memory space to better distinguish from address space.
- Add note that shrink doesn't guarantee the freed memory and that
users must fall back to shrink_all.
- Explain how pinning
On Wed, Mar 18, 2015 at 09:48:23AM +, Chris Wilson wrote:
Use both up/down manual ei calcuations for symmetry and greater
flexibility for reclocking, instead of faking the down interrupt based
on a fixed integer number of up interrupts.
Signed-off-by: Chris Wilson
On Thu, Mar 12, 2015 at 4:06 PM, Kumar, Shobhit shobhit.ku...@intel.com wrote:
On Mon, 2015-03-09 at 18:15 +0100, Linus Walleij wrote:
On Fri, Mar 6, 2015 at 5:23 PM, Kumar, Shobhit shobhit.ku...@intel.com
wrote:
There are actually two lines for Panel Power control and Backlight
On Fri, 13 Mar 2015, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
When we get an i2c defer or short ack for i2c-over-aux write we need
to switch to WRITE_STATUS_UPDATE to poll for the completion of the
original request.
i915 doesn't try to interpret
On Fri, 13 Mar 2015, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Rename the I2C_STATUS request to I2C_WRITE_STATUS_UPDATE to match the
spec.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
Reviewed-by: Jani Nikula jani.nik...@intel.com
On Thu, Mar 12, 2015 at 5:31 PM, Shobhit Kumar shobhit.ku...@intel.com wrote:
Export PANEL_EN/DISABLE (offset 0x52) as additional GPIO. Needed
by display driver to enable the DSI panel on BYT platform where
the Panel EN/Disable control is routed thorugh CRC PMIC
CC: Samuel Ortiz
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 5984
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -1 268/268
On Wed, Mar 18, 2015 at 11:19:46AM +, Chris Wilson wrote:
On Wed, Mar 18, 2015 at 11:19:32AM +0100, Daniel Vetter wrote:
Reduce default number of repeats a lot. High repeat count is only
useful for microbenchmarking, not that much for regression testing.
Bugzilla:
Rodrigo Vivi rodrigo.v...@intel.com writes:
From: Imre Deak imre.d...@intel.com
Due this typo we don't save/restore the GFX_MAX_REQ_COUNT register across
suspend/resume, so fix this.
This was introduced in
commit ddeea5b0c36f3665446518c609be91f9336ef674
Author: Imre Deak
On Wed, Mar 18, 2015 at 03:52:31PM +0200, Joonas Lahtinen wrote:
On ti, 2015-03-17 at 15:45 +, Tvrtko Ursulin wrote:
@@ -3993,7 +3994,9 @@ i915_gem_object_pin_to_display_plane(struct
drm_i915_gem_object *obj,
* (e.g. libkms for the bootup splash), we have to ensure that we
On 03/18/2015 10:30 AM, Chris Wilson wrote:
On Wed, Mar 18, 2015 at 11:53:16AM +0900, Michel Dänzer wrote:
drm_vblank_count_and_time() doesn't return the correct sequence number
while the vblank interrupt is disabled, does it? It returns the sequence
number from the last time
On Wed, Mar 18, 2015 at 02:50:43PM +0100, Daniel Vetter wrote:
And I haven't seen a lot of activity to track down the reloc regression
itself.
The cause was obvious. The essence is the multiple redundant atomic
operations added to execbuffer.
-Chris
--
Chris Wilson, Intel Open Source
On ti, 2015-03-17 at 15:45 +, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
Plane state carries the rotation information which is needed for determining
the appropriate GGTT view type.
This just adds the parameter with the actual usage coming in future patches.
I'd fix the below code style corrections, the functionality is ok.
On ti, 2015-03-17 at 15:45 +, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
For now only default implementation defaulting to normal view.
Signed-off-by: Tvrtko Ursulin tvrtko.ursu...@intel.com
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 5985
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -2 268/268
On Wed, 2015-03-18 at 12:22 +0200, Ville Syrjälä wrote:
We had another bug report which showed similar problems on something
as recent as SNB:
https://bugzilla.kernel.org/show_bug.cgi?id=94241
So I guess we really want to make the check 'gen 7'.
My IVB X1 Carbon doesn't need this quirk, so
Wa32bitGeneralStateOffset Wa32bitInstructionBaseOffset hardware
workarounds require that GeneralStateOffset InstructionBaseOffset
are restricted to a 32 bit address space.
This is a preparatory patch prior to supporting 64bit virtual memory
allocations.
Allow the user space to flag that a
On Thu, Mar 12, 2015 at 12:09:50PM +, Thomas Wood wrote:
On 10 March 2015 at 21:17, jeff.mc...@intel.com wrote:
From: Jeff McGee jeff.mc...@intel.com
New test pm_sseu is intended for any subtest related to the
slice/subslice/EU power gating feature. The sole initial subtest,
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 5986
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -2 268/268
On 03/09/2015 09:55 AM, Chris Wilson wrote:
I woke up one morning and found 50k objects sitting in the batch pool
and every search seemed to iterate the entire list... Painting the
screen in oils would provide a more fluid display.
One issue with the current design is that we only check for
On Wed, Mar 18, 2015 at 04:51:58PM +, Tvrtko Ursulin wrote:
On 03/09/2015 09:55 AM, Chris Wilson wrote:
I woke up one morning and found 50k objects sitting in the batch pool
and every search seemed to iterate the entire list... Painting the
screen in oils would provide a more fluid
On 03/18/2015 05:27 PM, Chris Wilson wrote:
On Wed, Mar 18, 2015 at 04:51:58PM +, Tvrtko Ursulin wrote:
On 03/09/2015 09:55 AM, Chris Wilson wrote:
diff --git a/drivers/gpu/drm/i915/i915_gem_batch_pool.c
b/drivers/gpu/drm/i915/i915_gem_batch_pool.c
index 21f3356cc0ab..1287abf55b84 100644
If we retire requests last, we may use a later seqno and so clear
the requests lists without clearing the active list, leading to
confusion. Hence we should retire requests first for consistency with
the early return. The order used to be important as the lifecycle for
the object on the active
On 03/18/2015 04:57 PM, Nick Hoath wrote:
Wa32bitGeneralStateOffset Wa32bitInstructionBaseOffset hardware
workarounds require that GeneralStateOffset InstructionBaseOffset
are restricted to a 32 bit address space.
This is a preparatory patch prior to supporting 64bit virtual memory
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 5987
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -2 268/268
On Mon, Mar 09, 2015 at 04:13:03PM -0700, jeff.mc...@intel.com wrote:
From: Jeff McGee jeff.mc...@intel.com
Update kernel interface with new I915_GETPARAM ioctl entries for
subslice total and EU total. Add a wrapping function for each
parameter. Userspace drivers need these values when
On Friday 06 March 2015 08:36 PM, Chris Wilson wrote:
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/i915_irq.c | 27 ---
1 file changed, 12 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c
-Original Message-
From: Conselvan De Oliveira, Ander
Sent: Friday, March 13, 2015 2:49 AM
To: intel-gfx@lists.freedesktop.org
Cc: Konduru, Chandra; Conselvan De Oliveira, Ander
Subject: [PATCH 08/19] drm/i915: Don't use encoder-new_crtc in
intel_modeset_pipe_config()
Move
tests/igt.py: add igt env to enable or disable dmesg triage
framework/test/base.py: trigger dmesg triage depending on dmesg log occurrence
framework/dmesg.py: employ dmesg triage simply for Linux dmesg
dmesg_triage/*: deal with kmsg log with pre-defined dmesg oops pattern
In general, if dmesg
-Original Message-
From: Conselvan De Oliveira, Ander
Sent: Wednesday, March 18, 2015 12:57 AM
To: intel-gfx@lists.freedesktop.org
Cc: Konduru, Chandra; Conselvan De Oliveira, Ander
Subject: [PATCH v4] drm/i915: Allocate a drm_atomic_state for the legacy
modeset code
For the
-Original Message-
From: Conselvan De Oliveira, Ander
Sent: Friday, March 13, 2015 2:49 AM
To: intel-gfx@lists.freedesktop.org
Cc: Konduru, Chandra; Conselvan De Oliveira, Ander
Subject: [PATCH v2 00/19] Remove depencies on staged config for atomic
transition
Here's v2 with
Yeah, MAP_FIXED sounds a bit more ambitious and though I think it would
work for OCL 2.0 pointer sharing, it's a little different than we were
planning.
To summarize, we have three possible approaches, each with its own
problems:
1) simple patch to avoid binding at address 0 in PPGTT:
This updates my old patch for this, but w/o fixing the locking issue
Ville mentioned. In looking at it, it seems like the sync point should
be at a higher level, maybe at the level of the atomic mode setting async
serialization points? Another possibility would be to make it a lazy
init type
From: Paulo Zanoni paulo.r.zan...@intel.com
Otherwise we'll get a WARN from drm_wait_one_vblank() saying that
vblanks are not available (since they were already disabled in
crtc_disable()).
This is certainly a regresison, but QA couldn't bisect it due to
other regressions breaking the bisect.
On Mon, Mar 02, 2015 at 03:39:27PM -0800, jeff.mc...@intel.com wrote:
From: Jeff McGee jeff.mc...@intel.com
2 small details, but otherwise:
Reviewed-by: Damien Lespiau damien.lesp...@intel.com
Update kernel interface with new I915_GETPARAM ioctl entries for
subslice total and EU total. Add
This helps speed up driver init time, and puts off the eDP stuff until
we actually need it.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/intel_dp.c | 103 ++-
drivers/gpu/drm/i915/intel_drv.h | 3 ++
2 files changed, 73
On Wed, Mar 18, 2015 at 04:15:07PM -0300, Paulo Zanoni wrote:
From: Paulo Zanoni paulo.r.zan...@intel.com
Otherwise we'll get a WARN from drm_wait_one_vblank() saying that
vblanks are not available (since they were already disabled in
crtc_disable()).
This is certainly a regresison, but
Determining whether we'll need to wait for vblanks is something we
should determine during the atomic 'check' phase, not the 'commit'
phase. Note that we only set these bits in the branch of 'check' where
intel_crtc-active is true so that we don't try to wait on a disabled
CRTC.
The whole 'wait
The existing ABI says that scanouts are pinned into the mappable region
so that legacy clients (e.g. old Xorg or plymouthd) can write directly
into the scanout through a GTT mapping. However if the surface does not
fit into the mappable region, we are better off just trying to fit it
anywhere and
On Tue, 2015-03-17 at 18:11 +, Konduru, Chandra wrote:
-Original Message-
From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel
Vetter
Sent: Tuesday, March 17, 2015 7:17 AM
To: Konduru, Chandra
Cc: intel-gfx@lists.freedesktop.org; Conselvan De Oliveira,
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