Re: [Intel-gfx] [PATCH] drm/i915: don't forget to set intel_crtc->dspaddr_offset on SKL+

On Fri, Aug 19, 2016 at 07:03:23PM -0300, Paulo Zanoni wrote: > We never remembered to set it (so it was zero), but this was not a > problem in the past due to the way handled the hardware registers. > Unfortunately we changed how we set the hardware and forgot to set > intel_crtc->dspaddr_offset.

[Intel-gfx] [PATCH 3/6] drm/i915: keep declarations in i915_drv.h

Fix sparse warnings: drivers/gpu/drm/i915/i915_drv.c:1179:5: warning: symbol 'i915_driver_load' was not declared. Should it be static? drivers/gpu/drm/i915/i915_drv.c:1267:6: warning: symbol 'i915_driver_unload' was not declared. Should it be static? drivers/gpu/drm/i915/i915_drv.c:2444:25:

[Intel-gfx] [PATCH 4/6] drm/i915: use NULL for NULL pointers

Fix sparse warning: drivers/gpu/drm/i915/i915_cmd_parser.c:987:72: warning: Using plain integer as NULL pointer Fixes: 52a42cec4b70 ("drm/i915/cmdparser: Accelerate copies from WC memory") Cc: Chris Wilson Signed-off-by: Jani Nikula ---

[Intel-gfx] ✗ Fi.CI.BAT: warning for series starting with [1/6] drm/i915: make intel_dp_compute_bpp static

== Series Details == Series: series starting with [1/6] drm/i915: make intel_dp_compute_bpp static URL : https://patchwork.freedesktop.org/series/12503/ State : warning == Summary == Series 12503v1 Series without cover letter

[Intel-gfx] [drm-intel:for-linux-next 12/12] drivers/gpu/drm/drm_dp_helper.c:551:2: error: implicit declaration of function 'seq_printf'

tree: git://anongit.freedesktop.org/drm-intel for-linux-next head: 80209e5f2c42c491ec5f4a63705b4377b407587c commit: 80209e5f2c42c491ec5f4a63705b4377b407587c [12/12] drm: Add DP branch device info on debugfs config: ia64-defconfig (attached as .config) compiler: ia64-linux-gcc (GCC) 4.9.0

Re: [Intel-gfx] [PATCH 5/9] drm/i915/gen9: minimum scanlines for Y tile is not always 4

Op 14-09-16 om 02:38 schreef Paulo Zanoni: > During watermarks calculations, this value is used in 3 different > places. Only one of them was not using a hardcoded 4. Move the code up > so everybody can benefit from the actual value. > > This should only help on situations with Y tiling + 90/270

[Intel-gfx] [PATCH 5/6] drm/i915: workaround sparse warning on variable length arrays

Fix sparse warning: drivers/gpu/drm/i915/intel_device_info.c:195:31: warning: Variable length array is used. In truth the array does have constant length, but sparse is too dumb to realize. This is a bit ugly, but silence the warning no matter what. Fixes: 91bedd34abf0 ("drm/i915/bdw: Check for

[Intel-gfx] [PATCH 2/6] drm/i915: do not use 'false' as a NULL pointer

Fixes sparse warning: drivers/gpu/drm/i915/intel_dpll_mgr.c:1712:24: warning: Using plain integer as NULL pointer Fixes: a277ca7dc01d ("drm/i915: Split bxt_ddi_pll_select()") Cc: Manasi Navare Cc: Ander Conselvan de Oliveira Cc:

[Intel-gfx] [PATCH 1/6] drm/i915: make intel_dp_compute_bpp static

Fix sparse warning: drivers/gpu/drm/i915/intel_dp.c:1527:5: warning: symbol 'intel_dp_compute_bpp' was not declared. Should it be static? Fixes: f9bb705e65f6 ("drm/i915: Update bits per component for display info") Cc: Mika Kahola Cc: Jim Bride

[Intel-gfx] [PATCH 6/6] drm/i915: silence io mapping/unmapping sparse warnings on different address spaces

drivers/gpu/drm/i915/i915_gem_execbuffer.c:432:52: warning: incorrect type in argument 1 (different address spaces) drivers/gpu/drm/i915/i915_gem_execbuffer.c:432:52:expected void [noderef] *vaddr drivers/gpu/drm/i915/i915_gem_execbuffer.c:432:52:got void *

Re: [Intel-gfx] [PATCH v2 2/2] drm/i915: Try to print INSTDONE bits for all slice/subslice

On Thu, 2016-09-15 at 17:30 +0300, Mika Kuoppala wrote: > Imre Deak writes: > > > From: Ben Widawsky > > > > v2: (Imre) > > - Access only subslices that are known to exist. > > - Reset explictly the MCR selector to slice/sub-slice ID 0 after

Re: [Intel-gfx] [PATCH 05/18] drm/i915: Move GEM activity tracking into a common struct reservation_object

On Thu, 15 Sep 2016, Dave Gordon wrote: > On 14/09/16 18:35, Chris Wilson wrote: >> On Wed, Sep 14, 2016 at 12:44:04PM +0300, Joonas Lahtinen wrote: >>> On ke, 2016-09-14 at 07:52 +0100, Chris Wilson wrote: -static inline bool

Re: [Intel-gfx] [PATCH v4 10/26] drm/i915/slpc: Allocate/Release/Initialize SLPC shared data

On 9/9/2016 10:38 PM, Chris Wilson wrote: On Fri, Sep 09, 2016 at 06:21:29PM +0530, Sagar Arun Kamble wrote: From: Tom O'Rourke SLPC shared data is used to pass information to/from SLPC in GuC firmware. For Skylake, platform sku type and slice count are identified

Re: [Intel-gfx] [PATCH v4 09/26] drm/i915/slpc: If using SLPC, do not set frequency

On 9/9/2016 10:51 PM, Chris Wilson wrote: On Fri, Sep 09, 2016 at 06:21:28PM +0530, Sagar Arun Kamble wrote: From: Tom O'Rourke When frequency requests are made by SLPC, host driver should not attempt to make frequency requests due to potential conflicts. Host-based

Re: [Intel-gfx] [PATCH v4 07/26] drm/i915/slpc: Use intel_slpc_* functions if supported

Thanks for the review. On 9/9/2016 10:50 PM, Chris Wilson wrote: On Fri, Sep 09, 2016 at 06:21:26PM +0530, Sagar Arun Kamble wrote: @@ -6720,31 +6743,38 @@ void intel_enable_gt_powersave(struct drm_i915_private *dev_priv) + if (intel_slpc_enabled()) { + } else { -

Re: [Intel-gfx] [PATCH v2] drm/i915: Queue page flip work via a low latency, unbound workqueue

On Thu, 2016-09-15 at 10:44 +0200, Maarten Lankhorst wrote: > Op 14-09-16 om 19:07 schreef Imre Deak: > > While user space has control over the scheduling priority of its > > page > > flipping thread, the corresponding work the driver schedules for > > MMIO > > flips always runs from the generic

Re: [Intel-gfx] drm/i915: Ignore OpRegion panel type except on select machines

> Tested-by: Marco Krüger > Tested-by: Alexey Shumitsky > Tested-by: Sean Greenslade > Tested-by: Emil Andersen Lauridsen > Tested-by: Robin Müller > Tested-by: oceans...@gmail.com >

Re: [Intel-gfx] [PATCH 1/6] drm/i915: make intel_dp_compute_bpp static

On Thu, Sep 15, 2016 at 04:28:52PM +0300, Jani Nikula wrote: > Fix sparse warning: > > drivers/gpu/drm/i915/intel_dp.c:1527:5: warning: symbol > 'intel_dp_compute_bpp' was not declared. Should it be static? > > Fixes: f9bb705e65f6 ("drm/i915: Update bits per component for display info") > Cc:

[Intel-gfx] [drm-intel:for-linux-next 6/12] htmldocs: drivers/gpu/drm/drm_dp_helper.c:523: warning: No description found for parameter 'id[6]'

tree: git://anongit.freedesktop.org/drm-intel for-linux-next head: 80209e5f2c42c491ec5f4a63705b4377b407587c commit: 266d783baaf5f34a5bea3b56489f091451a89767 [6/12] drm: Read DP branch device id reproduce: make htmldocs All warnings (new ones prefixed by >>):

Re: [Intel-gfx] [PATCH 4/6] drm/i915: use NULL for NULL pointers

Reviewed-by: Dhinakaran Pandiyan On Thu, 2016-09-15 at 16:28 +0300, Jani Nikula wrote: > Fix sparse warning: > > drivers/gpu/drm/i915/i915_cmd_parser.c:987:72: warning: Using plain > integer as NULL pointer > > Fixes: 52a42cec4b70 ("drm/i915/cmdparser: Accelerate

Re: [Intel-gfx] [PATCH v2 2/2] drm/i915: Try to print INSTDONE bits for all slice/subslice

Imre Deak writes: > From: Ben Widawsky > > v2: (Imre) > - Access only subslices that are known to exist. > - Reset explictly the MCR selector to slice/sub-slice ID 0 after the > readout. > - Use the subslice INSTDONE bits for the

Re: [Intel-gfx] 4.8-rc1: it is now common that machine needs re-run of xrandr after resume

Am Mittwoch, 14. September 2016, 14:14:35 CEST schrieb Jani Nikula: > On Wed, 14 Sep 2016, Jani Nikula wrote: > > On Wed, 14 Sep 2016, Pavel Machek wrote: > >> For the "sometimes need xrandr after resume": I don't think I can > >> bisect that. It only

Re: [Intel-gfx] [PATCH v6 0/5] Prep. for DP audio MST support

For the new patch, and any of the other patches in this series I haven't reviewed yet, looks good to me: Reviewed-by: Lyude On Wed, 2016-09-14 at 17:17 -0700, Dhinakaran Pandiyan wrote: > This series lays the groundwork for more DP MST audio work that will > follow. > > v2: >

Re: [Intel-gfx] [PATCH 2/6] drm/i915: do not use 'false' as a NULL pointer

Reviewed-by: Dhinakaran Pandiyan On Thu, 2016-09-15 at 16:28 +0300, Jani Nikula wrote: > Fixes sparse warning: > > drivers/gpu/drm/i915/intel_dpll_mgr.c:1712:24: warning: Using plain > integer as NULL pointer > > Fixes: a277ca7dc01d ("drm/i915: Split

Re: [Intel-gfx] [PATCH v3 5/5] drm/i915/dp/mst: Add support for upfront link training for DP MST

On Tue, 2016-09-13 at 18:08 -0700, Manasi Navare wrote: > From: Jim Bride > > Add upfront link training to intel_dp_mst_mode_valid() so that we know > topology constraints before we validate the legality of modes to be > checked. > The patch seems to do a lot more

Re: [Intel-gfx] [PATCH v2 3/5] drm/i915: Change the placement of some static functions in intel_dp.c

On Thu, Sep 15, 2016 at 10:41:23AM +0300, Mika Kahola wrote: > On Tue, 2016-09-13 at 18:08 -0700, Manasi Navare wrote: > > These static helper functions are required to be used within upfront > > link training related functions so they need to be placed at the top > > of the file. It also changes

Re: [Intel-gfx] [PATCH v3 5/5] drm/i915/dp/mst: Add support for upfront link training for DP MST

On Thu, Sep 15, 2016 at 10:48:17AM -0700, Pandiyan, Dhinakaran wrote: > On Tue, 2016-09-13 at 18:08 -0700, Manasi Navare wrote: > > From: Jim Bride > > > > Add upfront link training to intel_dp_mst_mode_valid() so that we know > > topology constraints before we

Re: [Intel-gfx] [PATCH i-g-t v4 01/13] lib/sw_sync: Add helper functions for managing synchronization primitives

On 2016-09-15 02:35 PM, Robert Foss wrote: On 2016-09-15 02:46 AM, Chris Wilson wrote: On Wed, Sep 14, 2016 at 11:04:30AM -0400, robert.f...@collabora.com wrote: +void sw_sync_timeline_inc(int fd, uint32_t count) +{ +uint32_t arg = count; + +if (fd == 0) +return; But fd =

[Intel-gfx] [PATCH i-g-t v5 12/13] tests/sw_sync: Add subtest test_sync_multi_timeline_wait

From: Robert Foss This subtest verifies that waiting, timing out on a wait and that counting fences in various states works. Signed-off-by: Robert Foss Reviewed-by: Eric Engestrom --- tests/sw_sync.c | 66

[Intel-gfx] [PATCH i-g-t v5 07/13] tests/sw_sync: Add subtest test_sync_merge

From: Robert Foss Add subtest test_sync_merge that tests merging fences and the validity of the resulting merged fence. Signed-off-by: Robert Foss Reviewed-by: Eric Engestrom --- tests/sw_sync.c | 67

[Intel-gfx] [PATCH i-g-t v5 13/13] tests/sw_sync: Add subtest test_sync_multi_producer_single_consumer

From: Robert Foss This subtest runs a single consumer thread and multiple producer thread that are synchronized using multiple timelines. Signed-off-by: Robert Foss Reviewed-by: Eric Engestrom --- tests/sw_sync.c | 139

[Intel-gfx] [PATCH i-g-t v5 09/13] tests/sw_sync: Add subtest test_sync_multi_consumer

From: Robert Foss This subtest verifies the access ordering of multiple consumer threads. Signed-off-by: Robert Foss Reviewed-by: Eric Engestrom --- tests/sw_sync.c | 103

[Intel-gfx] [PATCH i-g-t v5 11/13] tests/sw_sync: Add subtest test_sync_random_merge

From: Robert Foss This subtest verifies that creating many timelines and merging random fences from each timeline with eachother results in merged fences that are fully functional. Signed-off-by: Robert Foss Reviewed-by: Eric Engestrom

[Intel-gfx] [PATCH i-g-t v5 08/13] tests/sw_sync: Add subtest test_sync_merge_same

From: Robert Foss This subtest verifies merging a fence with itself does not fail. Signed-off-by: Robert Foss Reviewed-by: Eric Engestrom --- tests/sw_sync.c | 37 - 1 file changed,

[Intel-gfx] [PATCH i-g-t v5 02/13] tests/sw_sync: Add sw_sync test

From: Robert Foss Add initial tests for sw_sync. Signed-off-by: Robert Foss Signed-off-by: Gustavo Padovan Reviewed-by: Eric Engestrom --- tests/Makefile.sources | 1 + tests/sw_sync.c

Re: [Intel-gfx] [PATCH i-g-t v4 01/13] lib/sw_sync: Add helper functions for managing synchronization primitives

On 2016-09-15 02:46 AM, Chris Wilson wrote: On Wed, Sep 14, 2016 at 11:04:30AM -0400, robert.f...@collabora.com wrote: +void sw_sync_timeline_inc(int fd, uint32_t count) +{ + uint32_t arg = count; + + if (fd == 0) + return; But fd = 0 is a valid fd, and might be a

[Intel-gfx] [PATCH i-g-t v5 00/13] Implement sw_sync test

From: Robert Foss This series implements the sw_sync test and the lib/sw_sync helper functions for said test. Gustavo Padovans sw_sync series was just de-staged in gregkh-staging/staging-next [1], and this test is targeted at verifying the functionality implemented

[Intel-gfx] [PATCH i-g-t v5 10/13] tests/sw_sync: Add subtest test_sync_multi_consumer_producer

From: Robert Foss This test verifies that stressing the kernel by creating multiple consumer/producer threads that wait on a single timeline to be incremented by another conumer/producer thread does not fail. And that the order amongst the threads is maintained.

[Intel-gfx] [PATCH i-g-t v5 05/13] tests/sw_sync: Add subtest test_alloc_merge_fence

From: Robert Foss This subtest verifies that merging two fences works in the simples possible case. Signed-off-by: Robert Foss Reviewed-by: Eric Engestrom --- tests/sw_sync.c | 23 +++ 1 file

[Intel-gfx] [PATCH i-g-t v5 01/13] lib/sw_sync: Add helper functions for managing synchronization primitives

From: Robert Foss Base functions to help testing the Sync File Framework (explicit fencing mechanism ported from Android). These functions allow you to create, use and destroy timelines and fences. Signed-off-by: Robert Foss Signed-off-by:

[Intel-gfx] [PATCH i-g-t v5 04/13] tests/sw_sync: Add subtest test_alloc_fence_invalid_timeline

From: Robert Foss This subtests tests that creating fences on negative timelines fail. Signed-off-by: Robert Foss Reviewed-by: Eric Engestrom --- tests/sw_sync.c | 7 +++ 1 file changed, 7 insertions(+) diff --git

[Intel-gfx] [PATCH i-g-t v5 06/13] tests/sw_sync: Add subtest test_sync_wait

From: Robert Foss This subtest verifies that waiting on fences works properly. Signed-off-by: Robert Foss Reviewed-by: Eric Engestrom --- tests/sw_sync.c | 38 ++ 1 file changed, 38

[Intel-gfx] [PATCH i-g-t v5 03/13] tests/sw_sync: Add subtest test_alloc_fence

From: Robert Foss Add subtest alloc_fence that verifies that it's possible to allocate a fence on a timeline. Signed-off-by: Robert Foss Reviewed-by: Eric Engestrom --- tests/sw_sync.c | 16 1 file

Re: [Intel-gfx] [PATCH i-g-t v4 01/13] lib/sw_sync: Add helper functions for managing synchronization primitives

2016-09-15 Robert Foss : > > > On 2016-09-15 02:35 PM, Robert Foss wrote: > > > > > > On 2016-09-15 02:46 AM, Chris Wilson wrote: > > > On Wed, Sep 14, 2016 at 11:04:30AM -0400, robert.f...@collabora.com > > > wrote: > > > > +void sw_sync_timeline_inc(int fd,

Re: [Intel-gfx] [PATCH v5 1/5] drm/i915: Fallback to lower link rate and lane count during link training

On Wed, Sep 14, 2016 at 11:15:13AM +0300, Mika Kahola wrote: > On Tue, 2016-09-13 at 18:08 -0700, Manasi Navare wrote: > > According to the DisplayPort Spec, in case of Clock Recovery failure > > the link training sequence should fall back to the lower link rate > > followed by lower lane count

[Intel-gfx] [PATCH v3 5/5] drm/i915: squash lines for simple wrapper functions

Remove unneeded variables and assignments. Signed-off-by: Masahiro Yamada --- Changes in v3: - Keep the wrapper function. Cleanup of variables and assignments only. - Fix intel_engine_init_common() as well. drivers/gpu/drm/i915/i915_drv.c| 8

[Intel-gfx] [PATCH v17 5/6] drm/i915/dp: Enable Upfront link training on DDI platforms

To support USB type C alternate DP mode, the display driver needs to know the number of lanes required by the DP panel as well as number of lanes that can be supported by the type-C cable. Sometimes, the type-C cable may limit the bandwidth even if Panel can support more lanes. To address these

[Intel-gfx] [PATCH v3 2/6] drm/i915: Remove the link rate and lane count loop in compute config

While configuring the pipe during modeset, it should use max clock and max lane count and reduce the bpp until the requested mode rate is less than or equal to available link BW. This is required to pass DP Compliance. v3: * Add Debug print if requested mode cannot be supported during modeset

Re: [Intel-gfx] [PATCH i-g-t v5 07/13] tests/sw_sync: Add subtest test_sync_merge

On 2016-09-15 04:41 PM, Chris Wilson wrote: On Thu, Sep 15, 2016 at 02:40:12PM -0400, robert.f...@collabora.com wrote: From: Robert Foss Add subtest test_sync_merge that tests merging fences and the validity of the resulting merged fence. Signed-off-by: Robert

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v6,1/6] drm/i915: Fallback to lower link rate and lane count during link training

== Series Details == Series: series starting with [v6,1/6] drm/i915: Fallback to lower link rate and lane count during link training URL : https://patchwork.freedesktop.org/series/12534/ State : success == Summary == Series 12534v1 Series without cover letter

Re: [Intel-gfx] [PATCH i-g-t v5 06/13] tests/sw_sync: Add subtest test_sync_wait

On 2016-09-15 04:32 PM, Chris Wilson wrote: On Thu, Sep 15, 2016 at 02:40:11PM -0400, robert.f...@collabora.com wrote: From: Robert Foss This subtest verifies that waiting on fences works properly. Signed-off-by: Robert Foss

[Intel-gfx] linux-next: manual merge of the drm-intel tree with Linus' tree

Hi all, Today's linux-next merge of the drm-intel tree got a conflict in: drivers/gpu/drm/i915/intel_pm.c between commit: f403372658fc ("drm/i915/skl: Add support for the SAGV, fix underrun hangs") (which is also in the drm-intel tree) from Linus' tree and commit: 6f3fff602e81

[Intel-gfx] [PATCH v6 1/6] drm/i915: Fallback to lower link rate and lane count during link training

According to the DisplayPort Spec, in case of Clock Recovery failure the link training sequence should fall back to the lower link rate followed by lower lane count until CR succeeds. On CR success, the sequence proceeds with Channel EQ. In case of Channel EQ failures, it should fallback to lower

[Intel-gfx] [PATCH v3 3/6] drm/i915: Change the placement of some static functions in intel_dp.c

These static helper functions are required to be used within upfront link training related functions so they need to be placed at the top of the file. It also changes macro dev to dev_priv. v3: * Add cleanup to other patch (Mika Kahola) v2: * Dont move around functions declared in intel_drv.h

[Intel-gfx] [PATCH v3 6/6] drm/i915/dp/mst: Add support for upfront link training for DP MST

From: Jim Bride Add upfront link training to intel_dp_mst_mode_valid() so that we know topology constraints before we validate the legality of modes to be checked. These upfront values get used in mst_compute_config instead of using max link rate and lane count values.

[Intel-gfx] [PATCH 4/6] drm/i915: Code cleanup to use dev_priv and INTEL_GEN

Replace dev with dev_priv and INTEL_INFO with INTEL_GEN Signed-off-by: Manasi Navare --- drivers/gpu/drm/i915/intel_dp.c | 14 +++--- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c

[Intel-gfx] [PATCH 0/6] Remaining patches for upfront link training on DDI platforms

This patch series includes some of the remaining patches to enable upfront link training on DDI platforms for DP SST and MST. They are based on some of the patches submitted earlier by Ander and Durgadoss. The upfront link training had to be factored out of long pulse hanlder because of deadlock

Re: [Intel-gfx] [PATCH i-g-t v4 01/13] lib/sw_sync: Add helper functions for managing synchronization primitives

On Wed, Sep 14, 2016 at 11:04:30AM -0400, robert.f...@collabora.com wrote: > +void sw_sync_timeline_inc(int fd, uint32_t count) > +{ > + uint32_t arg = count; > + > + if (fd == 0) > + return; But fd = 0 is a valid fd, and might be a timeline somewhere. Did you mean count == 0

[Intel-gfx] ✗ Fi.CI.BAT: failure for Enable i915 perf stream for Haswell OA unit (rev4)

== Series Details == Series: Enable i915 perf stream for Haswell OA unit (rev4) URL : https://patchwork.freedesktop.org/series/11295/ State : failure == Summary == Series 11295v4 Enable i915 perf stream for Haswell OA unit

[Intel-gfx] ✗ Fi.CI.BAT: warning for drm/i915: introduce & use i915_gem_object_{set, clear, is}_dirty() (rev2)

== Series Details == Series: drm/i915: introduce & use i915_gem_object_{set, clear, is}_dirty() (rev2) URL : https://patchwork.freedesktop.org/series/12262/ State : warning == Summary == Series 12262v2 drm/i915: introduce & use i915_gem_object_{set, clear, is}_dirty()

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Standardize port type for DVO encoders (rev2)

== Series Details == Series: drm/i915: Standardize port type for DVO encoders (rev2) URL : https://patchwork.freedesktop.org/series/12418/ State : success == Summary == Series 12418v2 drm/i915: Standardize port type for DVO encoders

[Intel-gfx] ✗ Fi.CI.BAT: warning for drm/i915: Queue page flip work with high priority (rev2)

== Series Details == Series: drm/i915: Queue page flip work with high priority (rev2) URL : https://patchwork.freedesktop.org/series/12336/ State : warning == Summary == Series 12336v2 drm/i915: Queue page flip work with high priority

Re: [Intel-gfx] [PATCH] drm/i915: Add ddb size field to device info structure

On Wed, 14 Sep 2016, Deepak M wrote: > Adding the ddb size into the devide info will avoid > platform checks while computing wm. > > v2: Added comment and WARN_ON if ddb size is zero.(Jani) > > Suggested-by: Ander Conselvan de Oliveira >

Re: [Intel-gfx] [PATCH] DRM: i915: Fix random GPU hang, Bug 156851

You'll still need that commit message. See 'git log' on our driver for examples of the level of commit messages we expect. You'll also see how to reference bugs using the Bugzilla: tag. And please do file the bug where I asked, not somewhere else. BR, Jani. On Thu, 15 Sep 2016, Cheng Cao

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Unlock PPS registers after GPU reset

== Series Details == Series: drm/i915: Unlock PPS registers after GPU reset URL : https://patchwork.freedesktop.org/series/12446/ State : success == Summary == Series 12446v1 drm/i915: Unlock PPS registers after GPU reset

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Only expand COND once in wait_for() (rev2)

== Series Details == Series: drm/i915: Only expand COND once in wait_for() (rev2) URL : https://patchwork.freedesktop.org/series/12403/ State : success == Summary == Series 12403v2 drm/i915: Only expand COND once in wait_for()

[Intel-gfx] ✗ Fi.CI.BAT: failure for Enable i915 perf stream for Haswell OA unit (rev3)

== Series Details == Series: Enable i915 perf stream for Haswell OA unit (rev3) URL : https://patchwork.freedesktop.org/series/11295/ State : failure == Summary == Series 11295v3 Enable i915 perf stream for Haswell OA unit

Re: [Intel-gfx] [PATCH 3/8] drm/i915/kbl: KBL also needs to run the SAGV code

On Wed, 14 Sep 2016, "Zanoni, Paulo R" wrote: > Em Qua, 2016-09-14 às 12:59 +0300, Jani Nikula escreveu: >> On Tue, 13 Sep 2016, "Zanoni, Paulo R" >> wrote: >> > >> > I got confirmation from the Hardware guys that KBL does need to run >> > the

Re: [Intel-gfx] [PATCH] DRM: i915: Fix gen8 graphics on Broadwell-U. These patches stop the random gpu hang on my XPS-13-9343, kernel version 4.8-rc5.

On Thu, Sep 15, 2016 at 11:12:08AM +0800, bobcao3 wrote: > Signed-off-by: bobcao3 > --- > drivers/gpu/drm/i915/i915_gem_gtt.c | 6 > drivers/gpu/drm/i915/i915_gem_stolen.c | 61 > - > drivers/gpu/drm/i915/i915_reg.h | 6

[Intel-gfx] ✗ Fi.CI.BAT: failure for Prep. for DP audio MST support (rev10)

== Series Details == Series: Prep. for DP audio MST support (rev10) URL : https://patchwork.freedesktop.org/series/11129/ State : failure == Summary == Series 11129v10 Prep. for DP audio MST support https://patchwork.freedesktop.org/api/1.0/series/11129/revisions/10/mbox/ Test

Re: [Intel-gfx] [PATCH v2 3/5] drm/i915: Change the placement of some static functions in intel_dp.c

On Tue, 2016-09-13 at 18:08 -0700, Manasi Navare wrote: > These static helper functions are required to be used within upfront > link training related functions so they need to be placed at the top > of the file. It also changes macro dev to dev_priv. > We could split this patch into two parts.

Re: [Intel-gfx] [PATCH] DRM: i915: Fix gen8 graphics on Broadwell-U. These patches stop the random gpu hang on my XPS-13-9343, kernel version 4.8-rc5.

On Thu, 15 Sep 2016, bobcao3 wrote: > DRM: i915: Fix gen8 graphics on Broadwell-U. These patches stop the > random gpu hang on my XPS-13-9343, kernel version 4.8-rc5. Please do everyone a favor and file a bug on the hangs over at [1], describing the issue and attaching the

Re: [Intel-gfx] [PATCH i-g-t v5 02/13] tests/sw_sync: Add sw_sync test

On 2016-09-15 04:22 PM, Chris Wilson wrote: On Thu, Sep 15, 2016 at 02:40:07PM -0400, robert.f...@collabora.com wrote: From: Robert Foss Add initial tests for sw_sync. Signed-off-by: Robert Foss Signed-off-by: Gustavo Padovan

Re: [Intel-gfx] [PATCH i-g-t v5 06/13] tests/sw_sync: Add subtest test_sync_wait

On Thu, Sep 15, 2016 at 02:40:11PM -0400, robert.f...@collabora.com wrote: > From: Robert Foss > > This subtest verifies that waiting on fences works properly. > > Signed-off-by: Robert Foss > Reviewed-by: Eric Engestrom

Re: [Intel-gfx] [PATCH i-g-t v5 01/13] lib/sw_sync: Add helper functions for managing synchronization primitives

On Thu, Sep 15, 2016 at 02:40:06PM -0400, robert.f...@collabora.com wrote: > From: Robert Foss > > Base functions to help testing the Sync File Framework (explicit fencing > mechanism ported from Android). > These functions allow you to create, use and destroy

Re: [Intel-gfx] [PATCH i-g-t v5 06/13] tests/sw_sync: Add subtest test_sync_wait

On Thu, Sep 15, 2016 at 02:40:11PM -0400, robert.f...@collabora.com wrote: > From: Robert Foss > > This subtest verifies that waiting on fences works properly. > > Signed-off-by: Robert Foss > Reviewed-by: Eric Engestrom

Re: [Intel-gfx] [PATCH i-g-t v5 07/13] tests/sw_sync: Add subtest test_sync_merge

On Thu, Sep 15, 2016 at 02:40:12PM -0400, robert.f...@collabora.com wrote: > From: Robert Foss > > Add subtest test_sync_merge that tests merging fences and the validity of the > resulting merged fence. > > Signed-off-by: Robert Foss >

Re: [Intel-gfx] [PATCH i-g-t v5 02/13] tests/sw_sync: Add sw_sync test

On Thu, Sep 15, 2016 at 02:40:07PM -0400, robert.f...@collabora.com wrote: > From: Robert Foss > > Add initial tests for sw_sync. > > Signed-off-by: Robert Foss > Signed-off-by: Gustavo Padovan >

Re: [Intel-gfx] [PATCH 3/3] drm/i915/guc: general tidying up (submission)

On 14/09/2016 18:00, Dave Gordon wrote: On 14/09/16 16:22, Tvrtko Ursulin wrote: On 12/09/2016 21:19, Dave Gordon wrote: Renaming to more consistent scheme, and updating comments, mostly about i915_guc_wq_reserve(), aka i915_guc_wq_check_space(). Signed-off-by: Dave Gordon

Re: [Intel-gfx] [PATCH 3/3] drm/i915/guc: general tidying up (submission)

On Thu, Sep 15, 2016 at 09:57:18AM +0100, Tvrtko Ursulin wrote: > On 14/09/2016 18:00, Dave Gordon wrote: > >On 14/09/16 16:22, Tvrtko Ursulin wrote: > >> > >>On 12/09/2016 21:19, Dave Gordon wrote: > >>>Renaming to more consistent scheme, and updating comments, mostly > >>>about

Re: [Intel-gfx] [PATCH v4 25/26] drm/i915: Add sysfs interface to know the HW requested frequency

On Thu, Sep 15, 2016 at 04:14:22PM +0530, Kamble, Sagar A wrote: > > > On 9/9/2016 10:13 PM, Chris Wilson wrote: > >On Fri, Sep 09, 2016 at 06:21:44PM +0530, Sagar Arun Kamble wrote: > >>With SLPC, user can read this value to know SLPC requested frequency. > >Not SLPC specific, even elsewhere

Re: [Intel-gfx] [PATCH 9/9] drm/i915/gen9: fail the modeset instead of WARNing on unsuported config

On Tue, Sep 13, 2016 at 09:38:22PM -0300, Paulo Zanoni wrote: > Now that this code is part of the compute stage we can return -EINVAL > to prevent the modeset instead of giving a WARN and trying anyway. > > Reported-by: Lyude > Signed-off-by: Paulo Zanoni

Re: [Intel-gfx] [PATCH 11/18] drm/i915: Record space required for request emission

On 14/09/2016 18:33, Chris Wilson wrote: On Wed, Sep 14, 2016 at 02:30:20PM +0100, Tvrtko Ursulin wrote: On 14/09/2016 07:52, Chris Wilson wrote: In the next patch, we will use deferred request emission. That requires reserving sufficient space in the ringbuffer to emit the request, which

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Add ddb size field to device info structure (rev3)

== Series Details == Series: drm/i915: Add ddb size field to device info structure (rev3) URL : https://patchwork.freedesktop.org/series/12427/ State : success == Summary == Series 12427v3 drm/i915: Add ddb size field to device info structure

Re: [Intel-gfx] [PATCH v2 5/5] drm/i915: use i915_gem_open() directly instead of i915_driver_open()

2016-09-15 18:46 GMT+09:00 Jani Nikula : > On Wed, 14 Sep 2016, Masahiro Yamada wrote: >> i915_driver_open() is equivalent to i915_gem_open(). Replace the >> i915_driver_open with the direct use of i915_gem_open(). > > Sorry I know I

Re: [Intel-gfx] [PATCH v4 17/26] drm/i915/slpc: Add enable/disable debugfs for slpc

On 9/9/2016 10:24 PM, Chris Wilson wrote: On Fri, Sep 09, 2016 at 06:21:36PM +0530, Sagar Arun Kamble wrote: +static ssize_t slpc_dcc_write(struct file *file, const char __user *ubuf, + size_t len, loff_t *offp) +{ + struct seq_file *m = file->private_data; +

Re: [Intel-gfx] [PATCH v4 18/26] drm/i915/slpc: Add i915_slpc_info to debugfs

On 9/9/2016 10:44 PM, Chris Wilson wrote: On Fri, Sep 09, 2016 at 06:21:37PM +0530, Sagar Arun Kamble wrote: + if (!intel_slpc_active(dev_priv)) + return -ENODEV; Can we really say slpc is active without an slpc.vma? No. Will remove this check. -Chris

Re: [Intel-gfx] [PATCH v4 16/26] drm/i915/slpc: Add slpc support for max/min freq

On 9/9/2016 10:19 PM, Chris Wilson wrote: On Fri, Sep 09, 2016 at 06:21:35PM +0530, Sagar Arun Kamble wrote: From: Tom O'Rourke Update sysfs and debugfs functions to set SLPC parameters when setting max/min frequency. v1: Update for SLPC 2015.2.4 (params for both

Re: [Intel-gfx] [PATCH v4 11/26] drm/i915/slpc: Update sysfs/debugfs interfaces for frequency parameters

On 9/9/2016 10:43 PM, Chris Wilson wrote: On Fri, Sep 09, 2016 at 06:21:30PM +0530, Sagar Arun Kamble wrote: From: Tom O'Rourke When SLPC is controlling requested frequency, the rps.cur_freq value is not used to make the frequency request. Requested frequency from

Re: [Intel-gfx] [PATCH v4 11/26] drm/i915/slpc: Update sysfs/debugfs interfaces for frequency parameters

On Thu, Sep 15, 2016 at 04:11:45PM +0530, Kamble, Sagar A wrote: > > > On 9/9/2016 10:43 PM, Chris Wilson wrote: > >On Fri, Sep 09, 2016 at 06:21:30PM +0530, Sagar Arun Kamble wrote: > >>From: Tom O'Rourke > >> > >>When SLPC is controlling requested frequency, the

Re: [Intel-gfx] [PATCH v2] drm/i915: Queue page flip work via a low latency, unbound workqueue

Op 14-09-16 om 19:07 schreef Imre Deak: > While user space has control over the scheduling priority of its page > flipping thread, the corresponding work the driver schedules for MMIO > flips always runs from the generic system workqueue which has some > scheduling overhead due it being CPU bound.

Re: [Intel-gfx] [PATCH] drm/i915: Unlock PPS registers after GPU reset

On Wed, Sep 14, 2016 at 01:04:13PM +0300, Imre Deak wrote: > Reapply the PPS register unlock workaround after GPU reset on platforms > where the reset clobbers the display HW state. This at least gets rid of > the related WARN during LVDS encoder enabling on PNV. > > Fixes: ed6143b8f75

Re: [Intel-gfx] [PATCH] drm/i915: Add ddb size field to device info structure

On Thu, 15 Sep 2016, Deepak M wrote: > Adding the ddb size into the devide info will avoid > platform checks while computing wm. > > v2: Added comment and WARN_ON if ddb size is zero.(Jani) > v3: Added WARN_ON at the right place.(Jani) > > Suggested-by: Ander Conselvan de

[Intel-gfx] [PULL] drm-intel-fixes

Hi Dave, more Intel fixes for v4.8. BR, Jani. The following changes since commit fc2780b66b15092ac68272644a522c1624c48547: drm/i915: Add GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE to SNB (2016-09-07 17:40:43 +0300) are available in the git repository at:

Re: [Intel-gfx] [PATCH v9 00/12] drm/i915: DP branch devices

On Fri, 09 Sep 2016, Mika Kahola wrote: > Prep work for DP branch device handling > > This series of patches reads DPCD register 0x80h for receiver > capabilities for DP branch devices. The branch device types are > converters for the following standards > > - DP to VGA >

Re: [Intel-gfx] [PATCH] DRM: i915: Fix random GPU hang, Bug 156851

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97814 On Thu, 15 Sep 2016, Cheng Cao wrote: > Signed-off-by: Cheng Cao > --- > drivers/gpu/drm/i915/i915_gem_gtt.c | 6 > drivers/gpu/drm/i915/i915_gem_stolen.c | 61 >

Re: [Intel-gfx] [PATCH] drm/i915: Only expand COND once in wait_for()

On Wed, Sep 14, 2016 at 03:53:32PM -0300, Paulo Zanoni wrote: > Em Qua, 2016-09-14 às 13:10 +0100, Dave Gordon escreveu: > > Commentary from Chris Wilson's original version: > > > > > > > > I was looking at some wait_for() timeouts on a slow system, with > > > lots of > > > debug enabled (KASAN,

Re: [Intel-gfx] [PATCH 0/9] SKL/KBL watermark fixes, v2

On Wed, 14 Sep 2016, "Zanoni, Paulo R" wrote: > Em Qua, 2016-09-14 às 12:34 +0300, Jani Nikula escreveu: >> On Wed, 14 Sep 2016, Paulo Zanoni wrote: >> > >> > Hi >> > >> > Here's the series with the reviews implemented. There's a new >> >

[Intel-gfx] [PATCH] drm/i915: Add ddb size field to device info structure

Adding the ddb size into the devide info will avoid platform checks while computing wm. v2: Added comment and WARN_ON if ddb size is zero.(Jani) v3: Added WARN_ON at the right place.(Jani) Suggested-by: Ander Conselvan de Oliveira Signed-off-by: Deepak M

Re: [Intel-gfx] [PATCH 05/18] drm/i915: Move GEM activity tracking into a common struct reservation_object

On 14/09/16 18:35, Chris Wilson wrote: On Wed, Sep 14, 2016 at 12:44:04PM +0300, Joonas Lahtinen wrote: On ke, 2016-09-14 at 07:52 +0100, Chris Wilson wrote: -static inline bool -i915_gem_object_has_active_engine(const struct drm_i915_gem_object *obj, - int

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