[Intel-gfx] [PATCH 19/21] drm/i915: prevent bogus intel_update_fbc notifications

This pollutes dmesg output even if we do not have FBC for the device, so move the DRM_DEBUG_KMS statement lower. v2: just kill the message as suggested by Daniel. Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/intel_pm.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/d

[Intel-gfx] [PATCH 21/21] drm/i915: enable RC6 workaround on Haswell

For Haswell, on some of the early hardware revisions, it is possible to run into issues when RC6 state is enabled and when pipes change state. v2: add comment saying that this is for early revisions only. Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/i915_reg.h | 5 + drivers/gpu/

[Intel-gfx] [PATCH 12/21] drm/i915: support Haswell-style force waking

On Haswell, there is a different register for reading force wake ACKs. v2: simplify forcewake dance and therefore the commit message as noticed by Daniel Vetter. Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/i915_drv.c | 10 -- drivers/gpu/drm/i915/i915_reg.h | 1 + 2 files ch

Re: [Intel-gfx] [PATCH 20/21] drm/i915: fix PIPE_WM_LINETIME definition

On Thu, Jun 28, 2012 at 03:55:48PM -0300, Eugeni Dodonov wrote: > From: Paulo Zanoni > > Looks like a copy/paste error. > > Signed-off-by: Paulo Zanoni > Signed-off-by: Eugeni Dodonov Queued for -next, thanks for the patch. -Daniel -- Daniel Vetter Mail: dan...@ffwll.ch Mobile: +41 (0)79 365

Re: [Intel-gfx] [PATCH 12/21] drm/i915: support Haswell-style force waking

On Thu, Jun 28, 2012 at 03:55:40PM -0300, Eugeni Dodonov wrote: > On Haswell, there is a different register for reading force wake ACKs, and > all the writes should go into the multi-threaded register, even for the > legacy force wake. > > Also, we have a theorical possibility for the force wake s

Re: [Intel-gfx] [PATCH 19/21] drm/i915: prevent bogus intel_update_fbc notifications

On Thu, Jun 28, 2012 at 03:55:47PM -0300, Eugeni Dodonov wrote: > This pollutes dmesg output even if we do not have FBC for the device, so > move the DRM_DEBUG_KMS statement lower. > > Signed-off-by: Eugeni Dodonov I suggest we just kill this right away ;-) -Daniel > --- > drivers/gpu/drm/i915/

Re: [Intel-gfx] [PATCH 21/21] drm/i915: enable RC6 workaround on Haswell

On Thu, Jun 28, 2012 at 03:55:49PM -0300, Eugeni Dodonov wrote: > For Haswell, on some of the early hardware revisions, it is possible to > run into issues when RC6 state is enabled and when pipes change state. > > Signed-off-by: Eugeni Dodonov Given that this is a w/a that only applies for earl

Re: [Intel-gfx] [PATCH 00/21] More Haswell patches

2012/6/28 Eugeni Dodonov :> > Also, for DP and eDP, Paulo Zanoni and Shobhit Kumar are already working on a > larger series of patches which should appear in the next few days as well.  So > while the patches in this series should work on most configurations, > considerable amount of improvements a

Re: [Intel-gfx] [PATCH] drm/i915: "Flush Me Harder" required on gen6+

On Thu, Jun 28, 2012 at 10:37:07AM +0100, Chris Wilson wrote: > On Thu, 28 Jun 2012 09:48:42 +0200, Daniel Vetter > wrote: > > The prep to remove the flushing list in > > > > commit cc889e0f6ce6a63c62db17d702ecfed86d58083f > > Author: Daniel Vetter > > Date: Wed Jun 13 20:45:19 2012 +0200 > >

[Intel-gfx] [PATCH 21/21] drm/i915: enable RC6 workaround on Haswell

For Haswell, on some of the early hardware revisions, it is possible to run into issues when RC6 state is enabled and when pipes change state. Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/i915_reg.h | 5 + drivers/gpu/drm/i915/intel_pm.c | 9 + 2 files changed, 14 insertion

[Intel-gfx] [PATCH 20/21] drm/i915: fix PIPE_WM_LINETIME definition

From: Paulo Zanoni Looks like a copy/paste error. Signed-off-by: Paulo Zanoni Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/i915_reg.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 1165d2e..

[Intel-gfx] [PATCH 19/21] drm/i915: prevent bogus intel_update_fbc notifications

This pollutes dmesg output even if we do not have FBC for the device, so move the DRM_DEBUG_KMS statement lower. Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/intel_pm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu

[Intel-gfx] [PATCH 18/21] drm/i915: introduce haswell_init_clock_gating

This is based on Ivy Bridge clock gating for now, but is subject to changes in the future. Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/intel_pm.c | 54 - 1 file changed, 53 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_pm

[Intel-gfx] [PATCH 17/21] drm/i915: Hook eDP initialization on DDI A

From: Shobhit Kumar Signed-off-by: Shobhit Kumar Signed-off-by: Sateesh Kavuri Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/intel_ddi.c | 3 +-- drivers/gpu/drm/i915/intel_dp.c | 1 + 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/

[Intel-gfx] [PATCH 16/21] drm/i915: Modesetting for eDP on HSw

From: Shobhit Kumar The MSA register and PIPE EDP register are differnet than that of DP. Also link training flow though similar for DP had been corrected to follow DP path Signed-off-by: Shobhit Kumar Signed-off-by: Sateesh Kavuri Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/i915_

[Intel-gfx] [PATCH 15/21] drm/i915: Timing initialization for eDP on HSW

From: Shobhit Kumar v2: simplify horizontal and vertical timings calculations Signed-off-by: Shobhit Kumar Signed-off-by: Sateesh Kavuri Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/intel_display.c | 66 +++- 1 file changed, 42 insertions(+), 24 dele

[Intel-gfx] [PATCH 14/21] drm/i915: Add EDP Registers for Haswell

From: Shobhit Kumar PIPE EDP registers and timing registers are different for EDP on HSW Signed-off-by: Shobhit Kumar Signed-off-by: Sateesh Kavuri Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/i915_reg.h | 31 +++ 1 file changed, 31 insertions(+) diff -

[Intel-gfx] [PATCH 13/21] drm/i915: add RPS configuration for Haswell

Split Haswell-specific GT algorithms into its own function. Note that Haswell only has RC6, so account for that as well. Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_pm.c | 160 ++-- 2 files changed, 15

[Intel-gfx] [PATCH 12/21] drm/i915: support Haswell-style force waking

On Haswell, there is a different register for reading force wake ACKs, and all the writes should go into the multi-threaded register, even for the legacy force wake. Also, we have a theorical possibility for the force wake sequence to awaken the GT, but return while it hasn't finished bringing up

[Intel-gfx] [PATCH 11/21] drm/i915: program FDI_RX TP and FDI delays

This is required for a stable FDI connection. Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/i915_reg.h | 3 +++ drivers/gpu/drm/i915/intel_ddi.c | 10 ++ 2 files changed, 13 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 5b0

[Intel-gfx] [PATCH 07/21] drm/i915: re-initialize DDI buffer translations after resume

This is necessary for the modesetting to work correctly after a suspend-resume cycle. Without this, the pipes and clocks got the correct configuration, but the underlying DDI buffers configuration was lost. Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/intel_display.c | 4 ++-- 1 file c

[Intel-gfx] [PATCH 10/21] drm/i915: introduce lpt_enable_pch and cpt_enable_pch

CPT/PPT and LPT have different functionality. So we introduce specific functions to handle each of them instead of using multiple if.. statements. Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/intel_display.c | 70 1 file changed, 63 insertions(+), 7

[Intel-gfx] [PATCH 09/21] drm/i915: account for only one transcoder on LPT

Same as with FDI RX, Lynx point only has one transcoder, which can be driven by any pipe. So consider that only pipeA will be used with CRT for now. Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/intel_display.c | 19 +++ 1 file changed, 15 insertions(+), 4 deletions(-)

[Intel-gfx] [PATCH 08/21] drm/i915: simplify FDI RX check for LPT

On LPT onwards, there is only one FDI receiver, but any pipe can drive it. For now, we consider that only pipeA can work in CRT mode, so if any other pipe attempts to enable FDI receiver it is considered invalid behavior. Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/intel_display.c | 3

[Intel-gfx] [PATCH 06/21] drm/i915: Hook DP init in ddi module

From: Shobhit Kumar TBD: As of now just initializes DP connectors. Later we need to detect the actual output connected on the port(HDMI or DP) using AUX channel detection and appropriately call the initialization routines v2: Init DP connector on DDIB and DDID, and HDMI on DDIC. Signed-off-by:

[Intel-gfx] [PATCH 05/21] drm/i915: Disable DDI Pipe Control on HSW while disabling pipe

From: Shobhit Kumar In Haswell while disabling a pipe, we need to disable the DDI control as well along with the PIPECONF. Otherwise we will hit assertions during crtc disable Signed-off-by: Shobhit Kumar Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/intel_display.c | 7 +++ 1 fi

[Intel-gfx] [PATCH 04/21] drm/i915: Haswell specific code for the DP Link Training

From: Shobhit Kumar In Haswell the DDIs have moved on to CPU. The AUX control is on LPT. Had to split the code in such a way so as to be able to do source training using DDI_BUF_CTL and DP_TP_CTL and sink side using AUX on LPT. Also added new routine to get the Volatge and pre-emphashis values.

[Intel-gfx] [PATCH 03/21] drm/i915: Add DP Helper functions for Haswell

From: Shobhit Kumar Need to program new helpers for mode set and dpms as most of the stuff is done using DDI port. The current commit uses SPLL clock for SCC enabled panel and LCPLL for Non-SSC. Also Haswell has LPT and DDIs are moved on CPU side and has DP_BUF_CTL and DP_TP_CTL so added a new T

[Intel-gfx] [PATCH 02/21] drm/i915: Add support for DDI control DP outputs

From: Shobhit Kumar These are driven by DDIs on Haswell architecture, so we need to keep track of which DDI is being used on each output. Signed-off-by: Shobhit Kumar Reviewed-by: Eugeni Dodonov Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/intel_dp.c | 10 +++--- drivers/gpu/d

[Intel-gfx] [PATCH 01/21] drm/i915: Move DP structs to shared location

From: Shobhit Kumar Move the DP structure to shared location so that it can be used from within ddi module Signed-off-by: Shobhit Kumar Reviewed-by: Eugeni Dodonov Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/intel_dp.c | 34 -- drivers/gpu/drm/i915

[Intel-gfx] [PATCH 00/21] More Haswell patches

Hi, Those are the patches which I had in my queue for past few weeks, which I am sending now for your bikeshedding pleasure :). As major changes, this patch series adds support for DP, eDP and RC6 features for Haswell. Some of the DP-related patches were already posted here, but I am resending th

Re: [Intel-gfx] Trouble with dell latitude E6420

On Thu, Jun 28, 2012 at 07:52:18AM +0200, Takashi Iwai wrote: > At Tue, 26 Jun 2012 15:08:32 -0400, > Giacomo Comes wrote: > > > > I have a dell latitude E6420 with Sandybridge Mobile (GT2). > > Since I got it (about one year ago), it has been a nightmare to run linux > > on it. > > At the beginn

Re: [Intel-gfx] [PULL] drm-intel-next

On Thu, Jun 28, 2012 at 02:05:16PM +0200, Daniel Vetter wrote: > Hi Dave, > > New -next pull request. Highlights: > - Remaining vlv patches from Jesse et al. > - Some hw workarounds from Jesse > - hw context support from Ben > - full uncore sharing on ivb > - prep work to move the gtt code from in

[Intel-gfx] [PULL] drm-intel-next

Hi Dave, New -next pull request. Highlights: - Remaining vlv patches from Jesse et al. - Some hw workarounds from Jesse - hw context support from Ben - full uncore sharing on ivb - prep work to move the gtt code from intel-gtt.c to drm/i915 for gen6+ - some backlight code improvements - leftovers

Re: [Intel-gfx] [PATCH] drm/i915: "Flush Me Harder" required on gen6+

On Thu, 28 Jun 2012 09:48:42 +0200, Daniel Vetter wrote: > The prep to remove the flushing list in > > commit cc889e0f6ce6a63c62db17d702ecfed86d58083f > Author: Daniel Vetter > Date: Wed Jun 13 20:45:19 2012 +0200 > > drm/i915: disable flushing_list/gpu_write_list > > causes quite some

[Intel-gfx] [PATCH] drm/i915: "Flush Me Harder" required on gen6+

The prep to remove the flushing list in commit cc889e0f6ce6a63c62db17d702ecfed86d58083f Author: Daniel Vetter Date: Wed Jun 13 20:45:19 2012 +0200 drm/i915: disable flushing_list/gpu_write_list causes quite some decent regressions. We can fix this by setting the CS_STALL bit to ensure tha

[Intel-gfx] [QA 06/28] Testing report for `drm-intel-testing` (was: Updated -next)

Summary We finished a new round of kernel testing. During this round we filed 8 new bugs and close 6 bugs. So till now, 14 related bugs are still open. For the DRM support more mode lines now, some of the new additional modes don't work. On each kind of display port(eDP, VGA, DVI, HDMI and DP),