== Series Details ==
Series: drm/i915/gvt: dma-buf support for GVT-g (rev8)
URL : https://patchwork.freedesktop.org/series/23686/
State : failure
== Summary ==
CHK include/config/kernel.release
CHK include/generated/uapi/linux/version.h
CHK include/generated/utsrelease.h
CH
User space should create the management fd for the dma-buf operation first.
Then user can query the plane information and create dma-buf if necessary
using the management fd.
Signed-off-by: Xiaoguang Chen
Tested-by: Kechen Lu
---
drivers/gpu/drm/i915/gvt/dmabuf.c| 37 -
drivers/gpu
dmabuf for GVT-g can be exported to users who can use the dmabuf to show
the desktop of vm which use intel vgpu.
Currently we provide query and create new dmabuf operations.
Users of dmabuf can cache some created dmabufs and related information
such as the framebuffer's address, size, tiling mode
OpRegion is needed to support display related operation for
intel vgpu.
A vfio device region is added to intel vgpu to deliver the
host OpRegion information to user space so user space can
construct the OpRegion for vgpu.
Signed-off-by: Bing Niu
Signed-off-by: Xiaoguang Chen
---
drivers/gpu/dr
decode frambuffer attributes of primary, cursor and sprite plane
Signed-off-by: Xiaoguang Chen
---
drivers/gpu/drm/i915/gvt/Makefile | 3 +-
drivers/gpu/drm/i915/gvt/display.c| 2 +-
drivers/gpu/drm/i915/gvt/display.h| 2 +
drivers/gpu/drm/i915/gvt/fb_decoder.c | 425 ++
Here we defined a new ioctl to create a fd for a vfio device based on
the input type. Now only one type is supported that is a dma-buf
management fd.
Two ioctls are defined for the dma-buf management fd: query the vfio
vgpu's plane information and create a dma-buf for a plane.
Signed-off-by: Xiaog
Signed-off-by: Xiaoguang Chen
---
drivers/gpu/drm/i915/gvt/kvmgt.c | 21 ++---
1 file changed, 18 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/kvmgt.c b/drivers/gpu/drm/i915/gvt/kvmgt.c
index 1ae0b40..3c6a02b 100644
--- a/drivers/gpu/drm/i915/gvt/kvmgt.c
++
v7->v8:
1) refine framebuffer decoder code
2) fix a bug in decoding primary plane
v6->v7:
1) release dma-buf related allocations in dma-buf's associated release
function.
2) refine ioctl interface for querying plane info or create dma-buf
3) refine framebuffer decoder code
4) the patch series is b
== Series Details ==
Series: drm/i915: Enable guest i915 full ppgtt functionality (rev3)
URL : https://patchwork.freedesktop.org/series/24774/
State : success
== Summary ==
Series 24774v3 drm/i915: Enable guest i915 full ppgtt functionality
https://patchwork.freedesktop.org/api/1.0/series/2477
Enable the guest i915 full ppgtt functionality when host can provide this
capability. vgt_caps is introduced to guest i915 driver to get the vgpu
capabilities from the device model. VGT_CPAS_FULL_PPGTT is one of the
capabilities type to let guest i915 dirver know that the guest i915 full
ppgtt is s
Hi Dave,
Today's linux-next merge of the drm tree got a conflict in:
drivers/gpu/drm/i915/intel_engine_cs.c
between commit:
ef6c4d75e353 ("drm/i915: fix warning for unused variable")
from the drm-intel-fixes tree and commit:
a8e9a419c337 ("drm/i915: Lie and treat all engines as idle if
== Series Details ==
Series: series starting with [1/2] drm/i915/guc: Load GuC on Coffee Lake
URL : https://patchwork.freedesktop.org/series/25517/
State : success
== Summary ==
Series 25517v1 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/25517/revisions/1/mbox/
== Series Details ==
Series: series starting with [1/3] drm/i915/cfl: Add Coffee Lake PCI IDs for S
Skus.
URL : https://patchwork.freedesktop.org/series/25516/
State : success
== Summary ==
Series 25516v1 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/25516/revis
On Thu, 2017-06-08 at 16:53 -0700, Manasi Navare wrote:
> On Thu, Jun 08, 2017 at 03:03:17PM -0700, Rodrigo Vivi wrote:
> > Also new registers can have different mmio offsets
> > per different lane per port.
> >
> > v2: Use _PICK as PORT3 instead of creating a new
> > macro with if per port.
>
On Thu, 2017-06-08 at 16:41 -0700, Anusha Srivatsa wrote:
> Add PCI Ids for S Sku following the BSpec.
>
> v2: Remove the unused INTEL_CFL_IDS.(Rodrigo)
> v3: Add missing IDs(Rodrigo)
>
> Cc: Rodrigo Vivi
> Signed-off-by: Anusha Srivatsa
> ---
> drivers/gpu/drm/i915/i915_pci.c | 1 +
> includ
Reviewed-by: Rodrigo Vivi
On Thu, 2017-06-08 at 16:41 -0700, Anusha Srivatsa wrote:
> Add PCI Ids for U Skus of Coffeelake.
>
> v2: Use intel_coffeelake_gt3_info, in accordance to-
> Rodrigo's patch:
>
> v3: rebased
>
> v3: Remove unused INTEL_CFL_IDS(Rodrigo).
>
> Cc: Rodrigo Vivi
> Signed
Coffee Lake reuses Kabylake's GuC.
v2: Change Coffeelake to Coffee Lake
Cc: Rodrigo Vivi
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_pci.c | 1 +
drivers/gpu/drm/i915/intel_guc_loader.c | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/d
Reviewed-by: Rodrigo Vivi
On Thu, 2017-06-08 at 16:41 -0700, Anusha Srivatsa wrote:
> Add PCI Ids for H Sku by following the BSpec.
>
> v2: Remove unused INTEL_CFL_IDS.(Rodrigo).
> v3: Add missing IDs(Rodrigo)
>
> Cc: Rodrigo Vivi
> Signed-off-by: Anusha Srivatsa
> ---
> drivers/gpu/drm/i91
Coffee Lake reuses Kabylake's HUC firmware.
v2: Change Coffeelake to Coffee Lake
Cc: Rodrigo Vivi
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_huc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_huc.c b/drivers/gpu/drm/i915/inte
On Thu, Jun 08, 2017 at 03:03:17PM -0700, Rodrigo Vivi wrote:
> Also new registers can have different mmio offsets
> per different lane per port.
>
> v2: Use _PICK as PORT3 instead of creating a new
> macro with if per port.
> v3: Use _PICK directly on MMIO_PORT6. While MMIO_PORT
> isn't f
Add PCI Ids for S Sku following the BSpec.
v2: Remove the unused INTEL_CFL_IDS.(Rodrigo)
v3: Add missing IDs(Rodrigo)
Cc: Rodrigo Vivi
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_pci.c | 1 +
include/drm/i915_pciids.h | 8
2 files changed, 9 insertions(+)
diff
Add PCI Ids for H Sku by following the BSpec.
v2: Remove unused INTEL_CFL_IDS.(Rodrigo).
v3: Add missing IDs(Rodrigo)
Cc: Rodrigo Vivi
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_pci.c | 1 +
include/drm/i915_pciids.h | 5 +
2 files changed, 6 insertions(+)
diff --g
Add PCI Ids for U Skus of Coffeelake.
v2: Use intel_coffeelake_gt3_info, in accordance to-
Rodrigo's patch:
v3: rebased
v3: Remove unused INTEL_CFL_IDS(Rodrigo).
Cc: Rodrigo Vivi
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_pci.c | 1 +
include/drm/i915_pciids.h | 7 +++
Matches pseudo code in BSpec.
Reviewed-by: Clint Taylor
On 06/08/2017 04:03 PM, Rodrigo Vivi wrote:
From: "Kahola, Mika"
Enable wrpll computation for Cannonlake platform to support
pll's required for HDMI output. The patch contains the following features
- compute Cannonlake port clock pro
From: "Kahola, Mika"
Enable wrpll computation for Cannonlake platform to support
pll's required for HDMI output. The patch contains the following features
- compute Cannonlake port clock programming
dividers P, Q, and K.
- compute PLL parameters for Cannonlake. These parameters
set the value
== Series Details ==
Series: series starting with [01/17] drm/i915/cnl: Implement
.get_display_clock_speed() for CNL
URL : https://patchwork.freedesktop.org/series/25511/
State : success
== Summary ==
Series 25511v1 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/
\o/
Reviewed-by: Rodrigo Vivi
On Thu, Jun 8, 2017 at 4:48 AM, Ander Conselvan de Oliveira
wrote:
> Geminilake is now included in CI, making it part of the pre-merge
> criteria. The support should be in good enough shape, so let's remove
> the alpha_support flag.
>
> Signed-off-by: Ander Conselv
From: Ville Syrjälä
Add support for changing the cdclk frequency on CNL. Again, quite
similar to BXT, but there are some annoying differences which means
trying to share more code might not be feasible:
* PLL ratio now lives in the PLL enable register
* pcode came from SKL, not from BXT
We suppo
One of the steps for PLL (un)initialization is to (un)map
the correspondent DDI that is actually using that PLL.
So, let's do this step following the places already stablished
and used so far, although spec put this as part of PLL
initialization sequences.
v2: Use proper prefix on bits names as s
Since we have HAS_CSR tied to the platform definition
let's use this instead of checking per platform.
One less thing to worry when adding support to new platforms.
Signed-off-by: Rodrigo Vivi
Reviewed-by: Animesh Manna
---
drivers/gpu/drm/i915/intel_csr.c | 2 +-
1 file changed, 1 insertion(+)
Also new registers can have different mmio offsets
per different lane per port.
v2: Use _PICK as PORT3 instead of creating a new
macro with if per port.
v3: Use _PICK directly on MMIO_PORT6. While MMIO_PORT
isn't flexible enough let's continue with MMIO_PORT6
as we have MMIO_PORT3.
Cc
From: Clint Taylor
vswing programming sequence step 2 requires the Loadgen_select bit to
be set in PORT_TX_DW4 lane reigsters per table defined by Bit rate and
lane width. Implemented the change that was marked as FIXME in the
driver.
v2: (Rodrigo) checkpatch fixes.
Signed-off-by: Clint Taylor
As Geminilake scalers Cannonlake also don't need and don't have
the "high quality" mode programming.
Cc: Ander Conselvan de Oliveira
Signed-off-by: Rodrigo Vivi
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_atomic.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
This are the registers and bits needed for the voltage swing
sequence on Cannonlake.
v2: Remove CL_DW5 that was wrongly defined.
v3: Use (1 << 1) instead of (1<<1) as Paulo suggested
Change DW2 swing sel upper and lower macros to do the
bit selection instead of definint a table that doesn'
This is an important part of the DDI initalization as well as
for changing the voltage during DisplayPort link training.
This new sequence for Cannonlake is more like Broxton style
but still with different registers, different table and
different steps.
v2: Do not write to DW4_GRP to avoid overwr
There is no platform specific change needed for LSPCON
support on Cannonlake. So let's make it gen9+.
Cc: Shashank Sharma
Signed-off-by: Rodrigo Vivi
Reviewed-by: Shashank Sharma
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu
From: Anusha Srivatsa
This patch loads the DMC on CNL.The firmware version
is 1.04.
v2: (Rodrigo) Remove MODULE_FIRMWARE.
Cc: Rodrigo Vivi
Signed-off-by: Anusha Srivatsa
Signed-off-by: Rodrigo Vivi
Reviewed-by: Animesh Manna
---
drivers/gpu/drm/i915/i915_pci.c | 1 +
drivers/gpu/drm/i915
From: "Kahola, Mika"
DPLL's are defined in DPCLKA_CFGCR0 register (0x6C200). Let's use these
definitions when computing dpll's for ddi ports.
v2: (Rodrigo) Remove register that was defined in another patch with
fixed name and more bits.
Signed-off-by: Kahola, Mika
Signed-off-by: Rodrigo Vi
Although CNL follows PLL initialization more like Skylake
than Broxton we have a completely different initialization
sequence and registers used.
One big difference from SKL is that CDCLK PLL is now
exclusive (ADPLL) and for DDIs and MIPI we need to use
DFGPLLs 0, 1 or 2.
v2: Accept all Ander's s
All the low level cdclk bits are present, so let's add the required
hooks to reconfigure cdclk on the fly.
v2: Rebase due to cnl_sanitize_cdclk()
v3: Rebased by Rodrigo on top of Ville's cdclk rework.
v4: Rebase moving cnl_calc_cdclk up to follow same order
as previous platforms.
v2: Squash dr
Also in a way that reuse bdw+ for all next platforms.
Signed-off-by: Rodrigo Vivi
Reviewed-by: Mika Kahola
---
drivers/gpu/drm/i915/intel_fifo_underrun.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_fifo_underrun.c
b/drivers/gpu/drm/i915/intel_
From: Ville Syrjälä
Implement the CNL display init/uninit sequence as outlined in Bspec.
Quite similar to SKL/BXT. The main complicaiton is probably the extra
procmon setup we must do based on the process/voltage information we
can read out from some register.
v2: s/skl_dbuf/gen9_dbuf/ to follo
From: Ville Syrjälä
Add support for reading out the cdclk frequency from the hardware on
CNL. Very similar to BXT, with a few new twists and turns:
* the PLL is now called CDCLK PLL, not DE PLL
* reference clock can be 24 MHz in addition to the 19.2 MHz BXT had
* the ratio now lives in the PLL en
These tables are used on voltage wswing sequence initialization
on Cannonlake.
It is a complete new format now in use by the voltage swing team,
not following any other standard in use by any other platform.
Also the registers are different as well. So let's redefine
the translation table for Cann
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of sunpeng...@amd.com
> Sent: Thursday, June 08, 2017 3:11 PM
> To: intel-gfx@lists.freedesktop.org; amd-...@lists.freedesktop.org;
> Wentland, Harry
> Cc: Li, Sun peng
> Subject: [PATCH i-g-t] t
From: "Leo (Sunpeng) Li"
Increasing max pipe count to 6 to support AMD GPU's.
Since some tests' behavior depends on this value, small changes are made
to remove this dependency:
* kms_ccs: Early abort if wanted_pipe is out-of-bounds.
* kms_concurrent: Check if pipe is within bounds first.
* kms
On 2017-05-31 01:52, Daniel Vetter wrote:
> On Tue, May 30, 2017 at 02:17:04PM -0700, Stefan Agner wrote:
>> On 2017-05-26 00:00, Daniel Vetter wrote:
>> > On Thu, May 25, 2017 at 10:18 AM, Stefan Agner wrote:
>> >> On 2017-05-24 07:51, Daniel Vetter wrote:
>> >>> Again cleanup before irq disablin
== Series Details ==
Series: series starting with [v2,1/2] drm/i915/dp: Generalize
intel_dp_link_params function to accept arguments to be validated
URL : https://patchwork.freedesktop.org/series/25506/
State : success
== Summary ==
Series 25506v1 Series without cover letter
https://patchwork
== Series Details ==
Series: sna: Add XV_COLORSPACE attribute support for sprite Xv adaptors
URL : https://patchwork.freedesktop.org/series/25505/
State : failure
== Summary ==
CHK include/config/kernel.release
CHK include/generated/uapi/linux/version.h
CHK include/generated/
Validate the compliance test link parameters when the compliance
test dpcd registers are read. Also validate them in compute_config
before using them since the max values might have been reduced
due to link training fallback.
If either the link rate or lane count is invalid, we still bail
from usi
This function now takes the link rate and lane ocunt to be validated
as an argument so that this can be used for validating even the
compliance test link parameters.
Signed-off-by: Manasi Navare
Cc: Ville Syrjala
Cc: Jani Nikula
Reviewed-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_dp.c | 1
From: Ville Syrjälä
Use the new "COLOR_ENCODING" plane property to implement the
XV_COLORSPACE port attribute for sprite Xv adaptors.
Cc: Jyri Sarha
Cc: Chris Wilson
Signed-off-by: Ville Syrjälä
---
src/sna/sna.h | 1 +
src/sna/sna_display.c | 148
From: Ville Syrjälä
Add support for the COLOR_ENCODING plane property which selects
the matrix coefficients used for the YCbCr->RGB conversion. Our
hardware can generally handle BT.601 and BT.709.
CHV pipe B sprites have a fully programmable matrix, so in theory
we could handle anything, but it
From: Ville Syrjälä
On GLK the plane CSC controls moved into the COLOR_CTL register.
Update the code to progam the YCbCr->RGB CSC mode correctly when
faced with an YCbCr framebuffer.
The spec is rather confusing as it calls the mode "YUV601 to RGB709".
I'm going to assume that just means it's go
From: Ville Syrjälä
While reviewing the COLOR_ENCODING/COLOR_RANGE props I decided that I
might as well implement them in i915. And here is the result.
With this the user can now select between BT.601 vs. BT.709, and
limited vs. full range on every platform where we currently have
YCbCr framebuf
From: Ville Syrjälä
Bring us forward from the stone age and switch our default YCbCr->RGB
conversion matrix to BT.709 from BT.601. I would expect most matrial
to be BT.709 these days.
Cc: Jyri Sarha
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_display.c | 2 +-
drivers/gpu/drm/
From: Ville Syrjälä
Turns out the VLV/CHV fixed function sprite CSC expects full range
data as input. We've been feeding it limited range data to it all
along. To expand the data out to full range we'll use the color
correction registers (brightness, contrast, and saturation).
On CHV pipe B we w
From: Ville Syrjälä
Add support for the COLOR_RANGE property on planes. This property
selects whether the input YCbCr data is to treated as limited range
or full range.
On most platforms this is a matter of setting the "YUV range correction
disable" bit, and on VLV/CHV we'll just have to program
Quoting Michal Wajdeczko (2017-06-08 17:22:40)
> On Thu, Jun 08, 2017 at 07:03:55PM +0300, Ville Syrjälä wrote:
> > On Thu, Jun 08, 2017 at 03:07:32PM +, Michal Wajdeczko wrote:
> > > This is the only field from i915_params struct which name does not match
> > > the the name of the param that i
On Fri, Jun 02, 2017 at 11:55:32AM +0300, Jani Nikula wrote:
> On Fri, 02 Jun 2017, Jani Nikula wrote:
> > On Fri, 02 Jun 2017, Manasi Navare wrote:
> >> Validate the compliance test link parameters when the compliance
> >> test dpcd registers are read. Also validate them in compute_config
> >> b
== Series Details ==
Series: drm/i915: Make MMIO_PORT flexible.
URL : https://patchwork.freedesktop.org/series/25491/
State : failure
== Summary ==
Series 25491v1 drm/i915: Make MMIO_PORT flexible.
https://patchwork.freedesktop.org/api/1.0/series/25491/revisions/1/mbox/
Test gem_exec_suspend:
On Thu, Jun 08, 2017 at 04:36:25PM +, Navare, Manasi D wrote:
> On Thu, Jun 08, 2017 at 12:59:23AM +, Navare, Manasi D wrote:
> > Hi,
> >
> > I am executing the DP compliance test suite and the only test
> > currently failing with the drm-tip + my patch
> > (https://patchwork.freedeskt
On Thu, 2017-06-08 at 19:54 +0300, Mika Kuoppala wrote:
> Rodrigo Vivi writes:
>
> > WA to disable replay buffer destination buffer arbitration optimization.
> >
> > Same Wa on previous platforms has a different name:
> > WaToEnableHwFixForPushConstHWBug
> >
> > Signed-off-by: Rodrigo Vivi
> >
Rodrigo Vivi writes:
> WA forTDS handle reallocation getting dropped by SDE,
> which may result in PS attribute corruption.
>
> Disable enhanced SBE vertex caching in COMMON_SLICE_CHICKEN2 offset.
>
> Signed-off-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/intel_engine_cs.c | 4
> 1 file
In the past the magic reg_a + (reg_b - reg_a) * port
was enough because every new register that was appearing
on new platforms was respecting the same gap.
However on more recent platforms we start seeing many
registers that doesn't respect the gap. So picking from
a list of registers seems to be
patches merged to dinq.
Thanks for the reviews.
On Thu, Jun 8, 2017 at 8:50 AM, Rodrigo Vivi wrote:
> The whole Display engine for Coffee Lake is pretty much
> identical to the Kabylake. For this reason let's reuse
> all display related production workardounds here even though
> CFL is not explic
Rodrigo Vivi writes:
> WA to disable replay buffer destination buffer arbitration optimization.
>
> Same Wa on previous platforms has a different name:
> WaToEnableHwFixForPushConstHWBug
>
> Signed-off-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/intel_engine_cs.c | 4
> 1 file changed,
On Thu, Jun 08, 2017 at 12:59:23AM +, Navare, Manasi D wrote:
> Hi,
>
> I am executing the DP compliance test suite and the only test
> currently failing with the drm-tip + my patch
> (https://patchwork.freedesktop.org/series/25191/)
> Is the power management test (4.4.3) where it expects
On Thu, Jun 08, 2017 at 07:03:55PM +0300, Ville Syrjälä wrote:
> On Thu, Jun 08, 2017 at 03:07:32PM +, Michal Wajdeczko wrote:
> > This is the only field from i915_params struct which name does not match
> > the the name of the param that it is associated with. Lets fix that now
> > as this wil
== Series Details ==
Series: series starting with [1/3] drm/i915/cfl: Introduce Coffee Lake platform
definition.
URL : https://patchwork.freedesktop.org/series/25486/
State : success
== Summary ==
Series 25486v1 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/2548
Quoting Michal Hocko (2017-06-08 13:26:22)
> Do you plan to merge this patch? I would like to post my
> __GFP_RETRY_MAYFAIL series sometime soon and would like to cover this
> one as well.
Yes, just a strict policy on getting some sucker to review it first.
-Chris
_
On Thu, Jun 08, 2017 at 03:07:32PM +, Michal Wajdeczko wrote:
> This is the only field from i915_params struct which name does not match
> the the name of the param that it is associated with. Lets fix that now
> as this will unblock us with further improvements around params defs.
Maybe we sh
On Thu, Jun 08, 2017 at 05:47:23PM +0300, Jani Nikula wrote:
> On Thu, 08 Jun 2017, Ville Syrjälä wrote:
> > On Wed, Jun 07, 2017 at 04:45:07PM +0300, Jani Nikula wrote:
> >> On Mon, 15 May 2017, Jani Nikula wrote:
> >> > The following commits have been marked as Cc: stable or fixing something
>
So let's force it on the virtual detection.
Also it is still the only silicon for now on this PCH,
so WARN otherwise.
v2: Rebased on top of Cannonlake and added the missed
debug message as pointed by DK.
Cc: Dhinakaran Pandiyan
Signed-off-by: Rodrigo Vivi
Reviewed-by: Anusha Srivatsa
---
Coffee Lake is a Intel® Processor containing Intel® HD Graphics
following Kabylake.
It is Gen9 graphics based platform on top of CNP PCH.
Let's start by adding the platform definition based on previous
platforms but yet as preliminary_hw_support.
On following patches we will start adding PCI IDs
The whole Display engine for Coffee Lake is pretty much
identical to the Kabylake. For this reason let's reuse
all display related production workardounds here even though
CFL is not explicit listed at Display workarounds page at Spec.
v2: moved intel_pm.c chunck to this patch in order to address
We know default values for all params and we know which params are safe
to change. Mark params that were changed when dumping them in debugfs.
v2: simplify is_default calculation for strings (Chris)
Suggested-by: Chris Wilson
Signed-off-by: Michal Wajdeczko
Cc: Chris Wilson
---
drivers/gpu/dr
On 06/08/2017 04:45 AM, Szwichtenberg, Radoslaw wrote:
On Wed, 2017-06-07 at 10:45 -0700, clinton.a.tay...@intel.com wrote:
From: Clint Taylor
RGB565 Pixel format planes can now be rotated at 90 and 270 degrees
Signed-off-by: Clint Taylor
---
drivers/gpu/drm/i915/intel_atomic_plane.c | 1
== Series Details ==
Series: drm/i915: Misc improvements around module params
URL : https://patchwork.freedesktop.org/series/25482/
State : success
== Summary ==
Series 25482v1 drm/i915: Misc improvements around module params
https://patchwork.freedesktop.org/api/1.0/series/25482/revisions/1/m
Quoting Michal Wajdeczko (2017-06-08 16:07:34)
> We know default values for all params and we know which params are safe
> to change. Mark params that were changed when dumping them in debugfs.
>
> Suggested-by: Chris Wilson
> Signed-off-by: Michal Wajdeczko
> Cc: Chris Wilson
> ---
> drivers/
This is the only field from i915_params struct which name does not match
the the name of the param that it is associated with. Lets fix that now
as this will unblock us with further improvements around params defs.
Signed-off-by: Michal Wajdeczko
Cc: Chris Wilson
---
drivers/gpu/drm/i915/i915_p
Earlier RFC proposed to extend param macros with default values.
This series goes step further.
Michal Wajdeczko (3):
drm/i915: Rename i915.panel_use_ssc field to lvds_use_ssc
drm/i915: Extend PARAMS_FOR_EACH macro with more data
drm/i915/debugfs: Highlight modified i915 params
drivers/gp
== Series Details ==
Series: NOTFORUPSTREAM sound/hda: add debug information in call_hp_automute
(rev2)
URL : https://patchwork.freedesktop.org/series/25472/
State : success
== Summary ==
Series 25472v2 NOTFORUPSTREAM sound/hda: add debug information in
call_hp_automute
https://patchwork.fre
Currently our PARAMS_FOR_EACH macro contains only param type and name.
We use this macro to define struct members, but later on we initialize
this struct using handcrafted code, which leads in some cases to use
mismatched value vs. type. Let's extend our root macro with param
default value to keep
We know default values for all params and we know which params are safe
to change. Mark params that were changed when dumping them in debugfs.
Suggested-by: Chris Wilson
Signed-off-by: Michal Wajdeczko
Cc: Chris Wilson
---
drivers/gpu/drm/i915/i915_debugfs.c | 53 --
On to, 2017-04-06 at 12:15 -0700, Rodrigo Vivi wrote:
> By spec there is no change on force wake registers
> for Cannonlake. Let's reuse gen9 one.
>
> v2: Adding missing case for the write part. (Tvrtko)
> v3: Rebase on recent tree.
>
> Cc: Tvrtko Ursulin
> Signed-off-by: Rodrigo Vivi
Bspec: 1
On Thu, 08 Jun 2017, Ville Syrjälä wrote:
> On Wed, Jun 07, 2017 at 04:45:07PM +0300, Jani Nikula wrote:
>> On Mon, 15 May 2017, Jani Nikula wrote:
>> > The following commits have been marked as Cc: stable or fixing something
>> > in v4.12-rc1 or earlier, but failed to cherry-pick to
>> > drm-int
From: Ville Syrjälä
skl_check_plane_surface() already rotates the clipped plane source
coordinates to match the scanout direction because that's the way
the GTT mapping is set up. Thus we no longer need to rotate the
coordinates in the watermark code.
For cursors we use the non-clipped coordinat
From: Ville Syrjälä
Starting from commit b63a16f6cd89 ("drm/i915: Compute display surface
offset in the plane check hook for SKL+") we've already rotated the src
coordinates by 270 degrees by the time we check if a scaler is needed
or not, so we must not account for the rotation a second time.
Pr
Hi Dave, fixes all around for drm/i915, half stable, half for this merge
window.
There's a last minute build warning fix on top that I failed to notice
earlier, everything else was pushed earlier.
BR,
Jani.
The following changes since commit 3c2993b8c6143d8a5793746a54eba8f86f95240f:
Linux 4
On Wed, Jun 07, 2017 at 04:45:07PM +0300, Jani Nikula wrote:
> On Mon, 15 May 2017, Jani Nikula wrote:
> > The following commits have been marked as Cc: stable or fixing something
> > in v4.12-rc1 or earlier, but failed to cherry-pick to
> > drm-intel-fixes. Please see if they are worth backportin
I would like to send this patch to the core-for-CI branch, in order to
verify the theory I exposed in fdo#101246.
This patch also hides a potentially serious bug in the sound/hda
driver, which may improve our chances of not being affected by
bugs there. It may actually also fix some of the incompl
On Thu, Jun 08, 2017 at 03:23:09PM +0300, Petri Latvala wrote:
> The separation of testcases with and without subtests in the build
> system was used in the past, but now both are handled the same
> way. Merge them together and finally forget about the difference
> between TESTS_progs and TESTS_pro
Rodrigo Vivi writes:
> Coffee Lake inherit most of Kabylake production
> workardounds.
>
> Only difference identified so far is:
> - WaDisableLSQCROPERFforOCL is marked as SIWA_NEVER
>
> Cc: Dhinakaran Pandiyan
> Signed-off-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/i915_gem_gtt.c| 2 +
On Thu, Jun 08, 2017 at 03:23:08PM +0300, Petri Latvala wrote:
> The tests listed in XFAIL_TESTS have moved to lib/tests quite a while
> ago.
>
> Signed-off-by: Petri Latvala
Reviewed-by: Arkadiusz Hiler
--
Cheers,
Arek
___
Intel-gfx mailing list
Int
Quoting Ville Syrjälä (2017-06-08 14:47:27)
> On Thu, Jun 08, 2017 at 10:51:34AM +0100, Chris Wilson wrote:
> > + ret = i915_gem_object_pin_pages(obj);
> > + if (ret)
> > + return ret;
> > +
> > + ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
> > + if (ret
On Thu, Jun 08, 2017 at 10:51:34AM +0100, Chris Wilson wrote:
> Reduce acquisition of struct_mutex to the critical regions that must
> hold it; for KMS, we need struct_mutex currently only for the purpose of
> pinning/unpinning the framebuffer's VMA into the global GTT. This allows
> us to avoid ta
On Thu, Jun 08, 2017 at 12:59:23AM +, Navare, Manasi D wrote:
> Hi,
>
> I am executing the DP compliance test suite and the only test currently
> failing with the drm-tip + my patch
> (https://patchwork.freedesktop.org/series/25191/)
> Is the power management test (4.4.3) where it expects
The separation of testcases with and without subtests in the build
system was used in the past, but now both are handled the same
way. Merge them together and finally forget about the difference
between TESTS_progs and TESTS_progs_M.
Signed-off-by: Petri Latvala
---
tests/Makefile.am | 16
The tests listed in XFAIL_TESTS have moved to lib/tests quite a while
ago.
Signed-off-by: Petri Latvala
---
tests/Makefile.sources | 8
1 file changed, 8 deletions(-)
diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index b3a680e..14ea5b6 100644
--- a/tests/Makefile.sources
1 - 100 of 137 matches
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