Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v8,01/12] drm/i915: Park before resetting the submission backend

[Sagar Arun Kamble]

On 4/9/2018 9:02 PM, Michal Wajdeczko wrote:
On Mon, 09 Apr 2018 17:09:18 +0200, Patchwork 
 wrote:



== Series Details ==

Series: series starting with [v8,01/12] drm/i915: Park before 
resetting the submission backend

URL   : https://patchwork.freedesktop.org/series/41365/
State : failure

== Summary ==

 Possible new issues:


two variants:



Test drm_mm:
    Subgroup sanitycheck:
    pass   -> INCOMPLETE (shard-apl)


#1

<0>[  400.245461] drv_self-5775    1 400208508us : 
intel_guc_submission_disable: intel_guc_submission_disable:1255 
GEM_BUG_ON(dev_priv->gt.awake)


<4>[  400.245871] Call Trace:
<4>[  400.245959]  intel_uc_fini_hw+0x4b/0xe0 [i915]
<4>[  400.246047]  i915_gem_fini_hw+0x16/0x30 [i915]
<4>[  400.246129]  i915_reset+0x1e8/0x2b0 [i915]
<4>[  400.246222]  igt_global_reset+0x38/0xe0 [i915]


Without gem_set_wedged if i915_reset path is invoked we can face this issue.
igt_global_reset and gem_eio resets are directly invoking 
i915_handle_error/i915_reset so I think we should fix the IGTs.

Test drv_hangman:
    Subgroup error-state-capture-blt:
    pass   -> INCOMPLETE (shard-apl)
    Subgroup error-state-capture-bsd:
    pass   -> INCOMPLETE (shard-apl)
    Subgroup error-state-capture-render:
    pass   -> INCOMPLETE (shard-apl)
    Subgroup error-state-capture-vebox:
    pass   -> INCOMPLETE (shard-apl)
Test drv_selftest:
    Subgroup live_guc:
    pass   -> SKIP   (shard-apl)
    Subgroup live_hangcheck:
    pass   -> DMESG-FAIL (shard-apl)
Test gem_eio:
    Subgroup execbuf:
    pass   -> INCOMPLETE (shard-apl)


#2:

<3>[  227.833798] intel_engine_unpin_breadcrumbs_irq:219 
GEM_BUG_ON(!b->irq_enabled)


<4>[  227.834607] Call Trace:
<4>[  227.834691]  intel_engines_park+0xef/0x180 [i915]
<4>[  227.834709]  ? synchronize_irq+0x3e/0xb0
<4>[  227.834781]  __i915_gem_park+0x3e/0x160 [i915]
<4>[  227.834850]  i915_gem_idle_work_handler+0x1cd/0x220 [i915]
<4>[  227.834868]  process_one_work+0x21a/0x640


irq disabling with GuC submission is not taking into consideration if it 
was enabled by waiter.
May be we should skip disarming interrupts while parking if there was no 
waiter since we will disarm them

during engine->park. Something like below?

diff --git a/drivers/gpu/drm/i915/intel_breadcrumbs.c 
b/drivers/gpu/drm/i915/intel_breadcrumbs.c

index 671a6d6..f8c0c4d 100644
--- a/drivers/gpu/drm/i915/intel_breadcrumbs.c
+++ b/drivers/gpu/drm/i915/intel_breadcrumbs.c
@@ -231,6 +231,13 @@ void intel_engine_disarm_breadcrumbs(struct 
intel_engine_cs *engine)

    return;

    /*
+    * In case of reset with GuC submission we disarm the interrupts
+    * while parking if there are no waiters.
+    */
+   if (USES_GUC_SUBMISSION(engine->i915) && !b->irq_wait)
+   return;
+
+   /*
 * We only disarm the irq when we are idle (all requests 
completed),

 * so if the bottom-half remains asleep, it missed the request
 * completion.

    Subgroup in-flight-external:
    pass   -> INCOMPLETE (shard-apl)
Test gem_mocs_settings:
    Subgroup mocs-reset-dirty-render:
    pass   -> INCOMPLETE (shard-apl)
Test gem_request_retire:
    Subgroup retire-vma-not-inactive:
    pass   -> INCOMPLETE (shard-apl)
Test gem_workarounds:
    Subgroup reset-context:
    pass   -> INCOMPLETE (shard-apl)
Test kms_vblank:
    Subgroup pipe-a-query-idle-hang:
    pass   -> INCOMPLETE (shard-apl)
    Subgroup pipe-a-ts-continuation-idle-hang:
    pass   -> INCOMPLETE (shard-apl)
    Subgroup pipe-a-wait-busy-hang:
    pass   -> INCOMPLETE (shard-apl)
    Subgroup pipe-a-wait-forked-busy-hang:
    pass   -> INCOMPLETE (shard-apl)
    Subgroup pipe-a-wait-idle-hang:
    pass   -> INCOMPLETE (shard-apl)
    Subgroup pipe-b-query-forked-hang:
    pass   -> INCOMPLETE (shard-apl)
    Subgroup pipe-c-query-busy-hang:
    pass   -> INCOMPLETE (shard-apl)
    Subgroup pipe-c-query-forked-busy-hang:
    pass   -> INCOMPLETE (shard-apl)
    Subgroup pipe-c-query-forked-hang:
    pass   -> INCOMPLETE (shard-apl)
    Subgroup pipe-c-ts-continuation-idle-hang:
    pass   -> INCOMPLETE (shard-apl)
Test perf:
    Subgroup gen8-unprivileged-single-ctx-counters:
    pass   -> FAIL   (shard-apl)

 Known issues:

Test drv_missed_irq:
    pass   -> SKIP   (shard-apl) fdo#103199
Test gem_eio:
    Subgroup in-flight-suspend:
    pass   -> INCOMPLETE (shard-apl) fdo#103375
Test kms_flip:
    Subgroup flip-vs-expired-vblank:

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v3,1/4] drm/i915: Always do WOPCM partitioning based on real firmware sizes

[Patchwork]

== Series Details ==

Series: series starting with [v3,1/4] drm/i915: Always do WOPCM partitioning 
based on real firmware sizes
URL   : https://patchwork.freedesktop.org/series/41409/
State : failure

== Summary ==

 Possible new issues:

Test gem_eio:
Subgroup execbuf:
pass   -> INCOMPLETE (shard-apl)
Subgroup throttle:
pass   -> INCOMPLETE (shard-apl)
Test kms_cursor_legacy:
Subgroup pipe-c-torture-move:
dmesg-warn -> PASS   (shard-hsw)
Test kms_plane:
Subgroup pixel-format-pipe-b-planes:
dmesg-warn -> PASS   (shard-hsw)
Test perf:
Subgroup gen8-unprivileged-single-ctx-counters:
pass   -> FAIL   (shard-apl)
Test pm_rpm:
Subgroup debugfs-read:
pass   -> DMESG-WARN (shard-apl)

 Known issues:

Test drv_missed_irq:
pass   -> SKIP   (shard-apl) fdo#103199
Test kms_flip:
Subgroup 2x-plain-flip-ts-check-interruptible:
pass   -> FAIL   (shard-hsw) fdo#100368
Subgroup dpms-vs-vblank-race:
fail   -> PASS   (shard-hsw) fdo#103060

fdo#103199 https://bugs.freedesktop.org/show_bug.cgi?id=103199
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060

shard-apltotal:2586 pass:1774 dwarn:2   dfail:0   fail:11  skip:796 
time:11920s
shard-hswtotal:2680 pass:1785 dwarn:1   dfail:0   fail:2   skip:891 
time:11327s
Blacklisted hosts:
shard-kbltotal:2467 pass:1789 dwarn:21  dfail:0   fail:10  skip:641 
time:7348s
shard-snbtotal:2680 pass:1377 dwarn:1   dfail:0   fail:3   skip:1299 
time:6880s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8649/shards.html
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Re: [Intel-gfx] [PATCH v1 00/14] Preparation patches for NV12

[Srinivas, Vidya]

> -Original Message-
> From: Maarten Lankhorst [mailto:maarten.lankho...@linux.intel.com]
> Sent: Monday, April 9, 2018 5:15 PM
> To: Srinivas, Vidya ; intel-
> g...@lists.freedesktop.org
> Cc: Kamath, Sunil 
> Subject: Re: [Intel-gfx] [PATCH v1 00/14] Preparation patches for NV12
> 
> Op 09-04-18 om 11:41 schreef Srinivas, Vidya:
> >
> >> -Original Message-
> >> From: Maarten Lankhorst [mailto:maarten.lankho...@linux.intel.com]
> >> Sent: Monday, April 9, 2018 2:38 PM
> >> To: Srinivas, Vidya ; intel-
> >> g...@lists.freedesktop.org
> >> Cc: Kamath, Sunil 
> >> Subject: Re: [Intel-gfx] [PATCH v1 00/14] Preparation patches for
> >> NV12
> >>
> >> Op 09-04-18 om 10:57 schreef Srinivas, Vidya:
>  -Original Message-
>  From: Maarten Lankhorst [mailto:maarten.lankho...@linux.intel.com]
>  Sent: Monday, April 9, 2018 2:04 PM
>  To: Srinivas, Vidya ; intel-
>  g...@lists.freedesktop.org
>  Subject: Re: [Intel-gfx] [PATCH v1 00/14] Preparation patches for
>  NV12
> 
>  Op 09-04-18 om 05:40 schreef Vidya Srinivas:
> > Series contain preparation patches for NV12 support Enabling NV12
> > KMD support will follow the series
> >
> > Chandra Konduru (3):
> >   drm/i915: Set scaler mode for NV12
> >   drm/i915: Update format_is_yuv() to include NV12
> >   drm/i915: Upscale scaler max scale for NV12
> >
> > Mahesh Kumar (9):
> >   drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values
> >   drm/i915/skl+: refactor WM calculation for NV12
> >   drm/i915/skl+: add NV12 in skl_format_to_fourcc
> >   drm/i915/skl+: support verification of DDB HW state for NV12
> >   drm/i915/skl+: NV12 related changes for WM
> >   drm/i915/skl+: pass skl_wm_level struct to wm compute func
> >   drm/i915/skl+: make sure higher latency level has higher wm value
> >   drm/i915/skl+: nv12 workaround disable WM level 1-7
> >   drm/i915/skl: split skl_compute_ddb function
> >
> > Vidya Srinivas (2):
> >   drm/i915: Display WA 827
> >   drm/i915: Enable YUV to RGB for Gen10 in Plane Ctrl Reg
> >
> >  drivers/gpu/drm/i915/i915_drv.h  |  10 +-
> >  drivers/gpu/drm/i915/i915_reg.h  |   5 +
> >  drivers/gpu/drm/i915/intel_atomic.c  |  14 +-
> > drivers/gpu/drm/i915/intel_display.c |  93 ++--
> >  drivers/gpu/drm/i915/intel_drv.h |  11 +-
> >  drivers/gpu/drm/i915/intel_pm.c  | 438
> ++--
> >> ---
>  
> >  drivers/gpu/drm/i915/intel_sprite.c  |   7 +-
> >  7 files changed, 393 insertions(+), 185 deletions(-)
>  This series looks good, so for any patches I missed:
> 
>  Reviewed-by: Maarten Lankhorst 
> 
>  Do you have commit rights, or should I push them?
> >>> Thank you. I don’t have commit rights I think.
> >>> Also, Should I add your RB for all the patches and push them again?
> >>>
> >> I'll push them. :)
> > Thank you so much :)
> >
> Pushed!
Thank you so much.

Regards
Vidya
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[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v4] drm/i915: Enable edp psr error interrupts on hsw (rev3)

[Patchwork]

== Series Details ==

Series: series starting with [v4] drm/i915: Enable edp psr error interrupts on 
hsw (rev3)
URL   : https://patchwork.freedesktop.org/series/41095/
State : success

== Summary ==

 Possible new issues:

Test kms_cursor_legacy:
Subgroup pipe-c-torture-move:
dmesg-warn -> PASS   (shard-hsw)
Test kms_plane:
Subgroup pixel-format-pipe-b-planes:
dmesg-warn -> PASS   (shard-hsw)

 Known issues:

Test kms_flip:
Subgroup 2x-plain-flip-ts-check:
pass   -> FAIL   (shard-hsw) fdo#100368
Subgroup dpms-vs-vblank-race:
fail   -> PASS   (shard-hsw) fdo#103060
Test kms_rotation_crc:
Subgroup sprite-rotation-270:
pass   -> FAIL   (shard-apl) fdo#103356

fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
fdo#103356 https://bugs.freedesktop.org/show_bug.cgi?id=103356

shard-apltotal:2680 pass:1834 dwarn:1   dfail:0   fail:8   skip:836 
time:12726s
shard-hswtotal:2680 pass:1785 dwarn:1   dfail:0   fail:2   skip:891 
time:11285s
Blacklisted hosts:
shard-kbltotal:2680 pass:1963 dwarn:1   dfail:0   fail:6   skip:710 
time:9201s
shard-snbtotal:2680 pass:1377 dwarn:1   dfail:0   fail:3   skip:1299 
time:6884s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8648/shards.html
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v3,1/4] drm/i915: Always do WOPCM partitioning based on real firmware sizes

[Patchwork]

== Series Details ==

Series: series starting with [v3,1/4] drm/i915: Always do WOPCM partitioning 
based on real firmware sizes
URL   : https://patchwork.freedesktop.org/series/41409/
State : success

== Summary ==

Series 41409v1 series starting with [v3,1/4] drm/i915: Always do WOPCM 
partitioning based on real firmware sizes
https://patchwork.freedesktop.org/api/1.0/series/41409/revisions/1/mbox/

 Known issues:

Test gem_exec_suspend:
Subgroup basic-s3:
dmesg-warn -> PASS   (fi-glk-j4005) fdo#103359
Test gem_mmap_gtt:
Subgroup basic-small-bo-tiledx:
fail   -> PASS   (fi-gdg-551) fdo#102575
Test kms_flip:
Subgroup basic-flip-vs-wf_vblank:
fail   -> PASS   (fi-glk-j4005) fdo#100368
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-c:
pass   -> INCOMPLETE (fi-bxt-dsi) fdo#103927

fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359
fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927

fi-bdw-5557u total:285  pass:264  dwarn:0   dfail:0   fail:0   skip:21  
time:433s
fi-bdw-gvtdvmtotal:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:443s
fi-blb-e6850 total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  
time:380s
fi-bsw-n3050 total:285  pass:239  dwarn:0   dfail:0   fail:0   skip:46  
time:538s
fi-bwr-2160  total:285  pass:180  dwarn:0   dfail:0   fail:0   skip:105 
time:298s
fi-bxt-dsi   total:243  pass:216  dwarn:0   dfail:0   fail:0   skip:26 
fi-bxt-j4205 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:513s
fi-byt-j1900 total:285  pass:250  dwarn:0   dfail:0   fail:0   skip:35  
time:520s
fi-byt-n2820 total:285  pass:246  dwarn:0   dfail:0   fail:0   skip:39  
time:507s
fi-cfl-8700k total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:411s
fi-cfl-s3total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:561s
fi-cfl-u total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:515s
fi-cnl-y3total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:585s
fi-elk-e7500 total:285  pass:226  dwarn:0   dfail:0   fail:0   skip:59  
time:422s
fi-gdg-551   total:285  pass:177  dwarn:0   dfail:0   fail:0   skip:108 
time:315s
fi-glk-1 total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:535s
fi-glk-j4005 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:483s
fi-hsw-4770  total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:408s
fi-ilk-650   total:285  pass:225  dwarn:0   dfail:0   fail:0   skip:60  
time:421s
fi-ivb-3520m total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:474s
fi-ivb-3770  total:285  pass:252  dwarn:0   dfail:0   fail:0   skip:33  
time:437s
fi-kbl-7500u total:285  pass:260  dwarn:1   dfail:0   fail:0   skip:24  
time:473s
fi-kbl-7567u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:464s
fi-kbl-r total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:505s
fi-pnv-d510  total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  
time:672s
fi-skl-6260u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:448s
fi-skl-6600u total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:534s
fi-skl-6700k2total:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:505s
fi-skl-6770hqtotal:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:491s
fi-skl-guc   total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:432s
fi-skl-gvtdvmtotal:285  pass:262  dwarn:0   dfail:0   fail:0   skip:23  
time:444s
fi-snb-2520m total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:576s
fi-snb-2600  total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:404s

617cdf0bd4fd2cb0dcc64ddf07fbb56572ba800a drm-tip: 2018y-04m-09d-19h-55m-54s UTC 
integration manifest
9f8948d7bfa4 HAX enable guc for CI
c17662cc72f9 drm/i915: Add code to accept valid locked WOPCM register values
8cd29217af34 drm/i915: Always set HUC_LOADING_AGENT_GUC bit in WOPCM offset 
register
79d7faa4b092 drm/i915: Always do WOPCM partitioning based on real firmware sizes

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8649/issues.html
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v4] drm/i915: Enable edp psr error interrupts on hsw (rev3)

[Patchwork]

== Series Details ==

Series: series starting with [v4] drm/i915: Enable edp psr error interrupts on 
hsw (rev3)
URL   : https://patchwork.freedesktop.org/series/41095/
State : success

== Summary ==

Series 41095v3 series starting with [v4] drm/i915: Enable edp psr error 
interrupts on hsw
https://patchwork.freedesktop.org/api/1.0/series/41095/revisions/3/mbox/

 Known issues:

Test gem_exec_suspend:
Subgroup basic-s3:
dmesg-warn -> PASS   (fi-glk-j4005) fdo#103359
Test kms_flip:
Subgroup basic-flip-vs-wf_vblank:
fail   -> PASS   (fi-glk-j4005) fdo#100368

fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368

fi-bdw-5557u total:285  pass:264  dwarn:0   dfail:0   fail:0   skip:21  
time:432s
fi-bdw-gvtdvmtotal:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:445s
fi-blb-e6850 total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  
time:382s
fi-bsw-n3050 total:285  pass:239  dwarn:0   dfail:0   fail:0   skip:46  
time:543s
fi-bwr-2160  total:285  pass:180  dwarn:0   dfail:0   fail:0   skip:105 
time:298s
fi-bxt-dsi   total:285  pass:255  dwarn:0   dfail:0   fail:0   skip:30  
time:519s
fi-bxt-j4205 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:519s
fi-byt-j1900 total:285  pass:250  dwarn:0   dfail:0   fail:0   skip:35  
time:522s
fi-byt-n2820 total:285  pass:246  dwarn:0   dfail:0   fail:0   skip:39  
time:509s
fi-cfl-8700k total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:413s
fi-cfl-s3total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:559s
fi-cfl-u total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:510s
fi-cnl-y3total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:584s
fi-elk-e7500 total:285  pass:226  dwarn:0   dfail:0   fail:0   skip:59  
time:424s
fi-gdg-551   total:285  pass:176  dwarn:0   dfail:0   fail:1   skip:108 
time:317s
fi-glk-1 total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:543s
fi-glk-j4005 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:485s
fi-hsw-4770  total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:406s
fi-ilk-650   total:285  pass:225  dwarn:0   dfail:0   fail:0   skip:60  
time:425s
fi-ivb-3520m total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:471s
fi-ivb-3770  total:285  pass:252  dwarn:0   dfail:0   fail:0   skip:33  
time:443s
fi-kbl-7500u total:285  pass:260  dwarn:1   dfail:0   fail:0   skip:24  
time:477s
fi-kbl-7567u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:465s
fi-kbl-r total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:511s
fi-pnv-d510  total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  
time:671s
fi-skl-6260u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:444s
fi-skl-6600u total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:534s
fi-skl-6700k2total:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:508s
fi-skl-6770hqtotal:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:511s
fi-skl-guc   total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:427s
fi-skl-gvtdvmtotal:285  pass:262  dwarn:0   dfail:0   fail:0   skip:23  
time:443s
fi-snb-2520m total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:586s
fi-snb-2600  total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:399s

617cdf0bd4fd2cb0dcc64ddf07fbb56572ba800a drm-tip: 2018y-04m-09d-19h-55m-54s UTC 
integration manifest
d8186b823b62 drm/i915/psr: Timestamps for PSR entry and exit interrupts.
003ec0005027 drm/i915/psr: Control PSR interrupts via debugfs
7fdf2eed9ed4 drm/i915: Enable edp psr error interrupts on bdw+
0a22dbbae8f8 drm/i915: Enable edp psr error interrupts on hsw

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8648/issues.html
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v4] drm/i915: Enable edp psr error interrupts on hsw (rev3)

[Patchwork]

== Series Details ==

Series: series starting with [v4] drm/i915: Enable edp psr error interrupts on 
hsw (rev3)
URL   : https://patchwork.freedesktop.org/series/41095/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
0a22dbbae8f8 drm/i915: Enable edp psr error interrupts on hsw
-:111: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#111: FILE: drivers/gpu/drm/i915/i915_reg.h:4032:
+#define   EDP_PSR_ERROR(1<<2)
  ^

-:112: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#112: FILE: drivers/gpu/drm/i915/i915_reg.h:4033:
+#define   EDP_PSR_POST_EXIT(1<<1)
  ^

-:113: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#113: FILE: drivers/gpu/drm/i915/i915_reg.h:4034:
+#define   EDP_PSR_PRE_ENTRY(1<<0)
  ^

-:122: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#122: FILE: drivers/gpu/drm/i915/i915_reg.h:6847:
+#define DE_EDP_PSR_INT_HSW (1<<19)
  ^

total: 0 errors, 0 warnings, 4 checks, 78 lines checked
7fdf2eed9ed4 drm/i915: Enable edp psr error interrupts on bdw+
-:159: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in 
parentheses
#159: FILE: drivers/gpu/drm/i915/intel_display.h:221:
+#define for_each_cpu_transcoder_masked(__dev_priv, __t, __mask) \
+   for ((__t) = 0; (__t) < I915_MAX_TRANSCODERS; (__t)++)  \
+   for_each_if ((__mask) & (1 << (__t)))

-:159: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__t' - possible 
side-effects?
#159: FILE: drivers/gpu/drm/i915/intel_display.h:221:
+#define for_each_cpu_transcoder_masked(__dev_priv, __t, __mask) \
+   for ((__t) = 0; (__t) < I915_MAX_TRANSCODERS; (__t)++)  \
+   for_each_if ((__mask) & (1 << (__t)))

-:160: CHECK:SPACING: No space is necessary after a cast
#160: FILE: drivers/gpu/drm/i915/intel_display.h:222:
+   for ((__t) = 0; (__t) < I915_MAX_TRANSCODERS; (__t)++)  \

-:161: WARNING:SPACING: space prohibited between function name and open 
parenthesis '('
#161: FILE: drivers/gpu/drm/i915/intel_display.h:223:
+   for_each_if ((__mask) & (1 << (__t)))

total: 1 errors, 1 warnings, 2 checks, 123 lines checked
003ec0005027 drm/i915/psr: Control PSR interrupts via debugfs
d8186b823b62 drm/i915/psr: Timestamps for PSR entry and exit interrupts.

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[Intel-gfx] [PATCH v3 2/4] drm/i915: Always set HUC_LOADING_AGENT_GUC bit in WOPCM offset register

[Jackie Li]

The enable_guc modparam is used to enable/disable GuC/HuC FW uploading
dynamcially during i915 module loading. If WOPCM offset register was locked
without having HUC_LOADING_AGENT_GUC bit set to 1, the module reloading
with both GuC and HuC FW will fail since we need to set this bit to 1 for
HuC FW uploading.

Since HUC_LOADING_AGENT_GUC bit has no impact on GuC FW uploading, this
patch updates the register updating code to make sure the WOPCM offset
register is always locked with HUC_LOADING_AGENT_GUC bit set to 1 which
will guarantee successful uploading of both GuC and HuC FW. We will further
take care of the locked values in the following enhancement patch.

Signed-off-by: Jackie Li 
Cc: Michal Wajdeczko 
Cc: Sagar Arun Kamble 
Cc: Michal Winiarski 
Cc: John Spotswood 
Cc: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/intel_wopcm.c | 8 +++-
 1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_wopcm.c 
b/drivers/gpu/drm/i915/intel_wopcm.c
index 74bf76f..b1c08ca 100644
--- a/drivers/gpu/drm/i915/intel_wopcm.c
+++ b/drivers/gpu/drm/i915/intel_wopcm.c
@@ -238,8 +238,6 @@ static inline int write_and_verify(struct drm_i915_private 
*dev_priv,
 int intel_wopcm_init_hw(struct intel_wopcm *wopcm)
 {
struct drm_i915_private *dev_priv = wopcm_to_i915(wopcm);
-   u32 huc_agent;
-   u32 mask;
int err;
 
if (!USES_GUC(dev_priv))
@@ -255,10 +253,10 @@ int intel_wopcm_init_hw(struct intel_wopcm *wopcm)
if (err)
goto err_out;
 
-   huc_agent = USES_HUC(dev_priv) ? HUC_LOADING_AGENT_GUC : 0;
-   mask = GUC_WOPCM_OFFSET_MASK | GUC_WOPCM_OFFSET_VALID | huc_agent;
err = write_and_verify(dev_priv, DMA_GUC_WOPCM_OFFSET,
-  wopcm->guc.base | huc_agent, mask,
+  wopcm->guc.base | HUC_LOADING_AGENT_GUC,
+  GUC_WOPCM_OFFSET_MASK | HUC_LOADING_AGENT_GUC |
+  GUC_WOPCM_OFFSET_VALID,
   GUC_WOPCM_OFFSET_VALID);
if (err)
goto err_out;
-- 
2.7.4

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[Intel-gfx] [PATCH v3 3/4] drm/i915: Add code to accept valid locked WOPCM register values

[Jackie Li]

In current code, we only compare the locked WOPCM register values with the
calculated values. However, we can continue loading GuC/HuC firmware if the
locked (or partially locked) values were valid for current GuC/HuC firmware
sizes.

This patch added a new code path to verify whether the locked register
values can be used for GuC/HuC firmware loading, it will recalculate the
verify the new values if these registers were partially locked, so that we
won't fail the GuC/HuC firmware loading even if the locked register values
are different from the calculated ones.

v2:
 - Update WOPCM register only if it's not locked

Signed-off-by: Jackie Li 
Cc: Michal Wajdeczko 
Cc: Sagar Arun Kamble 
Cc: Michal Winiarski 
Cc: John Spotswood 
Cc: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/intel_wopcm.c | 217 +++--
 1 file changed, 185 insertions(+), 32 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_wopcm.c 
b/drivers/gpu/drm/i915/intel_wopcm.c
index b1c08ca..fa8d2be 100644
--- a/drivers/gpu/drm/i915/intel_wopcm.c
+++ b/drivers/gpu/drm/i915/intel_wopcm.c
@@ -140,6 +140,53 @@ static inline int check_hw_restriction(struct 
drm_i915_private *i915,
return err;
 }
 
+static inline u32 calculate_min_guc_wopcm_base(u32 huc_fw_size)
+{
+   return ALIGN(huc_fw_size + WOPCM_RESERVED_SIZE,
+GUC_WOPCM_OFFSET_ALIGNMENT);
+}
+
+static inline u32 calculate_min_guc_wopcm_size(u32 guc_fw_size)
+{
+   return guc_fw_size + GUC_WOPCM_RESERVED + GUC_WOPCM_STACK_RESERVED;
+}
+
+static inline int calculate_max_guc_wopcm_size(struct intel_wopcm *wopcm,
+  u32 guc_wopcm_base,
+  u32 *guc_wopcm_size)
+{
+   struct drm_i915_private *i915 = wopcm_to_i915(wopcm);
+   u32 ctx_rsvd = context_reserved_size(i915);
+
+   if (guc_wopcm_base >= wopcm->size ||
+   (guc_wopcm_base + ctx_rsvd) >= wopcm->size) {
+   DRM_ERROR("GuC WOPCM base (%uKiB) is too big.\n",
+ guc_wopcm_base / 1024);
+   return -E2BIG;
+   }
+
+   *guc_wopcm_size =
+   (wopcm->size - guc_wopcm_base - ctx_rsvd) & GUC_WOPCM_SIZE_MASK;
+
+   return 0;
+}
+
+static inline int verify_calculated_values(struct drm_i915_private *i915,
+  u32 guc_fw_size, u32 huc_fw_size,
+  u32 guc_wopcm_base,
+  u32 guc_wopcm_size)
+{
+   if (guc_wopcm_size < calculate_min_guc_wopcm_size(guc_fw_size)) {
+   DRM_ERROR("Need %uKiB WOPCM for GuC FW, %uKiB available.\n",
+ calculate_min_guc_wopcm_size(guc_fw_size),
+ guc_wopcm_size / 1024);
+   return -E2BIG;
+   }
+
+   return check_hw_restriction(i915, guc_wopcm_base, guc_wopcm_size,
+   huc_fw_size);
+}
+
 /**
  * intel_wopcm_init() - Initialize the WOPCM structure.
  * @wopcm: pointer to intel_wopcm.
@@ -157,10 +204,8 @@ int intel_wopcm_init(struct intel_wopcm *wopcm)
struct drm_i915_private *i915 = wopcm_to_i915(wopcm);
u32 guc_fw_size = intel_uc_fw_get_upload_size(>guc.fw);
u32 huc_fw_size = intel_uc_fw_get_upload_size(>huc.fw);
-   u32 ctx_rsvd = context_reserved_size(i915);
u32 guc_wopcm_base;
u32 guc_wopcm_size;
-   u32 guc_wopcm_rsvd;
int err;
 
GEM_BUG_ON(!wopcm->size);
@@ -177,35 +222,121 @@ int intel_wopcm_init(struct intel_wopcm *wopcm)
return -E2BIG;
}
 
-   guc_wopcm_base = ALIGN(huc_fw_size + WOPCM_RESERVED_SIZE,
-  GUC_WOPCM_OFFSET_ALIGNMENT);
-   if ((guc_wopcm_base + ctx_rsvd) >= wopcm->size) {
-   DRM_ERROR("GuC WOPCM base (%uKiB) is too big.\n",
- guc_wopcm_base / 1024);
+   guc_wopcm_base = calculate_min_guc_wopcm_base(huc_fw_size);
+   err = calculate_max_guc_wopcm_size(wopcm, guc_wopcm_base,
+  _wopcm_size);
+   if (err)
+   return err;
+
+   DRM_DEBUG_DRIVER("Calculated GuC WOPCM Region: [%uKiB, %uKiB)\n",
+guc_wopcm_base / 1024,
+(guc_wopcm_base + guc_wopcm_size) / 1024);
+
+   err = verify_calculated_values(i915, guc_fw_size, huc_fw_size,
+  guc_wopcm_base, guc_wopcm_size);
+   if (err)
+   return err;
+
+   wopcm->guc.base = guc_wopcm_base;
+   wopcm->guc.size = guc_wopcm_size;
+
+   return 0;
+}
+
+static inline int verify_locked_values(struct intel_wopcm *wopcm,
+  u32 guc_wopcm_base, u32 guc_wopcm_size)
+{
+   

[Intel-gfx] [PATCH v3 4/4] HAX enable guc for CI

[Jackie Li]

Signed-off-by: Jackie Li 
---
 drivers/gpu/drm/i915/i915_params.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_params.h 
b/drivers/gpu/drm/i915/i915_params.h
index c963603..53037b5 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -47,7 +47,7 @@ struct drm_printer;
param(int, disable_power_well, -1) \
param(int, enable_ips, 1) \
param(int, invert_brightness, 0) \
-   param(int, enable_guc, 0) \
+   param(int, enable_guc, -1) \
param(int, guc_log_level, -1) \
param(char *, guc_firmware_path, NULL) \
param(char *, huc_firmware_path, NULL) \
-- 
2.7.4

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[Intel-gfx] [PATCH v3 1/4] drm/i915: Always do WOPCM partitioning based on real firmware sizes

[Jackie Li]

After enabled the WOPCM write-once registers locking status checking,
reloading of the i915 module will fail with modparam enable_guc set to 3
(enable GuC and HuC firmware loading) if the module was originally loaded
with enable_guc set to 1 (only enable GuC firmware loading). This is
because WOPCM registers were updated and locked without considering the HuC
FW size. Since we need both GuC and HuC FW sizes to determine the final
layout of WOPCM, we should always calculate the WOPCM layout based on the
actual sizes of the GuC and HuC firmware available for a specific platform
if we need continue to support enable/disable HuC FW loading dynamically
with enable_guc modparam.

This patch splits uC firmware fetching into two stages. First stage is to
fetch the firmware image and verify the firmware header. uC firmware will
be marked as verified and this will make FW info available for following
WOPCM layout calculation. The second stage is to create a GEM object and
copy the FW data into the created GEM object which will only be available
when GuC/HuC loading is enabled by enable_guc modparam. This will guarantee
that the WOPCM layout will be always be calculated correctly without making
any assumptions to the GuC and HuC firmware sizes.

v3:
 - Rebase

Signed-off-by: Jackie Li 
Cc: Michal Wajdeczko 
Cc: Sagar Arun Kamble 
Cc: Michal Winiarski 
Cc: John Spotswood 
Cc: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/intel_uc.c| 14 --
 drivers/gpu/drm/i915/intel_uc_fw.c | 31 ---
 drivers/gpu/drm/i915/intel_uc_fw.h |  7 +--
 3 files changed, 29 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 1cffaf7..73b8f6c 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -172,11 +172,8 @@ void intel_uc_init_early(struct drm_i915_private *i915)
 
sanitize_options_early(i915);
 
-   if (USES_GUC(i915))
-   intel_uc_fw_fetch(i915, >fw);
-
-   if (USES_HUC(i915))
-   intel_uc_fw_fetch(i915, >fw);
+   intel_uc_fw_fetch(i915, >fw, USES_GUC(i915));
+   intel_uc_fw_fetch(i915, >fw, USES_HUC(i915));
 }
 
 void intel_uc_cleanup_early(struct drm_i915_private *i915)
@@ -184,11 +181,8 @@ void intel_uc_cleanup_early(struct drm_i915_private *i915)
struct intel_guc *guc = >guc;
struct intel_huc *huc = >huc;
 
-   if (USES_HUC(i915))
-   intel_uc_fw_fini(>fw);
-
-   if (USES_GUC(i915))
-   intel_uc_fw_fini(>fw);
+   intel_uc_fw_fini(>fw);
+   intel_uc_fw_fini(>fw);
 
guc_free_load_err_log(guc);
 }
diff --git a/drivers/gpu/drm/i915/intel_uc_fw.c 
b/drivers/gpu/drm/i915/intel_uc_fw.c
index 6e8e0b5..a9cb900 100644
--- a/drivers/gpu/drm/i915/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/intel_uc_fw.c
@@ -33,11 +33,13 @@
  *
  * @dev_priv: device private
  * @uc_fw: uC firmware
+ * @copy_to_obj: whether fetch uC firmware into GEM object or not
  *
- * Fetch uC firmware into GEM obj.
+ * Fetch and verify uC firmware and copy firmware data into GEM object if
+ * @copy_to_obj is true.
  */
 void intel_uc_fw_fetch(struct drm_i915_private *dev_priv,
-  struct intel_uc_fw *uc_fw)
+  struct intel_uc_fw *uc_fw, bool copy_to_obj)
 {
struct pci_dev *pdev = dev_priv->drm.pdev;
struct drm_i915_gem_object *obj;
@@ -154,17 +156,24 @@ void intel_uc_fw_fetch(struct drm_i915_private *dev_priv,
goto fail;
}
 
-   obj = i915_gem_object_create_from_data(dev_priv, fw->data, fw->size);
-   if (IS_ERR(obj)) {
-   err = PTR_ERR(obj);
-   DRM_DEBUG_DRIVER("%s fw object_create err=%d\n",
-intel_uc_fw_type_repr(uc_fw->type), err);
-   goto fail;
+   uc_fw->size = fw->size;
+   uc_fw->fetch_status = INTEL_UC_FIRMWARE_VERIFIED;
+
+   if (copy_to_obj) {
+   obj = i915_gem_object_create_from_data(dev_priv, fw->data,
+  fw->size);
+   if (IS_ERR(obj)) {
+   err = PTR_ERR(obj);
+   DRM_DEBUG_DRIVER("%s fw object_create err=%d\n",
+intel_uc_fw_type_repr(uc_fw->type),
+err);
+   goto fail;
+   }
+
+   uc_fw->obj = obj;
+   uc_fw->fetch_status = INTEL_UC_FIRMWARE_SUCCESS;
}
 
-   uc_fw->obj = obj;
-   uc_fw->size = fw->size;
-   uc_fw->fetch_status = INTEL_UC_FIRMWARE_SUCCESS;
DRM_DEBUG_DRIVER("%s fw fetch %s\n",
 intel_uc_fw_type_repr(uc_fw->type),
 

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] drm/i915/guc: Check that the breadcrumb irq is enabled

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915/guc: Check that the breadcrumb irq 
is enabled
URL   : https://patchwork.freedesktop.org/series/41396/
State : failure

== Summary ==

 Possible new issues:

Test gem_eio:
Subgroup execbuf:
pass   -> INCOMPLETE (shard-apl)
Subgroup throttle:
pass   -> INCOMPLETE (shard-apl)
Test kms_frontbuffer_tracking:
Subgroup fbc-rgb565-draw-mmap-gtt:
pass   -> FAIL   (shard-apl)
Test perf:
Subgroup gen8-unprivileged-single-ctx-counters:
pass   -> FAIL   (shard-apl)

 Known issues:

Test drv_missed_irq:
pass   -> SKIP   (shard-apl) fdo#103199
Test drv_selftest:
Subgroup live_gtt:
pass   -> INCOMPLETE (shard-apl) fdo#103927
Test kms_flip:
Subgroup 2x-flip-vs-expired-vblank-interruptible:
fail   -> PASS   (shard-hsw) fdo#102887

fdo#103199 https://bugs.freedesktop.org/show_bug.cgi?id=103199
fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887

shard-apltotal:2589 pass:1758 dwarn:1   dfail:0   fail:10  skip:816 
time:11770s
shard-hswtotal:2680 pass:1786 dwarn:1   dfail:0   fail:1   skip:891 
time:11424s
Blacklisted hosts:
shard-kbltotal:2483 pass:1788 dwarn:2   dfail:0   fail:8   skip:680 
time:8212s
shard-snbtotal:2680 pass:1377 dwarn:1   dfail:0   fail:3   skip:1299 
time:6983s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8647/shards.html
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Re: [Intel-gfx] [PATCH 3/8] drm/i915/icl: add basic support for the ICL clocks

[James Ausmus]

On Wed, Mar 28, 2018 at 02:57:58PM -0700, Paulo Zanoni wrote:
> This commit introduces the definitions for the ICL clocks and adds the
> basic functions to the shared DPLL framework. It adds code for the
> Enable and Disable sequences for some PLLs, but it does not have the
> code to compute the actual PLL values, which are marked as TODO
> comments and should be introduced as separate commits.
> 
> Special thanks to James Ausmus for investigating and fixing a bug with
> the placement of icl_unmap_plls_to_ports() function.
> 
> v2:
>  - Rebase around dpll_lock changes.
> v3:
>  - The spec now says what the timeouts should be.
>  - Touch DPCLKA_CFGCR0_ICL at the appropriate time so we don't freeze
>the machine.
>  - Checkpatch found a white space problem.
>  - Small adjustments before upstreaming.
> v4:
>  - Move the ICL checks out of the *map_plls_to_ports() functions
>   (James)
>  - Add extra encoder check (James)
>  - Call icl_unmap_plls_to_ports() later (James)
> v5:
>  - Rebase after the pll struct changes.
> 
> Cc: James Ausmus 
> Signed-off-by: Paulo Zanoni 
> ---
>  drivers/gpu/drm/i915/i915_debugfs.c   |  22 +++
>  drivers/gpu/drm/i915/intel_ddi.c  |  98 ++-
>  drivers/gpu/drm/i915/intel_display.c  |  16 ++
>  drivers/gpu/drm/i915/intel_dpll_mgr.c | 312 
> +-
>  drivers/gpu/drm/i915/intel_dpll_mgr.h |  41 +
>  drivers/gpu/drm/i915/intel_drv.h  |   6 +
>  6 files changed, 490 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index ff90577da450..43a805c39b0a 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -3296,6 +3296,28 @@ static int i915_shared_dplls_info(struct seq_file *m, 
> void *unused)
>   seq_printf(m, " fp0: 0x%08x\n", pll->state.hw_state.fp0);
>   seq_printf(m, " fp1: 0x%08x\n", pll->state.hw_state.fp1);
>   seq_printf(m, " wrpll:   0x%08x\n", pll->state.hw_state.wrpll);
> + seq_printf(m, " cfgcr0:  0x%08x\n", pll->state.hw_state.cfgcr0);
> + seq_printf(m, " cfgcr1:  0x%08x\n", pll->state.hw_state.cfgcr1);
> + seq_printf(m, " mg_refclkin_ctl:0x%08x\n",
> +pll->state.hw_state.mg_refclkin_ctl);
> + seq_printf(m, " mg_clktop2_coreclkctl1: 0x%08x\n",
> +pll->state.hw_state.mg_clktop2_coreclkctl1);
> + seq_printf(m, " mg_clktop2_hsclkctl:0x%08x\n",
> +pll->state.hw_state.mg_clktop2_hsclkctl);
> + seq_printf(m, " mg_pll_div0:  0x%08x\n",
> +pll->state.hw_state.mg_pll_div0);
> + seq_printf(m, " mg_pll_div1:  0x%08x\n",
> +pll->state.hw_state.mg_pll_div1);
> + seq_printf(m, " mg_pll_lf:0x%08x\n",
> +pll->state.hw_state.mg_pll_lf);
> + seq_printf(m, " mg_pll_frac_lock: 0x%08x\n",
> +pll->state.hw_state.mg_pll_frac_lock);
> + seq_printf(m, " mg_pll_ssc:   0x%08x\n",
> +pll->state.hw_state.mg_pll_ssc);
> + seq_printf(m, " mg_pll_bias:  0x%08x\n",
> +pll->state.hw_state.mg_pll_bias);
> + seq_printf(m, " mg_pll_tdc_coldst_bias: 0x%08x\n",
> +pll->state.hw_state.mg_pll_tdc_coldst_bias);
>   }
>   drm_modeset_unlock_all(dev);
>  
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c 
> b/drivers/gpu/drm/i915/intel_ddi.c
> index a6672a9abd85..10223ffcceab 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1013,6 +1013,25 @@ static uint32_t hsw_pll_to_ddi_pll_sel(const struct 
> intel_shared_dpll *pll)
>   }
>  }
>  
> +static uint32_t icl_pll_to_ddi_pll_sel(struct intel_encoder *encoder,
> +const struct intel_shared_dpll *pll)
> +{
> + const enum intel_dpll_id id = pll->info->id;
> +
> + switch (id) {
> + default:
> + MISSING_CASE(id);
> + case DPLL_ID_ICL_DPLL0:
> + case DPLL_ID_ICL_DPLL1:
> + return DDI_CLK_SEL_NONE;
> + case DPLL_ID_ICL_MGPLL1:
> + case DPLL_ID_ICL_MGPLL2:
> + case DPLL_ID_ICL_MGPLL3:
> + case DPLL_ID_ICL_MGPLL4:
> + return DDI_CLK_SEL_MG;
> + }
> +}
> +
>  /* Starting with Haswell, different DDI ports can work in FDI mode for
>   * connection to the PCH-located connectors. For this, it is necessary to 
> train
>   * both the DDI port and PCH receiver for the desired DDI buffer settings.
> @@ -2234,6 +2253,69 @@ uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
>   return DDI_BUF_TRANS_SELECT(level);
>  }
>  
> +void icl_map_plls_to_ports(struct drm_crtc *crtc,
> +struct intel_crtc_state *crtc_state,
> +

Re: [Intel-gfx] [PATCH] drm/i915/audio: Fix audio detection issue on GLK

[Kumar, Abhay]

On 4/9/2018 4:20 PM, Pandiyan, Dhinakaran wrote:



On Mon, 2018-04-09 at 12:18 -0700, Kumar, Abhay wrote:

On 4/9/2018 12:10 PM, Rodrigo Vivi wrote:

On Mon, Apr 09, 2018 at 05:07:31PM +0300, Jani Nikula wrote:

On Sun, 08 Apr 2018, Gaurav K Singh  wrote:

On Geminilake, sometimes audio card is not getting
detected after reboot. This is a spurious issue happening on
Geminilake. HW codec and HD audio controller link was going
out of sync for which there was a fix in i915 driver but
was not getting invoked for GLK. Extending this fix to GLK as well.

Tested by Du,Wenkai on GLK board.

Signed-off-by: Gaurav K Singh 
---
   drivers/gpu/drm/i915/intel_audio.c | 3 ++-
   1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_audio.c 
b/drivers/gpu/drm/i915/intel_audio.c
index 656f6c931341..73b1e0b96f88 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -729,7 +729,8 @@ static void i915_audio_component_codec_wake_override(struct 
device *kdev,
struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
u32 tmp;
   
-	if (!IS_GEN9_BC(dev_priv) && !IS_BROXTON(dev_priv))

+   if (!IS_GEN9_BC(dev_priv) && !IS_BROXTON(dev_priv) &&
+   !IS_GEMINILAKE(dev_priv))

That could be written as

if (!IS_GEN9_BC(dev_priv) && !IS_GEN9_LP(dev_priv))

which in turn could just be written as

if (!IS_GEN9(dev_priv))

...but since GLK has gen 10 display, so I'm wondering if the same issue
will be present in gen 10 too, and whether this should just become

if (INTEL_GEN(dev_priv) < 9)

+1. I opened here to exactly add same comment.

I am checking with DINQ and without this patch for GLK it can enumerate
HDA codec. Ofcourse after cdclk fix.

How about the other way around? i.e., does codec enumeration work this
patch but without the cdclk change?
Nop. with DINQ we need to have cdclk change to make Codec detection 
work. With or without this patch.







BR,
Jani.




return;
   
   	i915_audio_component_get_power(kdev);

--
Jani Nikula, Intel Open Source Technology Center
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Re: [Intel-gfx] [PATCH] drm/i915/audio: Fix audio detection issue on GLK

[Dhinakaran Pandiyan]

On Mon, 2018-04-09 at 12:18 -0700, Kumar, Abhay wrote:
> 
> On 4/9/2018 12:10 PM, Rodrigo Vivi wrote:
> > On Mon, Apr 09, 2018 at 05:07:31PM +0300, Jani Nikula wrote:
> >> On Sun, 08 Apr 2018, Gaurav K Singh  wrote:
> >>> On Geminilake, sometimes audio card is not getting
> >>> detected after reboot. This is a spurious issue happening on
> >>> Geminilake. HW codec and HD audio controller link was going
> >>> out of sync for which there was a fix in i915 driver but
> >>> was not getting invoked for GLK. Extending this fix to GLK as well.
> >>>
> >>> Tested by Du,Wenkai on GLK board.
> >>>
> >>> Signed-off-by: Gaurav K Singh 
> >>> ---
> >>>   drivers/gpu/drm/i915/intel_audio.c | 3 ++-
> >>>   1 file changed, 2 insertions(+), 1 deletion(-)
> >>>
> >>> diff --git a/drivers/gpu/drm/i915/intel_audio.c 
> >>> b/drivers/gpu/drm/i915/intel_audio.c
> >>> index 656f6c931341..73b1e0b96f88 100644
> >>> --- a/drivers/gpu/drm/i915/intel_audio.c
> >>> +++ b/drivers/gpu/drm/i915/intel_audio.c
> >>> @@ -729,7 +729,8 @@ static void 
> >>> i915_audio_component_codec_wake_override(struct device *kdev,
> >>>   struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
> >>>   u32 tmp;
> >>>   
> >>> - if (!IS_GEN9_BC(dev_priv) && !IS_BROXTON(dev_priv))
> >>> + if (!IS_GEN9_BC(dev_priv) && !IS_BROXTON(dev_priv) &&
> >>> + !IS_GEMINILAKE(dev_priv))
> >> That could be written as
> >>
> >>if (!IS_GEN9_BC(dev_priv) && !IS_GEN9_LP(dev_priv))
> >>
> >> which in turn could just be written as
> >>
> >>if (!IS_GEN9(dev_priv))
> >>
> >> ...but since GLK has gen 10 display, so I'm wondering if the same issue
> >> will be present in gen 10 too, and whether this should just become
> >>
> >>if (INTEL_GEN(dev_priv) < 9)
> > +1. I opened here to exactly add same comment.
> I am checking with DINQ and without this patch for GLK it can enumerate 
> HDA codec. Ofcourse after cdclk fix.

How about the other way around? i.e., does codec enumeration work this
patch but without the cdclk change?



> >
> >> BR,
> >> Jani.
> >>
> >>
> >>
> >>>   return;
> >>>   
> >>>   i915_audio_component_get_power(kdev);
> >> -- 
> >> Jani Nikula, Intel Open Source Technology Center
> >> ___
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> >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > ___
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> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
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Re: [Intel-gfx] [PATCH v2] drm/i915: set minimum CD clock to twice the BCLK.

[Kumar, Abhay]

On 4/9/2018 3:33 AM, Ville Syrjälä wrote:

On Fri, Apr 06, 2018 at 04:47:08PM +0300, Jani Nikula wrote:

On Thu, 05 Apr 2018, Abhay Kumar  wrote:

In glk when device boots with 1366x768 panel, HDA codec doesn't comeup.
This result in no audio forever as cdclk is < 96Mhz.
This chagne will ensure CD clock to be twice of  BCLK.

In short, we can't poke around CDCLK like this. It needs a full modeset,
and it's non-trivial from the path you're calling this from.

I tried to cobble something together quickly:
git://github.com/vsyrjala/linux.git glk_cnl_cdclk_audio

Not tested at all, and I have no idea if my assumptions about
snd_hda_intel actually hold.

Hi Ville,

Tried your patch but as soon as it enters "glk_force_audio_cdclk" 
the device locks up and reboots.  waited for 30-40 times and it always 
reboot at same place.

It never reaches Chrome OS login screen.

Thanks.



I'm considering pushing the original patch [1], because we haven't come
up with working alternatives. Please confirm that the patch reliably
fixes the issue.

(Though I think if you boot with *all* outputs disabled, we'll choose
the lowest CDCLK possible regardless of the patch, reproducing the same
issue.)

What's the CDCLK frequency set by the BIOS/GOP at boot? There are no
logs with drm.debug=14 attached to the referenced bug.

I see that bspec says, "158.4 MHz CD (Display Audio enumeration and
playback OK)" but that's *not* twice the BCLK. I'm inclined to lean
towards 192 MHz min leading to max CDCLK on GLK.

BR,
Jani.

Hi Jani,
   Dynamic cdclk is disabled in BIOS/GOP hence gop makes it to highest 
clock i.e 316.8. Will attach logs with drm debug enabled in bug.

I am also inclined towards 192 which will make max cdclk..

Currently testing all scenario to confirm if patchset 1 fixes all issue 
or not. There was 4s delay issue during s0ix from audio which i 
specifically want to test.


Thanks.





[1] https://patchwork.freedesktop.org/patch/184778/




v2:
 - Address comment (Jani)
 - New design approach

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102937
Signed-off-by: Abhay Kumar 
---
  drivers/gpu/drm/i915/intel_audio.c | 33 ++---
  drivers/gpu/drm/i915/intel_cdclk.c | 21 +
  drivers/gpu/drm/i915/intel_drv.h   |  1 +
  3 files changed, 44 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_audio.c 
b/drivers/gpu/drm/i915/intel_audio.c
index 709d6ca68074..f7dd3d532e93 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -723,15 +723,37 @@ static void i915_audio_component_put_power(struct device 
*kdev)
intel_display_power_put(kdev_to_i915(kdev), POWER_DOMAIN_AUDIO);
  }
  
+/* Get CDCLK in kHz  */

+static int i915_audio_component_get_cdclk_freq(struct device *kdev)
+{
+   struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
+
+   if (WARN_ON_ONCE(!HAS_DDI(dev_priv)))
+   return -ENODEV;
+
+   return dev_priv->cdclk.hw.cdclk;
+}
+
  static void i915_audio_component_codec_wake_override(struct device *kdev,
 bool enable)
  {
struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
u32 tmp;
+   int current_cdclk;
  
  	if (!IS_GEN9_BC(dev_priv))

return;
  
+	current_cdclk = i915_audio_component_get_cdclk_freq(kdev);

+
+   /*
+* Before probing for HDA Codec we need to make sure
+* "The CD clock frequency must be at least twice
+* the frequency of the Azalia BCLK."
+*/
+   if (INTEL_GEN(dev_priv) >= 9 && current_cdclk <= 192000)
+   intel_cdclk_bump(dev_priv);
+
i915_audio_component_get_power(kdev);
  
  	/*

@@ -753,17 +775,6 @@ static void 
i915_audio_component_codec_wake_override(struct device *kdev,
i915_audio_component_put_power(kdev);
  }
  
-/* Get CDCLK in kHz  */

-static int i915_audio_component_get_cdclk_freq(struct device *kdev)
-{
-   struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
-
-   if (WARN_ON_ONCE(!HAS_DDI(dev_priv)))
-   return -ENODEV;
-
-   return dev_priv->cdclk.hw.cdclk;
-}
-
  /*
   * get the intel_encoder according to the parameter port and pipe
   * intel_encoder is saved by the index of pipe
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c 
b/drivers/gpu/drm/i915/intel_cdclk.c
index dc7db8a2caf8..9426e1b7badc 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -1516,6 +1516,27 @@ void bxt_init_cdclk(struct drm_i915_private *dev_priv)
  }
  
  /**

+ * intel_cdclk_bump - Increase cdclk to 2* BCLK
+ * @dev_priv: i915 device
+ *
+ * Increase CDCLK for GKL and CNL. This is done only
+ * during HDA codec probe.
+ */
+void intel_cdclk_bump(struct drm_i915_private *dev_priv)
+{
+   struct intel_cdclk_state cdclk_state;
+
+   cdclk_state = dev_priv->cdclk.hw;
+
+   if 

Re: [Intel-gfx] [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds

[Oscar Mateo]

On 4/9/2018 12:53 PM, Chris Wilson wrote:

Quoting Oscar Mateo (2018-04-06 23:24:57)

Inherit workarounds from previous platforms that are still valid for
Icelake.

Speaking of the workarounds, where do we stand with at least landing the
split out of init_workarounds_ring()?

Rebuilding the invariant wa_regs[] on every reset is annoying, and how
many of the general mmio need to be reemitted everytime? I would dearly
like to get the flow of the gt/context workarounds improved.
-Chris


I'm afraid we stand nowhere. The latest patches I sent were sidetracked 
by a conversation about where i915.rst should reside:


https://patchwork.freedesktop.org/patch/206937/
https://patchwork.freedesktop.org/patch/206557/

I can try once more, see if I am more lucky this time around?
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[Intel-gfx] ✗ Fi.CI.IGT: warning for drm/i915/pmu: check runtime resume vs pmu race

[Patchwork]

== Series Details ==

Series: drm/i915/pmu: check runtime resume vs pmu race
URL   : https://patchwork.freedesktop.org/series/41380/
State : warning

== Summary ==

 Possible new issues:

Test perf_pmu:
Subgroup rc6-runtime-pm:
pass   -> DMESG-WARN (shard-apl)
Subgroup rc6-runtime-pm-long:
pass   -> DMESG-WARN (shard-apl)

 Known issues:

Test kms_flip:
Subgroup 2x-flip-vs-expired-vblank-interruptible:
fail   -> PASS   (shard-hsw) fdo#102887
Test perf_pmu:
Subgroup rc6-runtime-pm-long:
pass   -> DMESG-WARN (shard-hsw) fdo#105010 +1

fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
fdo#105010 https://bugs.freedesktop.org/show_bug.cgi?id=105010

shard-apltotal:2680 pass:1833 dwarn:3   dfail:0   fail:7   skip:836 
time:12710s
shard-hswtotal:2680 pass:1784 dwarn:3   dfail:0   fail:1   skip:891 
time:11407s
Blacklisted hosts:
shard-snbtotal:2680 pass:1377 dwarn:1   dfail:0   fail:3   skip:1299 
time:6970s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8645/shards.html
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/guc: Check that the breadcrumb irq is enabled

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915/guc: Check that the breadcrumb irq 
is enabled
URL   : https://patchwork.freedesktop.org/series/41396/
State : success

== Summary ==

Series 41396v1 series starting with [1/2] drm/i915/guc: Check that the 
breadcrumb irq is enabled
https://patchwork.freedesktop.org/api/1.0/series/41396/revisions/1/mbox/

 Possible new issues:

Test gem_exec_gttfill:
Subgroup basic:
skip   -> PASS   (fi-pnv-d510)

 Known issues:

Test gem_mmap_gtt:
Subgroup basic-small-bo-tiledx:
fail   -> PASS   (fi-gdg-551) fdo#102575

fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575

fi-bdw-5557u total:285  pass:264  dwarn:0   dfail:0   fail:0   skip:21  
time:431s
fi-bdw-gvtdvmtotal:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:447s
fi-blb-e6850 total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  
time:384s
fi-bsw-n3050 total:285  pass:239  dwarn:0   dfail:0   fail:0   skip:46  
time:544s
fi-bwr-2160  total:285  pass:180  dwarn:0   dfail:0   fail:0   skip:105 
time:298s
fi-bxt-dsi   total:285  pass:255  dwarn:0   dfail:0   fail:0   skip:30  
time:522s
fi-bxt-j4205 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:515s
fi-byt-j1900 total:285  pass:250  dwarn:0   dfail:0   fail:0   skip:35  
time:524s
fi-byt-n2820 total:285  pass:246  dwarn:0   dfail:0   fail:0   skip:39  
time:512s
fi-cfl-8700k total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:417s
fi-cfl-s3total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:563s
fi-cfl-u total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:515s
fi-cnl-y3total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:579s
fi-elk-e7500 total:285  pass:226  dwarn:0   dfail:0   fail:0   skip:59  
time:425s
fi-gdg-551   total:285  pass:177  dwarn:0   dfail:0   fail:0   skip:108 
time:316s
fi-glk-1 total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:537s
fi-glk-j4005 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:485s
fi-hsw-4770  total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:403s
fi-ilk-650   total:285  pass:225  dwarn:0   dfail:0   fail:0   skip:60  
time:424s
fi-ivb-3520m total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:471s
fi-ivb-3770  total:285  pass:252  dwarn:0   dfail:0   fail:0   skip:33  
time:437s
fi-kbl-7500u total:285  pass:260  dwarn:1   dfail:0   fail:0   skip:24  
time:471s
fi-kbl-7567u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:463s
fi-kbl-r total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:510s
fi-pnv-d510  total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  
time:666s
fi-skl-6260u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:443s
fi-skl-6600u total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:532s
fi-skl-6700k2total:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:507s
fi-skl-6770hqtotal:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:514s
fi-skl-guc   total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:432s
fi-skl-gvtdvmtotal:285  pass:262  dwarn:0   dfail:0   fail:0   skip:23  
time:446s
fi-snb-2520m total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:602s
fi-snb-2600  total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:406s

1cda370ffded69ce8c5ffa4fba3564a952730b97 drm-tip: 2018y-04m-09d-14h-03m-58s UTC 
integration manifest
d4cb395ccc8c HAX:guc
2fc2ed95e6cd drm/i915/guc: Check that the breadcrumb irq is enabled

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8647/issues.html
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/guc: Check that the breadcrumb irq is enabled

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915/guc: Check that the breadcrumb irq 
is enabled
URL   : https://patchwork.freedesktop.org/series/41396/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
2fc2ed95e6cd drm/i915/guc: Check that the breadcrumb irq is enabled
d4cb395ccc8c HAX:guc
-:19: ERROR:MISSING_SIGN_OFF: Missing Signed-off-by: line(s)

total: 1 errors, 0 warnings, 0 checks, 8 lines checked

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Re: [Intel-gfx] [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds

[Chris Wilson]

Quoting Oscar Mateo (2018-04-06 23:24:57)
> Inherit workarounds from previous platforms that are still valid for
> Icelake.

Speaking of the workarounds, where do we stand with at least landing the
split out of init_workarounds_ring()?

Rebuilding the invariant wa_regs[] on every reset is annoying, and how
many of the general mmio need to be reemitted everytime? I would dearly
like to get the flow of the gt/context workarounds improved.
-Chris
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Re: [Intel-gfx] [PATCH] drm/i915: Add debugfs file to clear FIFO underruns.

[Rodrigo Vivi]

On Wed, Mar 28, 2018 at 06:20:26PM +0200, Maarten Lankhorst wrote:
> Op 28-03-18 om 12:21 schreef Jani Nikula:
> > On Wed, 28 Mar 2018, Maarten Lankhorst  
> > wrote:
> >> Adding a i915_fifo_underrun_reset debugfs file will make it possible
> >> for IGT tests to clear FIFO underrun fallout at the start of each
> >> subtest, and make re-enable FBC so tests always have maximum exposure
> >> to features used by IGT. FIFO underruns and FBC bugs will no longer
> >> hide when an earlier subtests disables both.
> >>
> >> Signed-off-by: Maarten Lankhorst 
> >> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105685
> >> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105681
> > FWIW, ack on the idea, didn't look at the implementation.
> Well I had a NV12 test that produced FIFO underruns, did some quick testing 
> against the i915_fifo_underrun_reset file and manually writing it does reset 
> FIFO underruns.
> Immediately after i915_fbc_status still reads "FBC disabled: underrun 
> detected", but this is cleared by the next atomic commit. So I think it 
> works, and can be used for igt in the way I wrote it.

What about a error message change on fbc_status to reflect this temporary state?
Just to avoid later confusion on expectation.

But the approach and code look sane for me, so anyways:

Reviewed-by: Rodrigo Vivi 

> 
> ~Maarten
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[Intel-gfx] [PATCH 2/2] HAX:guc

[Chris Wilson]

---
 drivers/gpu/drm/i915/i915_params.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_params.h 
b/drivers/gpu/drm/i915/i915_params.h
index c96360398072..53037b5eff22 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -47,7 +47,7 @@ struct drm_printer;
param(int, disable_power_well, -1) \
param(int, enable_ips, 1) \
param(int, invert_brightness, 0) \
-   param(int, enable_guc, 0) \
+   param(int, enable_guc, -1) \
param(int, guc_log_level, -1) \
param(char *, guc_firmware_path, NULL) \
param(char *, huc_firmware_path, NULL) \
-- 
2.17.0

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[Intel-gfx] [PATCH 1/2] drm/i915/guc: Check that the breadcrumb irq is enabled

[Chris Wilson]

Our execlists emulation for GuC requires use of the breadcrumb following
every request as a simulcrum for the context-switch interrupt, which we
then use to drive the submission tasklet. Therefore, when we unpark the
engine for use with the GuC, we pin the breadcrumb interrupt to keep it
enabled for the duration. This has to be remain so across all resets,
wedging and resume, so check we do have the irq enabled when we start
submitting requests to the GuC and on all submissions thereafter.

Signed-off-by: Chris Wilson 
Cc: Michal Wajdeczko 
Cc: Michał Winiarski 
---
 drivers/gpu/drm/i915/intel_guc_submission.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c 
b/drivers/gpu/drm/i915/intel_guc_submission.c
index 97121230656c..a7957b669b68 100644
--- a/drivers/gpu/drm/i915/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/intel_guc_submission.c
@@ -758,6 +758,8 @@ static void guc_submission_tasklet(unsigned long data)
struct execlist_port *port = execlists->port;
struct i915_request *rq;
 
+   GEM_BUG_ON(!READ_ONCE(engine->breadcrumbs.irq_enabled));
+
rq = port_request(port);
while (rq && i915_request_completed(rq)) {
trace_i915_request_out(rq);
-- 
2.17.0

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Re: [Intel-gfx] [PATCH] drm/i915/audio: Fix audio detection issue on GLK

[Kumar, Abhay]

On 4/9/2018 12:10 PM, Rodrigo Vivi wrote:

On Mon, Apr 09, 2018 at 05:07:31PM +0300, Jani Nikula wrote:

On Sun, 08 Apr 2018, Gaurav K Singh  wrote:

On Geminilake, sometimes audio card is not getting
detected after reboot. This is a spurious issue happening on
Geminilake. HW codec and HD audio controller link was going
out of sync for which there was a fix in i915 driver but
was not getting invoked for GLK. Extending this fix to GLK as well.

Tested by Du,Wenkai on GLK board.

Signed-off-by: Gaurav K Singh 
---
  drivers/gpu/drm/i915/intel_audio.c | 3 ++-
  1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_audio.c 
b/drivers/gpu/drm/i915/intel_audio.c
index 656f6c931341..73b1e0b96f88 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -729,7 +729,8 @@ static void i915_audio_component_codec_wake_override(struct 
device *kdev,
struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
u32 tmp;
  
-	if (!IS_GEN9_BC(dev_priv) && !IS_BROXTON(dev_priv))

+   if (!IS_GEN9_BC(dev_priv) && !IS_BROXTON(dev_priv) &&
+   !IS_GEMINILAKE(dev_priv))

That could be written as

if (!IS_GEN9_BC(dev_priv) && !IS_GEN9_LP(dev_priv))

which in turn could just be written as

if (!IS_GEN9(dev_priv))

...but since GLK has gen 10 display, so I'm wondering if the same issue
will be present in gen 10 too, and whether this should just become

if (INTEL_GEN(dev_priv) < 9)

+1. I opened here to exactly add same comment.
I am checking with DINQ and without this patch for GLK it can enumerate 
HDA codec. Ofcourse after cdclk fix.



BR,
Jani.




return;
  
  	i915_audio_component_get_power(kdev);

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Re: [Intel-gfx] [PATCH] drm/i915/psr: Chase psr.enabled only under the psr.lock

[Rodrigo Vivi]

On Sat, Apr 07, 2018 at 10:05:25AM +0100, Chris Wilson wrote:
> Quoting Rodrigo Vivi (2018-04-06 23:18:16)
> > On Fri, Apr 06, 2018 at 11:12:27AM -0700, Souza, Jose wrote:
> > > On Thu, 2018-04-05 at 12:49 +0100, Chris Wilson wrote:
> > > > +   struct drm_crtc *crtc =
> > > > +   dp_to_dig_port(intel_dp)->base.base.crtc;
> > 
> > I'm afraid that the issue is this pointer here. So this will only mask
> > the issue.
> > 
> > Should we maybe stash the pipe? :/
> 
> It's not that bad. pipe cannot change until after psr_disable is called,
> right? And psr_disable ensures that this worker is flushed. The current
> problem is just the coordination of cancelling the worker, where we may
> set psr.enabled to NULL right before the worker grabs it and
> dereferences it.
> 
> So if we lock until we have the pipe, we know that dereference chain is
> valid, and we know that psr_disable() cannot complete until we complete
> the wait. So the pipe remains valid until we return (so long as the pipe
> exists when we start).

hmm... it makes sense and I have no better suggestion actually.
So, as long it really fixes the regression we introduced:

Acked-by: Rodrigo Vivi 

> -Chris
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Re: [Intel-gfx] [PATCH] drm/i915/cnp: Properly handle VBT ddc pin out of bounds.

[Rodrigo Vivi]

On Mon, Apr 09, 2018 at 12:48:15PM +0300, Jani Nikula wrote:
> On Fri, 23 Mar 2018, Timo Aaltonen  wrote:
> > On 30.01.2018 00:12, Rodrigo Vivi wrote:
> >> On Mon, Jan 29, 2018 at 05:42:53AM +, Kai Heng Feng wrote:
> >>>
>  On 26 Jan 2018, at 6:25 AM, Rodrigo Vivi  wrote:
> 
>  If the table result is out of bounds on the array map
>  there is something really wrong with VBT pin so we don't
>  return that vbt_pin, but only return 0 instead.
> 
>  This basically reverts commit 'a8e6f3888b05 ("drm/i915/cnp:
>  Ignore VBT request for know invalid DDC pin.")'
> 
>  Also this properly fixes commit 9c3b2689d01f ("drm/i915/cnl:
>  Map VBT DDC Pin to BSpec DDC Pin.")
> 
>  v2: Do in a way that we don't break other platforms. (Jani)
> 
>  v3: Keep debug message (Jani)
> 
>  v4: Don't mess with 0 mapping was noticed by Jani and
> addressed with a simple solution suggested by Lucas
> that makes this even simpler.
> 
>  Fixes: a8e6f3888b05 ("drm/i915/cnp: Ignore VBT request for know invalid 
>  DDC pin.")
>  Fixes: 9c3b2689d01f ("drm/i915/cnl: Map VBT DDC Pin to BSpec DDC Pin.")
>  Cc: Radhakrishna Sripada 
>  Cc: Jani Nikula 
>  Cc: Kai Heng Feng 
>  Cc: Lucas De Marchi 
>  Suggested-by: Lucas De Marchi 
>  Signed-off-by: Rodrigo Vivi 
> >>>
> >>> Tested-by: Kai-Heng Feng 
> >> 
> >> merged. thanks for suggestions, reviews, tests and patience ;)
> >
> > Shouldn't this and
> >
> > drm/i915/cnp: Ignore VBT request for know invalid DDC pin.
> >
> > be cc:stable? Though they aren't even in 4.16 yet.
> 
> Apologies for nobody replying. The commits are in v4.16, and I've made a
> stable backport request for v4.15.

Ops, my bad. I'm sorry...
I had missed those.

Thank you very much Jani.

> 
> BR,
> Jani.
> 
> -- 
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Re: [Intel-gfx] [PATCH] drm/i915/audio: Fix audio detection issue on GLK

[Rodrigo Vivi]

On Mon, Apr 09, 2018 at 05:07:31PM +0300, Jani Nikula wrote:
> On Sun, 08 Apr 2018, Gaurav K Singh  wrote:
> > On Geminilake, sometimes audio card is not getting
> > detected after reboot. This is a spurious issue happening on
> > Geminilake. HW codec and HD audio controller link was going
> > out of sync for which there was a fix in i915 driver but
> > was not getting invoked for GLK. Extending this fix to GLK as well.
> >
> > Tested by Du,Wenkai on GLK board.
> >
> > Signed-off-by: Gaurav K Singh 
> > ---
> >  drivers/gpu/drm/i915/intel_audio.c | 3 ++-
> >  1 file changed, 2 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_audio.c 
> > b/drivers/gpu/drm/i915/intel_audio.c
> > index 656f6c931341..73b1e0b96f88 100644
> > --- a/drivers/gpu/drm/i915/intel_audio.c
> > +++ b/drivers/gpu/drm/i915/intel_audio.c
> > @@ -729,7 +729,8 @@ static void 
> > i915_audio_component_codec_wake_override(struct device *kdev,
> > struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
> > u32 tmp;
> >  
> > -   if (!IS_GEN9_BC(dev_priv) && !IS_BROXTON(dev_priv))
> > +   if (!IS_GEN9_BC(dev_priv) && !IS_BROXTON(dev_priv) &&
> > +   !IS_GEMINILAKE(dev_priv))
> 
> That could be written as
> 
>   if (!IS_GEN9_BC(dev_priv) && !IS_GEN9_LP(dev_priv))
> 
> which in turn could just be written as
> 
>   if (!IS_GEN9(dev_priv))
> 
> ...but since GLK has gen 10 display, so I'm wondering if the same issue
> will be present in gen 10 too, and whether this should just become
> 
>   if (INTEL_GEN(dev_priv) < 9)

+1. I opened here to exactly add same comment.

> 
> BR,
> Jani.
> 
> 
> 
> > return;
> >  
> > i915_audio_component_get_power(kdev);
> 
> -- 
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Enable display workaround 827 for all planes, v2.

[Patchwork]

== Series Details ==

Series: drm/i915: Enable display workaround 827 for all planes, v2.
URL   : https://patchwork.freedesktop.org/series/41371/
State : success

== Summary ==

 Known issues:

Test kms_flip:
Subgroup 2x-flip-vs-expired-vblank-interruptible:
fail   -> PASS   (shard-hsw) fdo#102887
Subgroup dpms-vs-vblank-race:
pass   -> FAIL   (shard-hsw) fdo#103060
Test kms_sysfs_edid_timing:
warn   -> PASS   (shard-apl) fdo#100047
Test perf:
Subgroup polling:
pass   -> INCOMPLETE (shard-hsw) fdo#102252

fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252

shard-apltotal:2680 pass:1836 dwarn:1   dfail:0   fail:7   skip:836 
time:12684s
shard-hswtotal:2679 pass:1783 dwarn:1   dfail:0   fail:2   skip:891 
time:10954s
Blacklisted hosts:
shard-kbltotal:2680 pass:1960 dwarn:1   dfail:0   fail:9   skip:710 
time:9209s
shard-snbtotal:2680 pass:1377 dwarn:1   dfail:0   fail:3   skip:1299 
time:6953s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8644/shards.html
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Re: [Intel-gfx] [PATCH 6/7] drm/i915/dp: abstract link config selection

[Manasi Navare]

On Mon, Apr 09, 2018 at 05:12:03PM +0300, Jani Nikula wrote:
> On Thu, 05 Apr 2018, Manasi Navare  wrote:
> > On Thu, Apr 05, 2018 at 05:39:04PM +0300, Jani Nikula wrote:
> >> For now, there's just the one link config selection, optimizing for slow
> >> and wide link. No functional changes.
> >> 
> >> Signed-off-by: Jani Nikula 
> >> ---
> >>  drivers/gpu/drm/i915/intel_dp.c | 81 
> >> +
> >>  1 file changed, 50 insertions(+), 31 deletions(-)
> >> 
> >> diff --git a/drivers/gpu/drm/i915/intel_dp.c 
> >> b/drivers/gpu/drm/i915/intel_dp.c
> >> index 3c5fbdf42b9b..c98626b3af65 100644
> >> --- a/drivers/gpu/drm/i915/intel_dp.c
> >> +++ b/drivers/gpu/drm/i915/intel_dp.c
> >> @@ -1704,6 +1704,42 @@ static bool intel_edp_compare_alt_mode(struct 
> >> drm_display_mode *m1,
> >>return bres;
> >>  }
> >>  
> >> +/* Optimize link config in order: max bpp, min clock, min lanes */
> >> +static bool
> >> +intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
> >> +struct intel_crtc_state *pipe_config,
> >> +const struct link_config_limits *limits)
> >> +{
> >> +  struct drm_display_mode *adjusted_mode = 
> >> _config->base.adjusted_mode;
> >> +  int bpp, clock, lane_count;
> >> +  int mode_rate, link_clock, link_avail;
> >> +
> >> +  for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
> >> +  mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
> >> + bpp);
> >> +
> >> +  for (clock = limits->min_clock; clock <= limits->max_clock; 
> >> clock++) {
> >> +  for (lane_count = limits->min_lane_count;
> >> +   lane_count <= limits->max_lane_count;
> >> +   lane_count <<= 1) {
> >> +  link_clock = intel_dp->common_rates[clock];
> >> +  link_avail = intel_dp_max_data_rate(link_clock,
> >> +  lane_count);
> >> +
> >> +  if (mode_rate <= link_avail) {
> >> +  pipe_config->lane_count = lane_count;
> >> +  pipe_config->pipe_bpp = bpp;
> >> +  pipe_config->port_clock = link_clock;
> >> +
> >> +  return true;
> >> +  }
> >> +  }
> >> +  }
> >> +  }
> >> +
> >> +  return false;
> >> +}
> >> +
> >>  static bool
> >>  intel_dp_compute_link_config(struct intel_encoder *encoder,
> >> struct intel_crtc_state *pipe_config)
> >> @@ -1711,8 +1747,6 @@ intel_dp_compute_link_config(struct intel_encoder 
> >> *encoder,
> >>struct drm_display_mode *adjusted_mode = 
> >> _config->base.adjusted_mode;
> >>struct intel_dp *intel_dp = enc_to_intel_dp(>base);
> >>struct link_config_limits limits;
> >> -  int bpp, clock, lane_count;
> >> -  int mode_rate, link_avail, link_clock;
> >>int common_len;
> >>  
> >>common_len = intel_dp_common_len_rate_limit(intel_dp,
> >> @@ -1766,37 +1800,22 @@ intel_dp_compute_link_config(struct intel_encoder 
> >> *encoder,
> >>  intel_dp->common_rates[limits.max_clock],
> >>  limits.max_bpp, adjusted_mode->crtc_clock);
> >>  
> >> -  for (bpp = limits.max_bpp; bpp >= limits.min_bpp; bpp -= 2 * 3) {
> >> -  mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
> >> - bpp);
> >> -
> >> -  for (clock = limits.min_clock; clock <= limits.max_clock; 
> >> clock++) {
> >> -  for (lane_count = limits.min_lane_count;
> >> -   lane_count <= limits.max_lane_count;
> >> -   lane_count <<= 1) {
> >> -
> >> -  link_clock = intel_dp->common_rates[clock];
> >> -  link_avail = intel_dp_max_data_rate(link_clock,
> >> -  lane_count);
> >> -
> >> -  if (mode_rate <= link_avail) {
> >> -  goto found;
> >> -  }
> >> -  }
> >> -  }
> >> -  }
> >> -
> >> -  return false;
> >> -
> >> -found:
> >> -  pipe_config->lane_count = lane_count;
> >> -  pipe_config->pipe_bpp = bpp;
> >> -  pipe_config->port_clock = intel_dp->common_rates[clock];
> >> +  /*
> >> +   * Optimize for slow and wide. This is the place to add alternative
> >> +   * optimization policy.
> >> +   */
> >> +  if (!intel_dp_compute_link_config_wide(intel_dp, pipe_config, ))
> >> +  return false;
> >>  
> >>DRM_DEBUG_KMS("DP lane count %d clock %d bpp %d\n",
> >> -pipe_config->lane_count, pipe_config->port_clock, bpp);
> >> -  DRM_DEBUG_KMS("DP link bw 

Re: [Intel-gfx] [PATCH v2 1/2] drm/i915/debugfs: Print sink PSR status

[Souza, Jose]

On Fri, 2018-04-06 at 18:40 -0700, Dhinakaran Pandiyan wrote:
> 
> 
> On Sat, 2018-04-07 at 00:49 +, Souza, Jose wrote:
> > On Fri, 2018-04-06 at 16:36 -0700, José Roberto de Souza wrote:
> > > On Mon, 2018-04-02 at 15:38 -0700, Pandiyan, Dhinakaran wrote:
> > > > On Mon, 2018-04-02 at 13:51 -0700, José Roberto de Souza wrote:
> > > > > IGT tests could be improved with sink status, knowing for
> > > > > sure
> > > > > that
> > > > > hardware have activate or exit PSR.
> > > > > 
> > > > > Reviewed-by: Dhinakaran Pandiyan  > > > > om>
> > > > 
> > > > 
> > > > Please don't merge this patch yet. While the patch itself is
> > > > correct,
> > > > testing it brings up an interesting problem.
> > > > 
> > > > Printing the sink_status() leads to power_get(aux_domain) which
> > > > wakes
> > > > up
> > > > the display engine from DC5/6. This results in a HW triggered
> > > > PSR
> > > > exit,
> > > > effectively altering the state that we are trying to read. I
> > > > would
> > > > like
> > > > to understand the problem fully before merging the patch.
> > > 
> > > In my tests(PSR1 only) with DMC loaded, I can see HW trigerring
> > > PSR
> > > exit when reading i915_edp_psr_status with or without this patch,
> > > the
> > > event that caused is 'SRD Mask Reg Write'.
> > > After masking EDP_PSR_DEBUG_MASK_DISP_REG_WRITE in EDP_PSR_DEBUG
> > > it
> > > do
> > > not happens with or without this patch.
> > > 
> 
> Reads causing PSR exit is a concern, but I have seen edp_psr_status
> showing PSR live status as active. If reads triggered exit, then it
> should always be inactive. Unless the exit happens after the status
> is
> read.

Same thing for sink status, I can see that PSR is exiting but the
status is still active on sink.

> 
> > > Masking this event did not bring more IGT errors than we have
> > > now,
> > > what
> > > do you think Dhinakaran? Should we mask it?
> 
> We'll need PSR to exit on some register writes, example flips or
> cursor
> moves. 

PIPE related writes are still causing PSR to exit, PSR_EVENT have a bit
for Register Update and other for Pipe Registers Update but it don't
have a counter part in PSR_MASK/SRD_DEBUG to make the pipe register
updated not trigger a PSR exit.

> 
> > Another information missed:
> > 
> > When doing a dpcd(I did not look at what exacly is causing it)
> > transaction it is causing the HW to be awaken from DC6 with or
> > without
> > masking EDP_PSR_DEBUG_MASK_DISP_REG_WRITE 
> 
> This is expected, AUX_A is in the DC_OFF power domain, so the driver
> forces a DC6 exit.
> 
> > but when masking it do not
> > cause a PSR exit.
> > Reading i915_sr_status also cause HW to be awaken from DC6.
> > 
> 
> What hardware are you testing on? And is this a PSR2 panel?

KBL it is a PSR2 pannels but I did some changes to only enable PSR1.

> 
> 
> 
> > > 
> > > > 
> > > > 
> > > > > Cc: Rodrigo Vivi 
> > > > > Signed-off-by: José Roberto de Souza 
> > > > > ---
> > > > >  drivers/gpu/drm/i915/i915_debugfs.c | 29
> > > > > +
> > > > >  1 file changed, 29 insertions(+)
> > > > > 
> > > > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> > > > > b/drivers/gpu/drm/i915/i915_debugfs.c
> > > > > index 1dba2c451255..c9ac946b62c9 100644
> > > > > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > > > > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > > > > @@ -2603,6 +2603,26 @@ static const char
> > > > > *psr2_live_status(u32
> > > > > val)
> > > > >   return "unknown";
> > > > >  }
> > > > >  
> > > > > +static const char *psr_sink_status(u8 val)
> > > > > +{
> > > > > + static const char * const sink_status[] = {
> > > > > + "inactive",
> > > > > + "transition to active, capture and display",
> > > > > + "active, display from RFB",
> > > > > + "active, capture and display on sink device
> > > > > timings",
> > > > > + "transition to inactive, capture and
> > > > > display,
> > > > > timing re-sync",
> > > > > + "reserved",
> > > > > + "reserved",
> > > > > + "sink internal error"
> > > > > + };
> > > > > +
> > > > > + val &= DP_PSR_SINK_STATE_MASK;
> > > > > + if (val < ARRAY_SIZE(sink_status))
> > > > > + return sink_status[val];
> > > > > +
> > > > > + return "unknown";
> > > > > +}
> > > > > +
> > > > >  static int i915_edp_psr_status(struct seq_file *m, void
> > > > > *data)
> > > > >  {
> > > > >   struct drm_i915_private *dev_priv = node_to_i915(m-
> > > > > > private);
> > > > > 
> > > > > @@ -2684,6 +2704,15 @@ static int i915_edp_psr_status(struct
> > > > > seq_file *m, void *data)
> > > > >   seq_printf(m, "EDP_PSR2_STATUS: %x [%s]\n",
> > > > >  psr2, psr2_live_status(psr2));
> > > > >   }
> > > > > +
> > > > > + if (dev_priv->psr.enabled) {
> > > > > + struct drm_dp_aux *aux = _priv-
> > 

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/4] drm/i915: Change use get_new_plane_state instead of existing plane state

[Patchwork]

== Series Details ==

Series: series starting with [1/4] drm/i915: Change use get_new_plane_state 
instead of existing plane state
URL   : https://patchwork.freedesktop.org/series/41370/
State : success

== Summary ==

 Known issues:

Test kms_flip:
Subgroup flip-vs-absolute-wf_vblank:
pass   -> FAIL   (shard-hsw) fdo#100368
Subgroup flip-vs-expired-vblank:
pass   -> FAIL   (shard-hsw) fdo#102887

fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887

shard-apltotal:2680 pass:1835 dwarn:1   dfail:0   fail:7   skip:836 
time:12644s
shard-hswtotal:2680 pass:1783 dwarn:1   dfail:0   fail:4   skip:891 
time:11369s
Blacklisted hosts:
shard-kbltotal:2680 pass:1964 dwarn:1   dfail:0   fail:6   skip:709 
time:9202s
shard-snbtotal:2680 pass:1366 dwarn:1   dfail:0   fail:10  skip:1303 
time:6924s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8643/shards.html
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[Intel-gfx] ✗ Fi.CI.BAT: failure for Queued/runnable/running engine stats (rev7)

[Patchwork]

== Series Details ==

Series: Queued/runnable/running engine stats (rev7)
URL   : https://patchwork.freedesktop.org/series/36926/
State : failure

== Summary ==

Series 36926v7 Queued/runnable/running engine stats
https://patchwork.freedesktop.org/api/1.0/series/36926/revisions/7/mbox/

 Possible new issues:

Test gem_exec_gttfill:
Subgroup basic:
skip   -> PASS   (fi-pnv-d510)
Test gvt_basic:
Subgroup invalid-placeholder-test:
skip   -> INCOMPLETE (fi-elk-e7500)

fi-bdw-5557u total:285  pass:264  dwarn:0   dfail:0   fail:0   skip:21  
time:429s
fi-bdw-gvtdvmtotal:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:445s
fi-blb-e6850 total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  
time:382s
fi-bsw-n3050 total:285  pass:239  dwarn:0   dfail:0   fail:0   skip:46  
time:541s
fi-bwr-2160  total:285  pass:180  dwarn:0   dfail:0   fail:0   skip:105 
time:297s
fi-bxt-dsi   total:285  pass:255  dwarn:0   dfail:0   fail:0   skip:30  
time:517s
fi-bxt-j4205 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:516s
fi-byt-j1900 total:285  pass:250  dwarn:0   dfail:0   fail:0   skip:35  
time:521s
fi-byt-n2820 total:285  pass:246  dwarn:0   dfail:0   fail:0   skip:39  
time:512s
fi-cfl-8700k total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:409s
fi-cfl-s3total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:564s
fi-cfl-u total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:515s
fi-cnl-y3total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:580s
fi-elk-e7500 total:285  pass:226  dwarn:0   dfail:0   fail:0   skip:58 
fi-gdg-551   total:285  pass:176  dwarn:0   dfail:0   fail:1   skip:108 
time:318s
fi-glk-1 total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:541s
fi-glk-j4005 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:489s
fi-hsw-4770  total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:408s
fi-ilk-650   total:285  pass:225  dwarn:0   dfail:0   fail:0   skip:60  
time:422s
fi-ivb-3520m total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:470s
fi-ivb-3770  total:285  pass:252  dwarn:0   dfail:0   fail:0   skip:33  
time:433s
fi-kbl-7500u total:285  pass:260  dwarn:1   dfail:0   fail:0   skip:24  
time:471s
fi-kbl-7567u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:474s
fi-kbl-r total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:513s
fi-pnv-d510  total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  
time:668s
fi-skl-6260u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:444s
fi-skl-6600u total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:536s
fi-skl-6700k2total:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:500s
fi-skl-6770hqtotal:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:503s
fi-skl-guc   total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:431s
fi-skl-gvtdvmtotal:285  pass:262  dwarn:0   dfail:0   fail:0   skip:23  
time:445s
fi-snb-2520m total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:580s
fi-snb-2600  total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:406s

1cda370ffded69ce8c5ffa4fba3564a952730b97 drm-tip: 2018y-04m-09d-14h-03m-58s UTC 
integration manifest
966c10a475b1 drm/i915: Engine queues query
f2cd91627fb3 drm/i915/pmu: Add running counter
f85771222d50 drm/i915/pmu: Add runnable counter
d640c428d4e0 drm/i915/pmu: Add queued counter
765f3adef3ef drm/i915: Keep a count of requests submitted from userspace
7e5d1b1b004e drm/i915: Keep a count of requests waiting for a slot on GPU
0f51d0f81fea drm/i915/pmu: Fix enable count array size and bounds checking

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8646/issues.html
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Re: [Intel-gfx] [PATCH i-g-t] tools/aubdump: Fix ISO C90 forbids mixed declarations and code warning

[Scott D Phillips]

Tvrtko Ursulin  writes:

> From: Tvrtko Ursulin 
>
> Back to a clean build with no warnings, at least for me.

Why c90? If that's the language we mean to target then we should
probably add it to the build system so people with gcc 5.1 and later
will see the warnings too. fwiw, my build with clang 6 gives a couple
dozen warnings.

> Signed-off-by: Tvrtko Ursulin 
> Cc: Jordan Justen 
> Cc: Scott D Phillips 
> ---
>  tools/aubdump.c | 7 ---
>  1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/tools/aubdump.c b/tools/aubdump.c
> index 267061b0fc2b..2d2b6c607a43 100644
> --- a/tools/aubdump.c
> +++ b/tools/aubdump.c
> @@ -394,10 +394,11 @@ gen8_emit_ggtt_pte_for_range(uint64_t start, uint64_t 
> end)
>  
>   entry_addr = start & ~(4096 - 1);
>   do {
> + uint64_t last_page_entry, num_entries;
> +
>   page_num = entry_addr >> 21;
> - uint64_t last_page_entry =
> - min((page_num + 1) << 21, end_aligned);
> - uint64_t num_entries = (last_page_entry - entry_addr) >> 12;
> + last_page_entry = min((page_num + 1) << 21, end_aligned);
> + num_entries = (last_page_entry - entry_addr) >> 12;
>   mem_trace_memory_write_header_out(
>   entry_addr >> 9, num_entries * GEN8_PTE_SIZE,
>   AUB_MEM_TRACE_MEMORY_ADDRESS_SPACE_GGTT_ENTRY);
> -- 
> 2.14.1
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/guc: Check that the breadcrumb irq is enabled

[Patchwork]

== Series Details ==

Series: drm/i915/guc: Check that the breadcrumb irq is enabled
URL   : https://patchwork.freedesktop.org/series/41368/
State : success

== Summary ==

 Known issues:

Test kms_flip:
Subgroup 2x-wf_vblank-ts-check:
fail   -> PASS   (shard-hsw) fdo#100368
Subgroup flip-vs-expired-vblank:
pass   -> FAIL   (shard-hsw) fdo#102887
Test prime_vgem:
Subgroup basic-fence-flip:
pass   -> FAIL   (shard-apl) fdo#104008

fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008

shard-apltotal:2680 pass:1834 dwarn:1   dfail:0   fail:8   skip:836 
time:12671s
shard-hswtotal:2680 pass:1785 dwarn:1   dfail:0   fail:2   skip:891 
time:11431s
Blacklisted hosts:
shard-kbltotal:2680 pass:1961 dwarn:1   dfail:0   fail:8   skip:710 
time:9164s
shard-snbtotal:2680 pass:1377 dwarn:1   dfail:0   fail:3   skip:1299 
time:6942s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8642/shards.html
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[Intel-gfx] [PATCH v3 7/7] drm/i915: Engine queues query

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

As well as exposing active requests on engines via PMU, we can also export
the current raw values (as tracked by i915 command submission) via a
dedicated query.

This is to satisfy customers who have userspace load balancing solutions
implemented on top of their custom kernel patches.

Userspace is now able to include DRM_I915_QUERY_ENGINE_QUEUES in their
query list, pointing to initialized struct drm_i915_query_engine_queues
entry. Fields describing engine class and instance userspace would like to
know about need to be filled in, and i915 will fill in the rest.

Multiple engines can be queried in one go by having multiple queries in
the query list.

v2:
 * Use EINVAL for reporting insufficient buffer space. (Chris Wilson)

v3:
 * One more reserved dword because I like even numbers.
 Lionel Landwerlin:
 * Document input fields.
 * Document reserved bits must be zero.

Signed-off-by: Tvrtko Ursulin 
Cc: Dmitry Rogozhkin 
Reviewed-by: Lionel Landwerlin 
---
 drivers/gpu/drm/i915/i915_query.c | 43 +++
 include/uapi/drm/i915_drm.h   | 29 ++
 2 files changed, 72 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_query.c 
b/drivers/gpu/drm/i915/i915_query.c
index 3ace929dd90f..798672f5c104 100644
--- a/drivers/gpu/drm/i915/i915_query.c
+++ b/drivers/gpu/drm/i915/i915_query.c
@@ -82,9 +82,52 @@ static int query_topology_info(struct drm_i915_private 
*dev_priv,
return total_length;
 }
 
+static int
+query_engine_queues(struct drm_i915_private *i915,
+   struct drm_i915_query_item *query_item)
+{
+   struct drm_i915_query_engine_queues __user *query_ptr =
+   u64_to_user_ptr(query_item->data_ptr);
+   struct drm_i915_query_engine_queues query;
+   struct intel_engine_cs *engine;
+   const int len = sizeof(query);
+   unsigned int i;
+
+   if (query_item->flags)
+   return -EINVAL;
+
+   if (!query_item->length)
+   return len;
+   else if (query_item->length < len)
+   return -EINVAL;
+
+   if (copy_from_user(, query_ptr, len))
+   return -EFAULT;
+
+   for (i = 0; i < ARRAY_SIZE(query.rsvd); i++) {
+   if (query.rsvd[i])
+   return -EINVAL;
+   }
+
+   engine = intel_engine_lookup_user(i915, query.class, query.instance);
+   if (!engine)
+   return -ENOENT;
+
+   query.queued = atomic_read(>request_stats.queued);
+   query.runnable = engine->request_stats.runnable;
+   query.running = intel_engine_last_submit(engine) -
+   intel_engine_get_seqno(engine);
+
+   if (copy_to_user(query_ptr, , len))
+   return -EFAULT;
+
+   return len;
+}
+
 static int (* const i915_query_funcs[])(struct drm_i915_private *dev_priv,
struct drm_i915_query_item *query_item) 
= {
query_topology_info,
+   query_engine_queues,
 };
 
 int i915_query_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 9a00c30e4071..c82035b71824 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -1637,6 +1637,7 @@ struct drm_i915_perf_oa_config {
 struct drm_i915_query_item {
__u64 query_id;
 #define DRM_I915_QUERY_TOPOLOGY_INFO1
+#define DRM_I915_QUERY_ENGINE_QUEUES   2
 
/*
 * When set to zero by userspace, this is filled with the size of the
@@ -1734,6 +1735,34 @@ struct drm_i915_query_topology_info {
__u8 data[];
 };
 
+/**
+ * struct drm_i915_query_engine_queues
+ *
+ * Engine queues query enables userspace to query current counts of active
+ * requests in their different states.
+ */
+struct drm_i915_query_engine_queues {
+   /**
+* Engine class as in enum drm_i915_gem_engine_class (set by userspace).
+*/
+   __u16 class;
+
+   /** Engine instance number (set by userspace). */
+   __u16 instance;
+
+   /** Number of requests with unresolved fences and dependencies. */
+   __u32 queued;
+
+   /** Number of ready requests waiting on a slot on GPU. */
+   __u32 runnable;
+
+   /** Number of requests executing on the GPU. */
+   __u32 running;
+
+   /** Reserved bits must be set to zero by userspace. */
+   __u32 rsvd[6];
+};
+
 #if defined(__cplusplus)
 }
 #endif
-- 
2.14.1

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[Intel-gfx] [PATCH v10 2/7] drm/i915: Keep a count of requests waiting for a slot on GPU

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

Keep a per-engine number of runnable (waiting for GPU time) requests.

We choose to mange the runnable counter at the backend level instead of at
the request submit_notify callback. The latter would be more consolidated
and less code, but it would require making the counter either atomic_t or
taking the engine->timeline->lock in submit_notify. So the choice is to do
it at the backend level for the benefit of fewer atomic instructions.

v2:
 * Move queued increment from insert_request to execlist_submit_request to
   avoid bumping when re-ordering for priority.
 * Support the counter on the ringbuffer submission path as well, albeit
   just notionally. (Chris Wilson)

v3:
 * Rebase.

v4:
 * Rename and move the stats into a container structure. (Chris Wilson)

v5:
 * Re-order fields in struct intel_engine_cs. (Chris Wilson)

v6-v8:
 * Rebases.

v9:
 * Fix accounting during wedging.

v10:
 * Improved commit message. (Chris Wilson)

Signed-off-by: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/i915_gem.c | 1 +
 drivers/gpu/drm/i915/i915_request.c | 7 +++
 drivers/gpu/drm/i915/intel_engine_cs.c  | 5 +++--
 drivers/gpu/drm/i915/intel_lrc.c| 1 +
 drivers/gpu/drm/i915/intel_ringbuffer.h | 9 +
 5 files changed, 21 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 28ab0beff86c..aa8d19fac167 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3304,6 +3304,7 @@ static void nop_complete_submit_request(struct 
i915_request *request)
dma_fence_set_error(>fence, -EIO);
 
spin_lock_irqsave(>engine->timeline->lock, flags);
+   request->engine->request_stats.runnable++;
__i915_request_submit(request);
intel_engine_init_global_seqno(request->engine, request->global_seqno);
spin_unlock_irqrestore(>engine->timeline->lock, flags);
diff --git a/drivers/gpu/drm/i915/i915_request.c 
b/drivers/gpu/drm/i915/i915_request.c
index 9ca9c24b4421..2617bd008845 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -494,6 +494,9 @@ void __i915_request_submit(struct i915_request *request)
/* Transfer from per-context onto the global per-engine timeline */
move_to_timeline(request, engine->timeline);
 
+   GEM_BUG_ON(engine->request_stats.runnable == 0);
+   engine->request_stats.runnable--;
+
trace_i915_request_execute(request);
 
wake_up_all(>execute);
@@ -507,6 +510,8 @@ void i915_request_submit(struct i915_request *request)
/* Will be called from irq-context when using foreign fences. */
spin_lock_irqsave(>timeline->lock, flags);
 
+   engine->request_stats.runnable++;
+
__i915_request_submit(request);
 
spin_unlock_irqrestore(>timeline->lock, flags);
@@ -545,6 +550,8 @@ void __i915_request_unsubmit(struct i915_request *request)
/* Transfer back from the global per-engine timeline to per-context */
move_to_timeline(request, request->timeline);
 
+   engine->request_stats.runnable++;
+
/*
 * We don't need to wake_up any waiters on request->execute, they
 * will get woken by any other event or us re-adding this request
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 12486d8f534b..98254ff92785 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1934,12 +1934,13 @@ void intel_engine_dump(struct intel_engine_cs *engine,
if (i915_terminally_wedged(>i915->gpu_error))
drm_printf(m, "*** WEDGED ***\n");
 
-   drm_printf(m, "\tcurrent seqno %x, last %x, hangcheck %x [%d ms], 
inflight %d\n",
+   drm_printf(m, "\tcurrent seqno %x, last %x, hangcheck %x [%d ms], 
inflight %d, runnable %u\n",
   intel_engine_get_seqno(engine),
   intel_engine_last_submit(engine),
   engine->hangcheck.seqno,
   jiffies_to_msecs(jiffies - 
engine->hangcheck.action_timestamp),
-  engine->timeline->inflight_seqnos);
+  engine->timeline->inflight_seqnos,
+  engine->request_stats.runnable);
drm_printf(m, "\tReset count: %d (global %d)\n",
   i915_reset_engine_count(error, engine),
   i915_reset_count(error));
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 02b25bf2378a..16ea95ff7c51 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1124,6 +1124,7 @@ static void execlists_submit_request(struct i915_request 
*request)
 
queue_request(engine, >priotree, rq_prio(request));
submit_queue(engine, rq_prio(request));
+   engine->request_stats.runnable++;
 
GEM_BUG_ON(!engine->execlists.first);
   

[Intel-gfx] [PATCH v4 3/7] drm/i915: Keep a count of requests submitted from userspace

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

Keep a count of requests submitted from userspace and not yet runnable due
unresolved dependencies.

v2: Rename and move under the container struct. (Chris Wilson)
v3: Rebase.
v4: Move decrement site to the backend to shrink the window of double-
accounting as much as possible. (Chris Wilson)

Signed-off-by: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/i915_request.c | 3 +++
 drivers/gpu/drm/i915/intel_engine_cs.c  | 3 ++-
 drivers/gpu/drm/i915/intel_lrc.c| 2 ++
 drivers/gpu/drm/i915/intel_ringbuffer.h | 8 
 4 files changed, 15 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_request.c 
b/drivers/gpu/drm/i915/i915_request.c
index 2617bd008845..997be595d7e7 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -511,6 +511,7 @@ void i915_request_submit(struct i915_request *request)
spin_lock_irqsave(>timeline->lock, flags);
 
engine->request_stats.runnable++;
+   atomic_dec(>request_stats.queued);
 
__i915_request_submit(request);
 
@@ -1072,6 +1073,8 @@ void __i915_request_add(struct i915_request *request, 
bool flush_caches)
engine->schedule(request, request->ctx->priority);
rcu_read_unlock();
 
+   atomic_inc(>request_stats.queued);
+
local_bh_disable();
i915_sw_fence_commit(>submit);
local_bh_enable(); /* Kick the execlists tasklet if just scheduled */
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 98254ff92785..e4992c2e23a4 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1934,12 +1934,13 @@ void intel_engine_dump(struct intel_engine_cs *engine,
if (i915_terminally_wedged(>i915->gpu_error))
drm_printf(m, "*** WEDGED ***\n");
 
-   drm_printf(m, "\tcurrent seqno %x, last %x, hangcheck %x [%d ms], 
inflight %d, runnable %u\n",
+   drm_printf(m, "\tcurrent seqno %x, last %x, hangcheck %x [%d ms], 
inflight %d, queued %u, runnable %u\n",
   intel_engine_get_seqno(engine),
   intel_engine_last_submit(engine),
   engine->hangcheck.seqno,
   jiffies_to_msecs(jiffies - 
engine->hangcheck.action_timestamp),
   engine->timeline->inflight_seqnos,
+  atomic_read(>request_stats.queued),
   engine->request_stats.runnable);
drm_printf(m, "\tReset count: %d (global %d)\n",
   i915_reset_engine_count(error, engine),
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 16ea95ff7c51..ddd14e30be6c 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1124,7 +1124,9 @@ static void execlists_submit_request(struct i915_request 
*request)
 
queue_request(engine, >priotree, rq_prio(request));
submit_queue(engine, rq_prio(request));
+
engine->request_stats.runnable++;
+   atomic_dec(>request_stats.queued);
 
GEM_BUG_ON(!engine->execlists.first);
GEM_BUG_ON(list_empty(>priotree.link));
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h 
b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 54d2ad1c8daa..616066f536c9 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -339,6 +339,14 @@ struct intel_engine_cs {
struct drm_i915_gem_object *default_state;
 
struct {
+   /**
+* @queued: Number of submitted requests with dependencies.
+*
+* Count of requests waiting for dependencies before they can be
+* submitted to the backend.
+*/
+   atomic_t queued;
+
/**
 * @runnable: Number of runnable requests sent to the backend.
 *
-- 
2.14.1

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[Intel-gfx] [PATCH i-g-t] tools/aubdump: Fix ISO C90 forbids mixed declarations and code warning

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

Back to a clean build with no warnings, at least for me.

Signed-off-by: Tvrtko Ursulin 
Cc: Jordan Justen 
Cc: Scott D Phillips 
---
 tools/aubdump.c | 7 ---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/tools/aubdump.c b/tools/aubdump.c
index 267061b0fc2b..2d2b6c607a43 100644
--- a/tools/aubdump.c
+++ b/tools/aubdump.c
@@ -394,10 +394,11 @@ gen8_emit_ggtt_pte_for_range(uint64_t start, uint64_t end)
 
entry_addr = start & ~(4096 - 1);
do {
+   uint64_t last_page_entry, num_entries;
+
page_num = entry_addr >> 21;
-   uint64_t last_page_entry =
-   min((page_num + 1) << 21, end_aligned);
-   uint64_t num_entries = (last_page_entry - entry_addr) >> 12;
+   last_page_entry = min((page_num + 1) << 21, end_aligned);
+   num_entries = (last_page_entry - entry_addr) >> 12;
mem_trace_memory_write_header_out(
entry_addr >> 9, num_entries * GEN8_PTE_SIZE,
AUB_MEM_TRACE_MEMORY_ADDRESS_SPACE_GGTT_ENTRY);
-- 
2.14.1

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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/pmu: check runtime resume vs pmu race

[Patchwork]

== Series Details ==

Series: drm/i915/pmu: check runtime resume vs pmu race
URL   : https://patchwork.freedesktop.org/series/41380/
State : success

== Summary ==

Series 41380v1 drm/i915/pmu: check runtime resume vs pmu race
https://patchwork.freedesktop.org/api/1.0/series/41380/revisions/1/mbox/

 Possible new issues:

Test gem_exec_gttfill:
Subgroup basic:
skip   -> PASS   (fi-pnv-d510)

 Known issues:

Test gem_mmap_gtt:
Subgroup basic-small-bo-tiledx:
fail   -> PASS   (fi-gdg-551) fdo#102575
Test kms_flip:
Subgroup basic-flip-vs-wf_vblank:
pass   -> FAIL   (fi-skl-6770hq) fdo#100368
Test kms_pipe_crc_basic:
Subgroup read-crc-pipe-b-frame-sequence:
pass   -> FAIL   (fi-skl-6770hq) fdo#103481

fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#103481 https://bugs.freedesktop.org/show_bug.cgi?id=103481

fi-bdw-5557u total:285  pass:264  dwarn:0   dfail:0   fail:0   skip:21  
time:433s
fi-bdw-gvtdvmtotal:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:442s
fi-blb-e6850 total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  
time:380s
fi-bsw-n3050 total:285  pass:239  dwarn:0   dfail:0   fail:0   skip:46  
time:552s
fi-bwr-2160  total:285  pass:180  dwarn:0   dfail:0   fail:0   skip:105 
time:299s
fi-bxt-dsi   total:285  pass:255  dwarn:0   dfail:0   fail:0   skip:30  
time:513s
fi-bxt-j4205 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:516s
fi-byt-j1900 total:285  pass:250  dwarn:0   dfail:0   fail:0   skip:35  
time:524s
fi-byt-n2820 total:285  pass:246  dwarn:0   dfail:0   fail:0   skip:39  
time:511s
fi-cfl-8700k total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:410s
fi-cfl-s3total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:561s
fi-cfl-u total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:512s
fi-cnl-y3total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:582s
fi-elk-e7500 total:285  pass:226  dwarn:0   dfail:0   fail:0   skip:59  
time:428s
fi-gdg-551   total:285  pass:177  dwarn:0   dfail:0   fail:0   skip:108 
time:317s
fi-glk-1 total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:542s
fi-glk-j4005 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:486s
fi-hsw-4770  total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:408s
fi-ilk-650   total:285  pass:225  dwarn:0   dfail:0   fail:0   skip:60  
time:424s
fi-ivb-3520m total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:471s
fi-ivb-3770  total:285  pass:252  dwarn:0   dfail:0   fail:0   skip:33  
time:435s
fi-kbl-7500u total:285  pass:260  dwarn:1   dfail:0   fail:0   skip:24  
time:475s
fi-kbl-7567u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:465s
fi-kbl-r total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:512s
fi-pnv-d510  total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  
time:665s
fi-skl-6260u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:439s
fi-skl-6600u total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:538s
fi-skl-6700k2total:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:513s
fi-skl-6770hqtotal:285  pass:263  dwarn:0   dfail:0   fail:2   skip:20  
time:498s
fi-skl-guc   total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:429s
fi-skl-gvtdvmtotal:285  pass:262  dwarn:0   dfail:0   fail:0   skip:23  
time:444s
fi-snb-2520m total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:560s
fi-snb-2600  total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:400s

1cda370ffded69ce8c5ffa4fba3564a952730b97 drm-tip: 2018y-04m-09d-14h-03m-58s UTC 
integration manifest
bb065b725840 drm/i915/pmu: check runtime resume vs pmu race

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8645/issues.html
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gen9_lp: Increase DDI PHY0 power well enabling timeout

[Patchwork]

== Series Details ==

Series: drm/i915/gen9_lp: Increase DDI PHY0 power well enabling timeout
URL   : https://patchwork.freedesktop.org/series/41366/
State : success

== Summary ==

 Known issues:

Test kms_flip:
Subgroup 2x-wf_vblank-ts-check:
fail   -> PASS   (shard-hsw) fdo#100368

fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368

shard-apltotal:2680 pass:1835 dwarn:1   dfail:0   fail:7   skip:836 
time:12687s
shard-hswtotal:2680 pass:1786 dwarn:1   dfail:0   fail:1   skip:891 
time:11445s
Blacklisted hosts:
shard-snbtotal:2680 pass:1377 dwarn:1   dfail:0   fail:3   skip:1299 
time:6957s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8641/shards.html
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[Intel-gfx] [CI] drm/i915/pmu: check runtime resume vs pmu race

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

Signed-off-by: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/i915_pmu.c | 6 +-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index bd7e695fc663..9302b4abe357 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -479,7 +479,11 @@ static u64 get_rc6(struct drm_i915_private *i915)
 
val = kdev->power.suspended_jiffies -
  i915->pmu.suspended_jiffies_last;
-   val += jiffies - kdev->power.accounting_timestamp;
+
+   if (kdev->power.runtime_status == RPM_SUSPENDED)
+   val += jiffies - kdev->power.accounting_timestamp;
+   else
+   WARN(1, "not suspended");
 
spin_unlock(>power.lock);
 
-- 
2.14.1

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Re: [Intel-gfx] [PATCH v8 08/12] drm/i915/uc: Fully sanitize uC within intel_uc_fini_hw

[Sagar Arun Kamble]

On 4/9/2018 5:53 PM, Michal Wajdeczko wrote:

As we always call intel_uc_sanitize after every call to
intel_uc_fini_hw we may drop redundant call and sanitize
uC from the fini_hw function.

Signed-off-by: Michal Wajdeczko 
Cc: Sagar Arun Kamble 
Cc: Chris Wilson 

With change to sanitize during uc_init_mmio this looks good to me.
Reviewed-by: Sagar Arun Kamble 

---
  drivers/gpu/drm/i915/i915_gem.c | 2 --
  drivers/gpu/drm/i915/intel_uc.c | 9 +++--
  drivers/gpu/drm/i915/intel_uc.h | 1 -
  3 files changed, 3 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index ceec5a0..decda1a 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3077,7 +3077,6 @@ int i915_gem_reset_prepare(struct drm_i915_private 
*dev_priv)
}
  
  	i915_gem_revoke_fences(dev_priv);

-   intel_uc_sanitize(dev_priv);
  
  	return err;

  }
@@ -5062,7 +5061,6 @@ int i915_gem_suspend(struct drm_i915_private *dev_priv)
 * machine in an unusable condition.
 */
i915_gem_fini_hw(dev_priv);
-   intel_uc_sanitize(dev_priv);
i915_gem_sanitize(dev_priv);
  
  	intel_runtime_pm_put(dev_priv);

diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 1cffaf7..0439966 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -322,18 +322,13 @@ void intel_uc_fini(struct drm_i915_private *dev_priv)
intel_guc_fini(guc);
  }
  
-void intel_uc_sanitize(struct drm_i915_private *i915)

+static void __uc_sanitize(struct drm_i915_private *i915)
  {
struct intel_guc *guc = >guc;
struct intel_huc *huc = >huc;
  
-	if (!USES_GUC(i915))

-   return;
-
GEM_BUG_ON(!HAS_GUC(i915));
  
-	guc_disable_communication(guc);

-
intel_huc_sanitize(huc);
intel_guc_sanitize(guc);
  
@@ -445,6 +440,8 @@ void intel_uc_fini_hw(struct drm_i915_private *dev_priv)

intel_guc_submission_disable(guc);
  
  	guc_disable_communication(guc);

+
+   __uc_sanitize(dev_priv);
  }
  
  int intel_uc_suspend(struct drm_i915_private *i915)

diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
index 25d73ad..64aaf93 100644
--- a/drivers/gpu/drm/i915/intel_uc.h
+++ b/drivers/gpu/drm/i915/intel_uc.h
@@ -33,7 +33,6 @@
  void intel_uc_init_mmio(struct drm_i915_private *dev_priv);
  int intel_uc_init_misc(struct drm_i915_private *dev_priv);
  void intel_uc_fini_misc(struct drm_i915_private *dev_priv);
-void intel_uc_sanitize(struct drm_i915_private *dev_priv);
  int intel_uc_init_hw(struct drm_i915_private *dev_priv);
  void intel_uc_fini_hw(struct drm_i915_private *dev_priv);
  int intel_uc_init(struct drm_i915_private *dev_priv);


--
Thanks,
Sagar

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Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v8,01/12] drm/i915: Park before resetting the submission backend

[Michal Wajdeczko]

On Mon, 09 Apr 2018 17:09:18 +0200, Patchwork  
 wrote:



== Series Details ==

Series: series starting with [v8,01/12] drm/i915: Park before resetting  
the submission backend

URL   : https://patchwork.freedesktop.org/series/41365/
State : failure

== Summary ==

 Possible new issues:


two variants:



Test drm_mm:
Subgroup sanitycheck:
pass   -> INCOMPLETE (shard-apl)


#1

<0>[  400.245461] drv_self-57751 400208508us :  
intel_guc_submission_disable: intel_guc_submission_disable:1255  
GEM_BUG_ON(dev_priv->gt.awake)


<4>[  400.245871] Call Trace:
<4>[  400.245959]  intel_uc_fini_hw+0x4b/0xe0 [i915]
<4>[  400.246047]  i915_gem_fini_hw+0x16/0x30 [i915]
<4>[  400.246129]  i915_reset+0x1e8/0x2b0 [i915]
<4>[  400.246222]  igt_global_reset+0x38/0xe0 [i915]


Test drv_hangman:
Subgroup error-state-capture-blt:
pass   -> INCOMPLETE (shard-apl)
Subgroup error-state-capture-bsd:
pass   -> INCOMPLETE (shard-apl)
Subgroup error-state-capture-render:
pass   -> INCOMPLETE (shard-apl)
Subgroup error-state-capture-vebox:
pass   -> INCOMPLETE (shard-apl)
Test drv_selftest:
Subgroup live_guc:
pass   -> SKIP   (shard-apl)
Subgroup live_hangcheck:
pass   -> DMESG-FAIL (shard-apl)
Test gem_eio:
Subgroup execbuf:
pass   -> INCOMPLETE (shard-apl)


#2:

<3>[  227.833798] intel_engine_unpin_breadcrumbs_irq:219  
GEM_BUG_ON(!b->irq_enabled)


<4>[  227.834607] Call Trace:
<4>[  227.834691]  intel_engines_park+0xef/0x180 [i915]
<4>[  227.834709]  ? synchronize_irq+0x3e/0xb0
<4>[  227.834781]  __i915_gem_park+0x3e/0x160 [i915]
<4>[  227.834850]  i915_gem_idle_work_handler+0x1cd/0x220 [i915]
<4>[  227.834868]  process_one_work+0x21a/0x640



Subgroup in-flight-external:
pass   -> INCOMPLETE (shard-apl)
Test gem_mocs_settings:
Subgroup mocs-reset-dirty-render:
pass   -> INCOMPLETE (shard-apl)
Test gem_request_retire:
Subgroup retire-vma-not-inactive:
pass   -> INCOMPLETE (shard-apl)
Test gem_workarounds:
Subgroup reset-context:
pass   -> INCOMPLETE (shard-apl)
Test kms_vblank:
Subgroup pipe-a-query-idle-hang:
pass   -> INCOMPLETE (shard-apl)
Subgroup pipe-a-ts-continuation-idle-hang:
pass   -> INCOMPLETE (shard-apl)
Subgroup pipe-a-wait-busy-hang:
pass   -> INCOMPLETE (shard-apl)
Subgroup pipe-a-wait-forked-busy-hang:
pass   -> INCOMPLETE (shard-apl)
Subgroup pipe-a-wait-idle-hang:
pass   -> INCOMPLETE (shard-apl)
Subgroup pipe-b-query-forked-hang:
pass   -> INCOMPLETE (shard-apl)
Subgroup pipe-c-query-busy-hang:
pass   -> INCOMPLETE (shard-apl)
Subgroup pipe-c-query-forked-busy-hang:
pass   -> INCOMPLETE (shard-apl)
Subgroup pipe-c-query-forked-hang:
pass   -> INCOMPLETE (shard-apl)
Subgroup pipe-c-ts-continuation-idle-hang:
pass   -> INCOMPLETE (shard-apl)
Test perf:
Subgroup gen8-unprivileged-single-ctx-counters:
pass   -> FAIL   (shard-apl)

 Known issues:

Test drv_missed_irq:
pass   -> SKIP   (shard-apl) fdo#103199
Test gem_eio:
Subgroup in-flight-suspend:
pass   -> INCOMPLETE (shard-apl) fdo#103375
Test kms_flip:
Subgroup flip-vs-expired-vblank:
fail   -> PASS   (shard-hsw) fdo#102887
Subgroup modeset-vs-vblank-race-interruptible:
pass   -> FAIL   (shard-hsw) fdo#103060
Test kms_plane_multiple:
Subgroup atomic-pipe-c-tiling-x:
pass   -> FAIL   (shard-apl) fdo#103166
Test kms_rotation_crc:
Subgroup sprite-rotation-90:
fail   -> PASS   (shard-apl) fdo#103925

fdo#103199 https://bugs.freedesktop.org/show_bug.cgi?id=103199
fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375
fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166
fdo#103925 https://bugs.freedesktop.org/show_bug.cgi?id=103925

shard-apltotal:1541 pass:1003 dwarn:1   dfail:1   fail:9
skip:497 time:2569s
shard-hswtotal:2680 pass:1784 dwarn:1   dfail:0   fail:3
skip:891 time:11411s

Blacklisted hosts:
shard-kbltotal:1439 pass:1014 dwarn:1   dfail:1   fail:6
skip:386 time:1390s
shard-snbtotal:2680 pass:1378 dwarn:1   dfail:0   fail:3
skip:1298 time:6927s


== Logs ==

For more details see:  

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v8,01/12] drm/i915: Park before resetting the submission backend

[Patchwork]

== Series Details ==

Series: series starting with [v8,01/12] drm/i915: Park before resetting the 
submission backend
URL   : https://patchwork.freedesktop.org/series/41365/
State : failure

== Summary ==

 Possible new issues:

Test drm_mm:
Subgroup sanitycheck:
pass   -> INCOMPLETE (shard-apl)
Test drv_hangman:
Subgroup error-state-capture-blt:
pass   -> INCOMPLETE (shard-apl)
Subgroup error-state-capture-bsd:
pass   -> INCOMPLETE (shard-apl)
Subgroup error-state-capture-render:
pass   -> INCOMPLETE (shard-apl)
Subgroup error-state-capture-vebox:
pass   -> INCOMPLETE (shard-apl)
Test drv_selftest:
Subgroup live_guc:
pass   -> SKIP   (shard-apl)
Subgroup live_hangcheck:
pass   -> DMESG-FAIL (shard-apl)
Test gem_eio:
Subgroup execbuf:
pass   -> INCOMPLETE (shard-apl)
Subgroup in-flight-external:
pass   -> INCOMPLETE (shard-apl)
Test gem_mocs_settings:
Subgroup mocs-reset-dirty-render:
pass   -> INCOMPLETE (shard-apl)
Test gem_request_retire:
Subgroup retire-vma-not-inactive:
pass   -> INCOMPLETE (shard-apl)
Test gem_workarounds:
Subgroup reset-context:
pass   -> INCOMPLETE (shard-apl)
Test kms_vblank:
Subgroup pipe-a-query-idle-hang:
pass   -> INCOMPLETE (shard-apl)
Subgroup pipe-a-ts-continuation-idle-hang:
pass   -> INCOMPLETE (shard-apl)
Subgroup pipe-a-wait-busy-hang:
pass   -> INCOMPLETE (shard-apl)
Subgroup pipe-a-wait-forked-busy-hang:
pass   -> INCOMPLETE (shard-apl)
Subgroup pipe-a-wait-idle-hang:
pass   -> INCOMPLETE (shard-apl)
Subgroup pipe-b-query-forked-hang:
pass   -> INCOMPLETE (shard-apl)
Subgroup pipe-c-query-busy-hang:
pass   -> INCOMPLETE (shard-apl)
Subgroup pipe-c-query-forked-busy-hang:
pass   -> INCOMPLETE (shard-apl)
Subgroup pipe-c-query-forked-hang:
pass   -> INCOMPLETE (shard-apl)
Subgroup pipe-c-ts-continuation-idle-hang:
pass   -> INCOMPLETE (shard-apl)
Test perf:
Subgroup gen8-unprivileged-single-ctx-counters:
pass   -> FAIL   (shard-apl)

 Known issues:

Test drv_missed_irq:
pass   -> SKIP   (shard-apl) fdo#103199
Test gem_eio:
Subgroup in-flight-suspend:
pass   -> INCOMPLETE (shard-apl) fdo#103375
Test kms_flip:
Subgroup flip-vs-expired-vblank:
fail   -> PASS   (shard-hsw) fdo#102887
Subgroup modeset-vs-vblank-race-interruptible:
pass   -> FAIL   (shard-hsw) fdo#103060
Test kms_plane_multiple:
Subgroup atomic-pipe-c-tiling-x:
pass   -> FAIL   (shard-apl) fdo#103166
Test kms_rotation_crc:
Subgroup sprite-rotation-90:
fail   -> PASS   (shard-apl) fdo#103925

fdo#103199 https://bugs.freedesktop.org/show_bug.cgi?id=103199
fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375
fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166
fdo#103925 https://bugs.freedesktop.org/show_bug.cgi?id=103925

shard-apltotal:1541 pass:1003 dwarn:1   dfail:1   fail:9   skip:497 
time:2569s
shard-hswtotal:2680 pass:1784 dwarn:1   dfail:0   fail:3   skip:891 
time:11411s
Blacklisted hosts:
shard-kbltotal:1439 pass:1014 dwarn:1   dfail:1   fail:6   skip:386 
time:1390s
shard-snbtotal:2680 pass:1378 dwarn:1   dfail:0   fail:3   skip:1298 
time:6927s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8640/shards.html
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Re: [Intel-gfx] [PATCH v8 05/12] drm/i915: Add i915_gem_fini_hw to i915_gem_suspend

[Sagar Arun Kamble]

On 4/9/2018 5:53 PM, Michal Wajdeczko wrote:

By calling i915_gem_init_hw in i915_gem_resume and not calling
i915_gem_fini_hw in i915_gem_suspend we introduced asymmetry
in init_hw/fini_hw calls. Let's fix that.

Signed-off-by: Michal Wajdeczko 
Cc: Sagar Arun Kamble 
Cc: Chris Wilson 

Reviewed-by: Sagar Arun Kamble 

---
  drivers/gpu/drm/i915/i915_gem.c | 1 +
  1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 6f71099..ceec5a0 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -5061,6 +5061,7 @@ int i915_gem_suspend(struct drm_i915_private *dev_priv)
 * machines is a good idea, we don't - just in case it leaves the
 * machine in an unusable condition.
 */
+   i915_gem_fini_hw(dev_priv);
intel_uc_sanitize(dev_priv);
i915_gem_sanitize(dev_priv);
  


--
Thanks,
Sagar

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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Enable display workaround 827 for all planes, v2.

[Patchwork]

== Series Details ==

Series: drm/i915: Enable display workaround 827 for all planes, v2.
URL   : https://patchwork.freedesktop.org/series/41371/
State : success

== Summary ==

Series 41371v1 drm/i915: Enable display workaround 827 for all planes, v2.
https://patchwork.freedesktop.org/api/1.0/series/41371/revisions/1/mbox/

 Possible new issues:

Test gem_exec_gttfill:
Subgroup basic:
skip   -> PASS   (fi-pnv-d510)

 Known issues:

Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
pass   -> FAIL   (fi-skl-guc) fdo#103191

fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191

fi-bdw-5557u total:285  pass:264  dwarn:0   dfail:0   fail:0   skip:21  
time:432s
fi-bdw-gvtdvmtotal:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:442s
fi-blb-e6850 total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  
time:382s
fi-bsw-n3050 total:285  pass:239  dwarn:0   dfail:0   fail:0   skip:46  
time:544s
fi-bwr-2160  total:285  pass:180  dwarn:0   dfail:0   fail:0   skip:105 
time:299s
fi-bxt-dsi   total:285  pass:255  dwarn:0   dfail:0   fail:0   skip:30  
time:514s
fi-bxt-j4205 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:514s
fi-byt-j1900 total:285  pass:250  dwarn:0   dfail:0   fail:0   skip:35  
time:523s
fi-byt-n2820 total:285  pass:246  dwarn:0   dfail:0   fail:0   skip:39  
time:508s
fi-cfl-8700k total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:409s
fi-cfl-s3total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:560s
fi-cfl-u total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:514s
fi-cnl-y3total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:590s
fi-elk-e7500 total:285  pass:226  dwarn:0   dfail:0   fail:0   skip:59  
time:424s
fi-gdg-551   total:285  pass:176  dwarn:0   dfail:0   fail:1   skip:108 
time:314s
fi-glk-1 total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:546s
fi-glk-j4005 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:485s
fi-hsw-4770  total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:411s
fi-ilk-650   total:285  pass:225  dwarn:0   dfail:0   fail:0   skip:60  
time:425s
fi-ivb-3520m total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:473s
fi-ivb-3770  total:285  pass:252  dwarn:0   dfail:0   fail:0   skip:33  
time:437s
fi-kbl-7500u total:285  pass:260  dwarn:1   dfail:0   fail:0   skip:24  
time:471s
fi-kbl-7567u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:468s
fi-kbl-r total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:511s
fi-pnv-d510  total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  
time:668s
fi-skl-6260u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:439s
fi-skl-6600u total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:536s
fi-skl-6700k2total:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:499s
fi-skl-6770hqtotal:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:509s
fi-skl-guc   total:285  pass:256  dwarn:0   dfail:0   fail:1   skip:28  
time:430s
fi-skl-gvtdvmtotal:285  pass:262  dwarn:0   dfail:0   fail:0   skip:23  
time:446s
fi-snb-2520m total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:572s
fi-snb-2600  total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:396s

1cda370ffded69ce8c5ffa4fba3564a952730b97 drm-tip: 2018y-04m-09d-14h-03m-58s UTC 
integration manifest
b8f0788dfd3f drm/i915: Enable display workaround 827 for all planes, v2.

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8644/issues.html
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Re: [Intel-gfx] [PATCH v8 04/12] drm/i915: Introduce i915_gem_fini_hw for symmetry with i915_gem_init_hw

[Sagar Arun Kamble]

On 4/9/2018 5:53 PM, Michal Wajdeczko wrote:

We have i915_gem_init_hw function that on failure requires some
cleanup in uC and then in other places we were trying to do
such cleanup directly. Let's fix that by adding i915_gem_fini_hw
for nice symmetry with init_hw and call it on cleanup paths.

Signed-off-by: Michal Wajdeczko 
Cc: Sagar Arun Kamble 
Cc: Chris Wilson 

Reviewed-by: Sagar Arun Kamble 

---
  drivers/gpu/drm/i915/i915_drv.h |  1 +
  drivers/gpu/drm/i915/i915_gem.c | 13 +++--
  2 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f8bc276..dbd95a4 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3144,6 +3144,7 @@ void i915_gem_reset_engine(struct intel_engine_cs *engine,
  int __must_check i915_gem_init_hw(struct drm_i915_private *dev_priv);
  void i915_gem_init_swizzling(struct drm_i915_private *dev_priv);
  void i915_gem_fini(struct drm_i915_private *dev_priv);
+void i915_gem_fini_hw(struct drm_i915_private *dev_priv);
  void i915_gem_cleanup_engines(struct drm_i915_private *dev_priv);
  int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
   unsigned int flags);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index fb99485..6f71099 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -5257,6 +5257,15 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
goto out;
  }
  
+void i915_gem_fini_hw(struct drm_i915_private *dev_priv)

+{
+   intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
+
+   intel_uc_fini_hw(dev_priv);
+
+   intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+}
+
  static int __intel_engines_record_defaults(struct drm_i915_private *i915)
  {
struct i915_gem_context *ctx;
@@ -5482,7 +5491,7 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
  err_init_hw:
i915_gem_wait_for_idle(dev_priv, I915_WAIT_LOCKED);
i915_gem_contexts_lost(dev_priv);
-   intel_uc_fini_hw(dev_priv);
+   i915_gem_fini_hw(dev_priv);
  err_uc_init:
intel_uc_fini(dev_priv);
  err_pm:
@@ -5526,7 +5535,7 @@ void i915_gem_fini(struct drm_i915_private *dev_priv)
i915_gem_drain_workqueue(dev_priv);
  
  	mutex_lock(_priv->drm.struct_mutex);

-   intel_uc_fini_hw(dev_priv);
+   i915_gem_fini_hw(dev_priv);
intel_uc_fini(dev_priv);
i915_gem_cleanup_engines(dev_priv);
i915_gem_contexts_fini(dev_priv);


--
Thanks,
Sagar

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Re: [Intel-gfx] [PATCH v8 03/12] drm/i915: Move i915_gem_fini to i915_gem.c

[Sagar Arun Kamble]

On 4/9/2018 5:53 PM, Michal Wajdeczko wrote:

We should keep i915_gem_init/fini functions together for easier
tracking of their symmetry.

Signed-off-by: Michal Wajdeczko 
Cc: Sagar Arun Kamble 
Cc: Chris Wilson 

Reviewed-by: Sagar Arun Kamble 

---
  drivers/gpu/drm/i915/i915_drv.c | 20 
  drivers/gpu/drm/i915/i915_drv.h |  1 +
  drivers/gpu/drm/i915/i915_gem.c | 20 
  3 files changed, 21 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index f770be1..854b26c 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -625,26 +625,6 @@ static bool i915_switcheroo_can_switch(struct pci_dev 
*pdev)
.can_switch = i915_switcheroo_can_switch,
  };
  
-static void i915_gem_fini(struct drm_i915_private *dev_priv)

-{
-   /* Flush any outstanding unpin_work. */
-   i915_gem_drain_workqueue(dev_priv);
-
-   mutex_lock(_priv->drm.struct_mutex);
-   intel_uc_fini_hw(dev_priv);
-   intel_uc_fini(dev_priv);
-   i915_gem_cleanup_engines(dev_priv);
-   i915_gem_contexts_fini(dev_priv);
-   mutex_unlock(_priv->drm.struct_mutex);
-
-   intel_uc_fini_misc(dev_priv);
-   i915_gem_cleanup_userptr(dev_priv);
-
-   i915_gem_drain_freed_objects(dev_priv);
-
-   WARN_ON(!list_empty(_priv->contexts.list));
-}
-
  static int i915_load_modeset_init(struct drm_device *dev)
  {
struct drm_i915_private *dev_priv = to_i915(dev);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 9bca104..f8bc276 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3143,6 +3143,7 @@ void i915_gem_reset_engine(struct intel_engine_cs *engine,
  int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
  int __must_check i915_gem_init_hw(struct drm_i915_private *dev_priv);
  void i915_gem_init_swizzling(struct drm_i915_private *dev_priv);
+void i915_gem_fini(struct drm_i915_private *dev_priv);
  void i915_gem_cleanup_engines(struct drm_i915_private *dev_priv);
  int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
   unsigned int flags);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 26294e8..fb99485 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -5520,6 +5520,26 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
return ret;
  }
  
+void i915_gem_fini(struct drm_i915_private *dev_priv)

+{
+   /* Flush any outstanding unpin_work. */
+   i915_gem_drain_workqueue(dev_priv);
+
+   mutex_lock(_priv->drm.struct_mutex);
+   intel_uc_fini_hw(dev_priv);
+   intel_uc_fini(dev_priv);
+   i915_gem_cleanup_engines(dev_priv);
+   i915_gem_contexts_fini(dev_priv);
+   mutex_unlock(_priv->drm.struct_mutex);
+
+   intel_uc_fini_misc(dev_priv);
+   i915_gem_cleanup_userptr(dev_priv);
+
+   i915_gem_drain_freed_objects(dev_priv);
+
+   WARN_ON(!list_empty(_priv->contexts.list));
+}
+
  void i915_gem_init_mmio(struct drm_i915_private *i915)
  {
i915_gem_sanitize(i915);


--
Thanks,
Sagar

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Re: [Intel-gfx] [PATCH] drm/i915/guc: Check that the breadcrumb irq is enabled

[Chris Wilson]

Quoting Michal Wajdeczko (2018-04-09 15:08:40)
> On Mon, 09 Apr 2018 14:42:19 +0200, Chris Wilson  
>  wrote:
> 
> > Our execlists emulation for GuC requires use of the breadcrumb following
> > every request as a simulcrum for the context-switch interrupt, which we
> > then use to drive the submission tasklet. Therefore, when we unpark the
> > engine for use with the GuC, we pin the breadcrumb interrupt to keep it
> > enabled for the duration. This has to be remain so across all resets,
> > wedging and resume, so check we do have the irq enabled when we start
> > submitting requests to the GuC and on all submissions thereafter.
> >
> > Signed-off-by: Chris Wilson 
> > Cc: Michal Wajdeczko 
> > Cc: Michał Winiarski 
> > ---
> >  drivers/gpu/drm/i915/intel_guc_submission.c | 2 ++
> >  1 file changed, 2 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c  
> > b/drivers/gpu/drm/i915/intel_guc_submission.c
> > index 97121230656c..a7957b669b68 100644
> > --- a/drivers/gpu/drm/i915/intel_guc_submission.c
> > +++ b/drivers/gpu/drm/i915/intel_guc_submission.c
> > @@ -758,6 +758,8 @@ static void guc_submission_tasklet(unsigned long  
> > data)
> >   struct execlist_port *port = execlists->port;
> >   struct i915_request *rq;
> > + GEM_BUG_ON(!READ_ONCE(engine->breadcrumbs.irq_enabled));
> > +
> >   rq = port_request(port);
> >   while (rq && i915_request_completed(rq)) {
> >   trace_i915_request_out(rq);
> 
> LGTM, but can you run this with GuC enabled ?

Are you afraid? If gem_eio isn't hitting this, I need to tweak gem_eio
;)
-Chris
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Enable display workaround 827 for all planes, v2.

[Patchwork]

== Series Details ==

Series: drm/i915: Enable display workaround 827 for all planes, v2.
URL   : https://patchwork.freedesktop.org/series/41371/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
b8f0788dfd3f drm/i915: Enable display workaround 827 for all planes, v2.
-:58: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#58: FILE: drivers/gpu/drm/i915/intel_display.c:5148:
+   if ((INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv)) ||
+  IS_CANNONLAKE(dev_priv))

total: 0 errors, 0 warnings, 1 checks, 95 lines checked

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Re: [Intel-gfx] [PATCH] drm/i915: Enable display workaround 827 for all planes, v2.

[Ville Syrjälä]

On Mon, Apr 09, 2018 at 04:21:23PM +0200, Maarten Lankhorst wrote:
> The workaround was applied only to the primary plane, but is required
> on all planes. Iterate over all planes in the crtc atomic check to see
> if the workaround is enabled, and only perform the actual toggling in
> the pre/post plane update functions.
> 
> Changes since v1:
> - Track active NV12 planes in a nv12_planes bitmask. (Ville)
> 
> Signed-off-by: Maarten Lankhorst 
> Cc: Ville Syrjälä 
> ---
>  drivers/gpu/drm/i915/intel_atomic_plane.c |  7 +-
>  drivers/gpu/drm/i915/intel_display.c  | 40 
> ++-
>  drivers/gpu/drm/i915/intel_drv.h  |  1 +
>  3 files changed, 30 insertions(+), 18 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c 
> b/drivers/gpu/drm/i915/intel_atomic_plane.c
> index 7481ce85746b..6d068786eb41 100644
> --- a/drivers/gpu/drm/i915/intel_atomic_plane.c
> +++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
> @@ -183,11 +183,16 @@ int intel_plane_atomic_check_with_state(const struct 
> intel_crtc_state *old_crtc_
>   }
>  
>   /* FIXME pre-g4x don't work like this */
> - if (intel_state->base.visible)
> + if (state->visible)
>   crtc_state->active_planes |= BIT(intel_plane->id);
>   else
>   crtc_state->active_planes &= ~BIT(intel_plane->id);
>  
> + if (state->visible && state->fb->format->format == DRM_FORMAT_NV12)
> + crtc_state->nv12_planes |= BIT(intel_plane->id);
> + else
> + crtc_state->nv12_planes &= ~BIT(intel_plane->id);
> +
>   return intel_plane_atomic_calc_changes(old_crtc_state,
>  _state->base,
>  old_plane_state,
> diff --git a/drivers/gpu/drm/i915/intel_display.c 
> b/drivers/gpu/drm/i915/intel_display.c
> index 487a6e235222..3039d00546c2 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5138,6 +5138,19 @@ static bool hsw_post_update_enable_ips(const struct 
> intel_crtc_state *old_crtc_s
>   return !old_crtc_state->ips_enabled;
>  }
>  
> +static bool needs_nv12_wa(struct drm_i915_private *dev_priv,
> +   const struct intel_crtc_state *crtc_state)
> +{
> + if (!crtc_state->nv12_planes)
> + return false;
> +
> + if ((INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv)) ||
> +IS_CANNONLAKE(dev_priv))
> + return true;
> +
> + return false;
> +}
> +
>  static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
>  {
>   struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
> @@ -5162,7 +5175,6 @@ static void intel_post_plane_update(struct 
> intel_crtc_state *old_crtc_state)
>   if (old_primary_state) {
>   struct drm_plane_state *new_primary_state =
>   drm_atomic_get_new_plane_state(old_state, primary);
> - struct drm_framebuffer *fb = new_primary_state->fb;
>  
>   intel_fbc_post_update(crtc);
>  
> @@ -5170,15 +5182,12 @@ static void intel_post_plane_update(struct 
> intel_crtc_state *old_crtc_state)
>   (needs_modeset(_config->base) ||
>!old_primary_state->visible))
>   intel_post_enable_primary(>base, pipe_config);
> -
> - /* Display WA 827 */
> - if ((INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv)) ||
> - IS_CANNONLAKE(dev_priv)) {
> - if (fb && fb->format->format == DRM_FORMAT_NV12)
> - skl_wa_clkgate(dev_priv, crtc->pipe, false);
> - }
> -
>   }
> +
> + /* Display WA 827 */
> + if (needs_nv12_wa(dev_priv, old_crtc_state) &&
> + !needs_nv12_wa(dev_priv, pipe_config))
> + skl_wa_clkgate(dev_priv, crtc->pipe, false);
>  }
>  
>  static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
> @@ -5202,14 +5211,6 @@ static void intel_pre_plane_update(struct 
> intel_crtc_state *old_crtc_state,
>   struct intel_plane_state *new_primary_state =
>   intel_atomic_get_new_plane_state(old_intel_state,
>
> to_intel_plane(primary));
> - struct drm_framebuffer *fb = new_primary_state->base.fb;
> -
> - /* Display WA 827 */
> - if ((INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv)) ||
> - IS_CANNONLAKE(dev_priv)) {
> - if (fb && fb->format->format == DRM_FORMAT_NV12)
> - skl_wa_clkgate(dev_priv, crtc->pipe, true);
> - }
>  
>   intel_fbc_pre_update(crtc, pipe_config, new_primary_state);
>   /*
> @@ -5221,6 +5222,11 @@ static void intel_pre_plane_update(struct 
> 

[Intel-gfx] [PATCH] drm/i915: Enable display workaround 827 for all planes, v2.

[Maarten Lankhorst]

The workaround was applied only to the primary plane, but is required
on all planes. Iterate over all planes in the crtc atomic check to see
if the workaround is enabled, and only perform the actual toggling in
the pre/post plane update functions.

Changes since v1:
- Track active NV12 planes in a nv12_planes bitmask. (Ville)

Signed-off-by: Maarten Lankhorst 
Cc: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_atomic_plane.c |  7 +-
 drivers/gpu/drm/i915/intel_display.c  | 40 ++-
 drivers/gpu/drm/i915/intel_drv.h  |  1 +
 3 files changed, 30 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c 
b/drivers/gpu/drm/i915/intel_atomic_plane.c
index 7481ce85746b..6d068786eb41 100644
--- a/drivers/gpu/drm/i915/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
@@ -183,11 +183,16 @@ int intel_plane_atomic_check_with_state(const struct 
intel_crtc_state *old_crtc_
}
 
/* FIXME pre-g4x don't work like this */
-   if (intel_state->base.visible)
+   if (state->visible)
crtc_state->active_planes |= BIT(intel_plane->id);
else
crtc_state->active_planes &= ~BIT(intel_plane->id);
 
+   if (state->visible && state->fb->format->format == DRM_FORMAT_NV12)
+   crtc_state->nv12_planes |= BIT(intel_plane->id);
+   else
+   crtc_state->nv12_planes &= ~BIT(intel_plane->id);
+
return intel_plane_atomic_calc_changes(old_crtc_state,
   _state->base,
   old_plane_state,
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 487a6e235222..3039d00546c2 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5138,6 +5138,19 @@ static bool hsw_post_update_enable_ips(const struct 
intel_crtc_state *old_crtc_s
return !old_crtc_state->ips_enabled;
 }
 
+static bool needs_nv12_wa(struct drm_i915_private *dev_priv,
+ const struct intel_crtc_state *crtc_state)
+{
+   if (!crtc_state->nv12_planes)
+   return false;
+
+   if ((INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv)) ||
+  IS_CANNONLAKE(dev_priv))
+   return true;
+
+   return false;
+}
+
 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
 {
struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
@@ -5162,7 +5175,6 @@ static void intel_post_plane_update(struct 
intel_crtc_state *old_crtc_state)
if (old_primary_state) {
struct drm_plane_state *new_primary_state =
drm_atomic_get_new_plane_state(old_state, primary);
-   struct drm_framebuffer *fb = new_primary_state->fb;
 
intel_fbc_post_update(crtc);
 
@@ -5170,15 +5182,12 @@ static void intel_post_plane_update(struct 
intel_crtc_state *old_crtc_state)
(needs_modeset(_config->base) ||
 !old_primary_state->visible))
intel_post_enable_primary(>base, pipe_config);
-
-   /* Display WA 827 */
-   if ((INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv)) ||
-   IS_CANNONLAKE(dev_priv)) {
-   if (fb && fb->format->format == DRM_FORMAT_NV12)
-   skl_wa_clkgate(dev_priv, crtc->pipe, false);
-   }
-
}
+
+   /* Display WA 827 */
+   if (needs_nv12_wa(dev_priv, old_crtc_state) &&
+   !needs_nv12_wa(dev_priv, pipe_config))
+   skl_wa_clkgate(dev_priv, crtc->pipe, false);
 }
 
 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
@@ -5202,14 +5211,6 @@ static void intel_pre_plane_update(struct 
intel_crtc_state *old_crtc_state,
struct intel_plane_state *new_primary_state =
intel_atomic_get_new_plane_state(old_intel_state,
 
to_intel_plane(primary));
-   struct drm_framebuffer *fb = new_primary_state->base.fb;
-
-   /* Display WA 827 */
-   if ((INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv)) ||
-   IS_CANNONLAKE(dev_priv)) {
-   if (fb && fb->format->format == DRM_FORMAT_NV12)
-   skl_wa_clkgate(dev_priv, crtc->pipe, true);
-   }
 
intel_fbc_pre_update(crtc, pipe_config, new_primary_state);
/*
@@ -5221,6 +5222,11 @@ static void intel_pre_plane_update(struct 
intel_crtc_state *old_crtc_state,
intel_set_cpu_fifo_underrun_reporting(dev_priv, 
crtc->pipe, false);
}
 
+   /* Display WA 827 */
+   if (!needs_nv12_wa(dev_priv, 

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/4] drm/i915: Change use get_new_plane_state instead of existing plane state

[Patchwork]

== Series Details ==

Series: series starting with [1/4] drm/i915: Change use get_new_plane_state 
instead of existing plane state
URL   : https://patchwork.freedesktop.org/series/41370/
State : success

== Summary ==

Series 41370v1 series starting with [1/4] drm/i915: Change use 
get_new_plane_state instead of existing plane state
https://patchwork.freedesktop.org/api/1.0/series/41370/revisions/1/mbox/

 Known issues:

Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-c:
pass   -> DMESG-WARN (fi-cnl-y3) fdo#104951

fdo#104951 https://bugs.freedesktop.org/show_bug.cgi?id=104951

fi-bdw-5557u total:285  pass:264  dwarn:0   dfail:0   fail:0   skip:21  
time:430s
fi-bdw-gvtdvmtotal:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:449s
fi-blb-e6850 total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  
time:382s
fi-bsw-n3050 total:285  pass:239  dwarn:0   dfail:0   fail:0   skip:46  
time:543s
fi-bwr-2160  total:285  pass:180  dwarn:0   dfail:0   fail:0   skip:105 
time:297s
fi-bxt-dsi   total:285  pass:255  dwarn:0   dfail:0   fail:0   skip:30  
time:516s
fi-bxt-j4205 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:519s
fi-byt-j1900 total:285  pass:250  dwarn:0   dfail:0   fail:0   skip:35  
time:520s
fi-byt-n2820 total:285  pass:246  dwarn:0   dfail:0   fail:0   skip:39  
time:514s
fi-cfl-8700k total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:414s
fi-cfl-s3total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:561s
fi-cfl-u total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:511s
fi-cnl-y3total:285  pass:258  dwarn:1   dfail:0   fail:0   skip:26  
time:580s
fi-elk-e7500 total:285  pass:226  dwarn:0   dfail:0   fail:0   skip:59  
time:424s
fi-gdg-551   total:285  pass:177  dwarn:0   dfail:0   fail:0   skip:108 
time:316s
fi-glk-1 total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:544s
fi-glk-j4005 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:483s
fi-hsw-4770  total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:410s
fi-ilk-650   total:285  pass:225  dwarn:0   dfail:0   fail:0   skip:60  
time:423s
fi-ivb-3520m total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:469s
fi-ivb-3770  total:285  pass:252  dwarn:0   dfail:0   fail:0   skip:33  
time:434s
fi-kbl-7500u total:285  pass:260  dwarn:1   dfail:0   fail:0   skip:24  
time:472s
fi-kbl-7567u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:466s
fi-kbl-r total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:508s
fi-pnv-d510  total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  
time:671s
fi-skl-6260u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:439s
fi-skl-6600u total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:542s
fi-skl-6700k2total:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:508s
fi-skl-6770hqtotal:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:501s
fi-skl-guc   total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:428s
fi-skl-gvtdvmtotal:285  pass:262  dwarn:0   dfail:0   fail:0   skip:23  
time:446s
fi-snb-2520m total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:590s
fi-snb-2600  total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:399s

e5a01dd0c5d224beec064e40184cc63a82ae79ce drm-tip: 2018y-04m-09d-12h-37m-09s UTC 
integration manifest
90d0615ca37a drm/i915: Enable display workaround 827 for all planes.
78e0056cb594 drm/i915: Remove last references to drm_atomic_get_existing* macros
2c8e55a34368 drm/i915: Remove get_existing_crtc_state
591b58b45998 drm/i915: Change use get_new_plane_state instead of existing plane 
state

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8643/issues.html
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Re: [Intel-gfx] [PATCH 15/36] drm/i915: Mark up Ironlake ips with rpm wakerefs

[Chris Wilson]

Quoting Sagar Arun Kamble (2018-03-16 06:04:03)
> i915_mch_val() called from i915_emon_status debugfs is not protected 
> under rpm_get and mchdev_lock.
> Can that also be updated as part of this patch.

Actually, we can just do that unlocked since we know that debugfs
teardown is itself serialised so inside i915_emon_status() we know
dev_priv is stable and not about to be freed.
-Chris
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Re: [Intel-gfx] [PATCH 6/7] drm/i915/dp: abstract link config selection

[Jani Nikula]

On Thu, 05 Apr 2018, Manasi Navare  wrote:
> On Thu, Apr 05, 2018 at 05:39:04PM +0300, Jani Nikula wrote:
>> For now, there's just the one link config selection, optimizing for slow
>> and wide link. No functional changes.
>> 
>> Signed-off-by: Jani Nikula 
>> ---
>>  drivers/gpu/drm/i915/intel_dp.c | 81 
>> +
>>  1 file changed, 50 insertions(+), 31 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/intel_dp.c 
>> b/drivers/gpu/drm/i915/intel_dp.c
>> index 3c5fbdf42b9b..c98626b3af65 100644
>> --- a/drivers/gpu/drm/i915/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/intel_dp.c
>> @@ -1704,6 +1704,42 @@ static bool intel_edp_compare_alt_mode(struct 
>> drm_display_mode *m1,
>>  return bres;
>>  }
>>  
>> +/* Optimize link config in order: max bpp, min clock, min lanes */
>> +static bool
>> +intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
>> +  struct intel_crtc_state *pipe_config,
>> +  const struct link_config_limits *limits)
>> +{
>> +struct drm_display_mode *adjusted_mode = 
>> _config->base.adjusted_mode;
>> +int bpp, clock, lane_count;
>> +int mode_rate, link_clock, link_avail;
>> +
>> +for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
>> +mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
>> +   bpp);
>> +
>> +for (clock = limits->min_clock; clock <= limits->max_clock; 
>> clock++) {
>> +for (lane_count = limits->min_lane_count;
>> + lane_count <= limits->max_lane_count;
>> + lane_count <<= 1) {
>> +link_clock = intel_dp->common_rates[clock];
>> +link_avail = intel_dp_max_data_rate(link_clock,
>> +lane_count);
>> +
>> +if (mode_rate <= link_avail) {
>> +pipe_config->lane_count = lane_count;
>> +pipe_config->pipe_bpp = bpp;
>> +pipe_config->port_clock = link_clock;
>> +
>> +return true;
>> +}
>> +}
>> +}
>> +}
>> +
>> +return false;
>> +}
>> +
>>  static bool
>>  intel_dp_compute_link_config(struct intel_encoder *encoder,
>>   struct intel_crtc_state *pipe_config)
>> @@ -1711,8 +1747,6 @@ intel_dp_compute_link_config(struct intel_encoder 
>> *encoder,
>>  struct drm_display_mode *adjusted_mode = 
>> _config->base.adjusted_mode;
>>  struct intel_dp *intel_dp = enc_to_intel_dp(>base);
>>  struct link_config_limits limits;
>> -int bpp, clock, lane_count;
>> -int mode_rate, link_avail, link_clock;
>>  int common_len;
>>  
>>  common_len = intel_dp_common_len_rate_limit(intel_dp,
>> @@ -1766,37 +1800,22 @@ intel_dp_compute_link_config(struct intel_encoder 
>> *encoder,
>>intel_dp->common_rates[limits.max_clock],
>>limits.max_bpp, adjusted_mode->crtc_clock);
>>  
>> -for (bpp = limits.max_bpp; bpp >= limits.min_bpp; bpp -= 2 * 3) {
>> -mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
>> -   bpp);
>> -
>> -for (clock = limits.min_clock; clock <= limits.max_clock; 
>> clock++) {
>> -for (lane_count = limits.min_lane_count;
>> - lane_count <= limits.max_lane_count;
>> - lane_count <<= 1) {
>> -
>> -link_clock = intel_dp->common_rates[clock];
>> -link_avail = intel_dp_max_data_rate(link_clock,
>> -lane_count);
>> -
>> -if (mode_rate <= link_avail) {
>> -goto found;
>> -}
>> -}
>> -}
>> -}
>> -
>> -return false;
>> -
>> -found:
>> -pipe_config->lane_count = lane_count;
>> -pipe_config->pipe_bpp = bpp;
>> -pipe_config->port_clock = intel_dp->common_rates[clock];
>> +/*
>> + * Optimize for slow and wide. This is the place to add alternative
>> + * optimization policy.
>> + */
>> +if (!intel_dp_compute_link_config_wide(intel_dp, pipe_config, ))
>> +return false;
>>  
>>  DRM_DEBUG_KMS("DP lane count %d clock %d bpp %d\n",
>> -  pipe_config->lane_count, pipe_config->port_clock, bpp);
>> -DRM_DEBUG_KMS("DP link bw required %i available %i\n",
>> -  mode_rate, link_avail);
>> +  pipe_config->lane_count, pipe_config->port_clock,
>> +  

Re: [Intel-gfx] [PATCH v8 08/12] drm/i915/uc: Fully sanitize uC within intel_uc_fini_hw

[Michal Wajdeczko]

On Mon, 09 Apr 2018 14:47:24 +0200, Chris Wilson  
 wrote:



Quoting Michal Wajdeczko (2018-04-09 13:23:28)

As we always call intel_uc_sanitize after every call to
intel_uc_fini_hw we may drop redundant call and sanitize
uC from the fini_hw function.

Signed-off-by: Michal Wajdeczko 
Cc: Sagar Arun Kamble 
Cc: Chris Wilson 


Not that it matters, since doing it before losing control or on resume
is the same from our pov, but I've always pencilled in sanitize as being
done on takeover (i.e. before init).


In intel_uc_init_hw we are already doing some semi-sanitization (thanks
to __intel_uc_reset_hw), but maybe to be more explicit, we should add
call to __uc_sanitize() in intel_uc_init_mmio() ?


Why do you favour after fini?


Hmm, not at all, I would call it just more explicit



Gut feeling prefers keeping it as a separate step rather rolling it up
into init/fini. But that's just because before we did sanitize
elsewhere, we had many strange bugs and those bugs have left their
scars (so I like seeing sanitize, it reminds me of dead bugs).


As now we have symmetrical inits/finis that cover all critical paths,
I don't think we need separate 'sanitize' step that could be called
any time/any place.

I assume extra __sanitize in uc_init_mmio should be enough reminder.

/michal
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Re: [Intel-gfx] [PATCH] drm/i915/guc: Check that the breadcrumb irq is enabled

[Michal Wajdeczko]

On Mon, 09 Apr 2018 14:42:19 +0200, Chris Wilson  
 wrote:



Our execlists emulation for GuC requires use of the breadcrumb following
every request as a simulcrum for the context-switch interrupt, which we
then use to drive the submission tasklet. Therefore, when we unpark the
engine for use with the GuC, we pin the breadcrumb interrupt to keep it
enabled for the duration. This has to be remain so across all resets,
wedging and resume, so check we do have the irq enabled when we start
submitting requests to the GuC and on all submissions thereafter.

Signed-off-by: Chris Wilson 
Cc: Michal Wajdeczko 
Cc: Michał Winiarski 
---
 drivers/gpu/drm/i915/intel_guc_submission.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c  
b/drivers/gpu/drm/i915/intel_guc_submission.c

index 97121230656c..a7957b669b68 100644
--- a/drivers/gpu/drm/i915/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/intel_guc_submission.c
@@ -758,6 +758,8 @@ static void guc_submission_tasklet(unsigned long  
data)

struct execlist_port *port = execlists->port;
struct i915_request *rq;
+   GEM_BUG_ON(!READ_ONCE(engine->breadcrumbs.irq_enabled));
+
rq = port_request(port);
while (rq && i915_request_completed(rq)) {
trace_i915_request_out(rq);


LGTM, but can you run this with GuC enabled ?

Thanks,
Michal
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Re: [Intel-gfx] [PATCH 15/36] drm/i915: Mark up Ironlake ips with rpm wakerefs

[Chris Wilson]

Quoting Sagar Arun Kamble (2018-03-16 04:58:22)
> 
> 
> On 3/14/2018 3:07 PM, Chris Wilson wrote:
> > Currently Ironlake operates under the assumption that rpm awake (and its
> > error checking is disabled). As such, we have missed a few places where we
> > access registers without taking the rpm wakeref and thus trigger
> > warnings. intel_ips being one culprit.
> >
> > As this involved adding a potentially sleeping rpm_get, we have to
> > rearrange the spinlocks slightly and so switch to acquiring a device-ref
> > under the spinlock rather than hold the spinlock for the whole
> > operation. To be consistent, we make the change in pattern common to the
> > intel_ips interface even though this adds a few more atomic operations
> > than necessary in a few cases.
> >
> > Signed-off-by: Chris Wilson 
> > ---
> >   drivers/gpu/drm/i915/i915_drv.c |   3 +
> >   drivers/gpu/drm/i915/intel_pm.c | 138 
> > 
> >   2 files changed, 73 insertions(+), 68 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.c 
> > b/drivers/gpu/drm/i915/i915_drv.c
> > index 3d0b7353fb09..5c28990aab7f 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.c
> > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > @@ -1440,6 +1440,9 @@ void i915_driver_unload(struct drm_device *dev)
> >   
> >   i915_driver_unregister(dev_priv);
> >   
> > + /* Flush any external code that still may be under the RCU lock */
> > + synchronize_rcu();
> > +
> Hi Chris,
> 
> Will this rcu change be equivalent to
> 
> rcu_assign_pointer(i915_mch_dev, dev_priv) in gpu_ips_init
> rcu_assign_pointer(i915_mch_dev, NULL) in gpu_ips_teardown
> 
> eliminating smp_store_mb from init/teardown and synchronize_rcu here.

We still have to go through the RCU period on teardown to be sure we
flush all readers, but yes, the store_mb can be reduce to
RCU_INIT_POINTER() and the mb are overkill as all we really need is the
ordering on init, and the explicit rcu sync on teardown.
-Chris
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Re: [Intel-gfx] [PATCH] drm/i915/audio: Fix audio detection issue on GLK

[Jani Nikula]

On Sun, 08 Apr 2018, Gaurav K Singh  wrote:
> On Geminilake, sometimes audio card is not getting
> detected after reboot. This is a spurious issue happening on
> Geminilake. HW codec and HD audio controller link was going
> out of sync for which there was a fix in i915 driver but
> was not getting invoked for GLK. Extending this fix to GLK as well.
>
> Tested by Du,Wenkai on GLK board.
>
> Signed-off-by: Gaurav K Singh 
> ---
>  drivers/gpu/drm/i915/intel_audio.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_audio.c 
> b/drivers/gpu/drm/i915/intel_audio.c
> index 656f6c931341..73b1e0b96f88 100644
> --- a/drivers/gpu/drm/i915/intel_audio.c
> +++ b/drivers/gpu/drm/i915/intel_audio.c
> @@ -729,7 +729,8 @@ static void 
> i915_audio_component_codec_wake_override(struct device *kdev,
>   struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
>   u32 tmp;
>  
> - if (!IS_GEN9_BC(dev_priv) && !IS_BROXTON(dev_priv))
> + if (!IS_GEN9_BC(dev_priv) && !IS_BROXTON(dev_priv) &&
> + !IS_GEMINILAKE(dev_priv))

That could be written as

if (!IS_GEN9_BC(dev_priv) && !IS_GEN9_LP(dev_priv))

which in turn could just be written as

if (!IS_GEN9(dev_priv))

...but since GLK has gen 10 display, so I'm wondering if the same issue
will be present in gen 10 too, and whether this should just become

if (INTEL_GEN(dev_priv) < 9)

BR,
Jani.



>   return;
>  
>   i915_audio_component_get_power(kdev);

-- 
Jani Nikula, Intel Open Source Technology Center
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Re: [Intel-gfx] [PATCH 3/4] drm/i915: Remove last references to drm_atomic_get_existing* macros

[Maarten Lankhorst]

Op 09-04-18 om 15:04 schreef Ville Syrjälä:
> On Mon, Apr 09, 2018 at 02:46:55PM +0200, Maarten Lankhorst wrote:
>> All the references to get_existing_state can be converted to
>> get_new_state or get_old_state, which means that i915 is now
>> get_existing_state free.
>>
>> Signed-off-by: Maarten Lankhorst 
>> ---
>>  drivers/gpu/drm/i915/intel_display.c | 51 
>> 
>>  1 file changed, 23 insertions(+), 28 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_display.c 
>> b/drivers/gpu/drm/i915/intel_display.c
>> index d42b635c6807..487a6e235222 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -5148,8 +5148,8 @@ static void intel_post_plane_update(struct 
>> intel_crtc_state *old_crtc_state)
>>  
>> intel_atomic_get_new_crtc_state(to_intel_atomic_state(old_state),
>>  crtc);
>>  struct drm_plane *primary = crtc->base.primary;
>> -struct drm_plane_state *old_pri_state =
>> -drm_atomic_get_existing_plane_state(old_state, primary);
>> +struct drm_plane_state *old_primary_state =
>> +drm_atomic_get_old_plane_state(old_state, primary);
>>  
>>  intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
>>  
>> @@ -5159,19 +5159,16 @@ static void intel_post_plane_update(struct 
>> intel_crtc_state *old_crtc_state)
>>  if (hsw_post_update_enable_ips(old_crtc_state, pipe_config))
>>  hsw_enable_ips(pipe_config);
>>  
>> -if (old_pri_state) {
>> -struct intel_plane_state *primary_state =
>> -
>> intel_atomic_get_new_plane_state(to_intel_atomic_state(old_state),
>> - 
>> to_intel_plane(primary));
>> -struct intel_plane_state *old_primary_state =
>> -to_intel_plane_state(old_pri_state);
>> -struct drm_framebuffer *fb = primary_state->base.fb;
>> +if (old_primary_state) {
>> +struct drm_plane_state *new_primary_state =
>> +drm_atomic_get_new_plane_state(old_state, primary);
>> +struct drm_framebuffer *fb = new_primary_state->fb;
>>  
>>  intel_fbc_post_update(crtc);
>>  
>> -if (primary_state->base.visible &&
>> +if (new_primary_state->visible &&
>>  (needs_modeset(_config->base) ||
>> - !old_primary_state->base.visible))
>> + !old_primary_state->visible))
>>  intel_post_enable_primary(>base, pipe_config);
>>  
>>  /* Display WA 827 */
>> @@ -5192,8 +5189,8 @@ static void intel_pre_plane_update(struct 
>> intel_crtc_state *old_crtc_state,
>>  struct drm_i915_private *dev_priv = to_i915(dev);
>>  struct drm_atomic_state *old_state = old_crtc_state->base.state;
>>  struct drm_plane *primary = crtc->base.primary;
>> -struct drm_plane_state *old_pri_state =
>> -drm_atomic_get_existing_plane_state(old_state, primary);
>> +struct drm_plane_state *old_primary_state =
>> +drm_atomic_get_old_plane_state(old_state, primary);
>>  bool modeset = needs_modeset(_config->base);
>>  struct intel_atomic_state *old_intel_state =
>>  to_intel_atomic_state(old_state);
>> @@ -5201,13 +5198,11 @@ static void intel_pre_plane_update(struct 
>> intel_crtc_state *old_crtc_state,
>>  if (hsw_pre_update_disable_ips(old_crtc_state, pipe_config))
>>  hsw_disable_ips(old_crtc_state);
>>  
>> -if (old_pri_state) {
>> -struct intel_plane_state *primary_state =
>> +if (old_primary_state) {
>> +struct intel_plane_state *new_primary_state =
>>  intel_atomic_get_new_plane_state(old_intel_state,
>>   
>> to_intel_plane(primary));
>> -struct intel_plane_state *old_primary_state =
>> -to_intel_plane_state(old_pri_state);
>> -struct drm_framebuffer *fb = primary_state->base.fb;
>> +struct drm_framebuffer *fb = new_primary_state->base.fb;
>>  
>>  /* Display WA 827 */
>>  if ((INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv)) ||
>> @@ -5216,13 +5211,13 @@ static void intel_pre_plane_update(struct 
>> intel_crtc_state *old_crtc_state,
>>  skl_wa_clkgate(dev_priv, crtc->pipe, true);
>>  }
>>  
>> -intel_fbc_pre_update(crtc, pipe_config, primary_state);
>> +intel_fbc_pre_update(crtc, pipe_config, new_primary_state);
>>  /*
>>   * Gen2 reports pipe underruns whenever all planes are disabled.
>>   * So disable underrun reporting before all the planes get 
>> disabled.
>>   */
>> -if (IS_GEN2(dev_priv) && old_primary_state->base.visible &&

Re: [Intel-gfx] [PATCH 12/36] drm/i915: Merge sbi read/write into a single accessor

[Chris Wilson]

Quoting Sagar Arun Kamble (2018-03-16 03:39:56)
> 
> 
> On 3/14/2018 3:07 PM, Chris Wilson wrote:
> > Since intel_sideband_read and intel_sideband_write differ by only a
> > couple of lines (depending on whether we feed the value in or out),
> > merge the two into a single common accessor.
> >
> > Signed-off-by: Chris Wilson 
> 
> > -u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg)
> vlv_flisdsi_read declaration can be removed from sideband.h

Oops, no, that was a rebase mistake. The API should not be affected by
this patch. That we have unused API..
-Chris
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/4] drm/i915: Change use get_new_plane_state instead of existing plane state

[Patchwork]

== Series Details ==

Series: series starting with [1/4] drm/i915: Change use get_new_plane_state 
instead of existing plane state
URL   : https://patchwork.freedesktop.org/series/41370/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
591b58b45998 drm/i915: Change use get_new_plane_state instead of existing plane 
state
2c8e55a34368 drm/i915: Remove get_existing_crtc_state
78e0056cb594 drm/i915: Remove last references to drm_atomic_get_existing* macros
-:142: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#142: FILE: drivers/gpu/drm/i915/intel_display.c:12795:
+   drm_atomic_get_new_crtc_state(new_state->state,
   plane->state->crtc);

total: 0 errors, 0 warnings, 1 checks, 115 lines checked
90d0615ca37a drm/i915: Enable display workaround 827 for all planes.

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Re: [Intel-gfx] [PATCH] drm/i915/gen9_lp: Increase DDI PHY0 power well enabling timeout

[Ville Syrjälä]

On Mon, Apr 09, 2018 at 03:27:16PM +0300, Imre Deak wrote:
> On GLK sporadic timeouts occur during PHY0 enabling. Based on logs it looks
> like they happen sometime after a system suspend/resume cycle, with the
> same power well enabling succeeding both before and after the failed
> one and no other problems observed. The current timeout in the code is
> not actually specified by BSpec, so let's try to increase that until a
> BSpec update.

Looks like we've always used 1ms on CHV. I couldn't find any specific
notes on how long we should poll in any of the CHV PHY docs. So I assume
we just picked 1ms since it seemed sufficient.

Doing the same for BXT/GLK seems reasonable to me.
Reviewed-by: Ville Syrjälä 

> 
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105771
> Signed-off-by: Imre Deak 
> ---
>  drivers/gpu/drm/i915/intel_dpio_phy.c | 11 ++-
>  1 file changed, 6 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c 
> b/drivers/gpu/drm/i915/intel_dpio_phy.c
> index c8e9e44e5981..00b3ab656b06 100644
> --- a/drivers/gpu/drm/i915/intel_dpio_phy.c
> +++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
> @@ -380,13 +380,14 @@ static void _bxt_ddi_phy_init(struct drm_i915_private 
> *dev_priv,
>* all 1s.  Eventually they become accessible as they power up, then
>* the reserved bit will give the default 0.  Poll on the reserved bit
>* becoming 0 to find when the PHY is accessible.
> -  * HW team confirmed that the time to reach phypowergood status is
> -  * anywhere between 50 us and 100us.
> +  * The flag should get set in 100us according to the HW team, but
> +  * use 1ms due to occasional timeouts observed with that.
>*/
> - if (wait_for_us(((I915_READ(BXT_PORT_CL1CM_DW0(phy)) &
> - (PHY_RESERVED | PHY_POWER_GOOD)) == PHY_POWER_GOOD), 100)) {
> + if (intel_wait_for_register_fw(dev_priv, BXT_PORT_CL1CM_DW0(phy),
> +PHY_RESERVED | PHY_POWER_GOOD,
> +PHY_POWER_GOOD,
> +1))
>   DRM_ERROR("timeout during PHY%d power on\n", phy);
> - }
>  
>   /* Program PLL Rcomp code offset */
>   val = I915_READ(BXT_PORT_CL1CM_DW9(phy));
> -- 
> 2.13.2
> 
> ___
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
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Intel OTC
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/guc: Check that the breadcrumb irq is enabled

[Patchwork]

== Series Details ==

Series: drm/i915/guc: Check that the breadcrumb irq is enabled
URL   : https://patchwork.freedesktop.org/series/41368/
State : success

== Summary ==

Series 41368v1 drm/i915/guc: Check that the breadcrumb irq is enabled
https://patchwork.freedesktop.org/api/1.0/series/41368/revisions/1/mbox/

 Known issues:

Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-c:
pass   -> INCOMPLETE (fi-bxt-dsi) fdo#103927

fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927

fi-bdw-5557u total:285  pass:264  dwarn:0   dfail:0   fail:0   skip:21  
time:427s
fi-bdw-gvtdvmtotal:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:441s
fi-blb-e6850 total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  
time:380s
fi-bsw-n3050 total:285  pass:239  dwarn:0   dfail:0   fail:0   skip:46  
time:537s
fi-bwr-2160  total:285  pass:180  dwarn:0   dfail:0   fail:0   skip:105 
time:295s
fi-bxt-dsi   total:243  pass:216  dwarn:0   dfail:0   fail:0   skip:26 
fi-bxt-j4205 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:515s
fi-byt-j1900 total:285  pass:250  dwarn:0   dfail:0   fail:0   skip:35  
time:525s
fi-byt-n2820 total:285  pass:246  dwarn:0   dfail:0   fail:0   skip:39  
time:509s
fi-cfl-8700k total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:410s
fi-cfl-s3total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:560s
fi-cfl-u total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:514s
fi-cnl-y3total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:586s
fi-elk-e7500 total:285  pass:226  dwarn:0   dfail:0   fail:0   skip:59  
time:426s
fi-gdg-551   total:285  pass:177  dwarn:0   dfail:0   fail:0   skip:108 
time:317s
fi-glk-1 total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:538s
fi-glk-j4005 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:487s
fi-hsw-4770  total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:404s
fi-ilk-650   total:285  pass:225  dwarn:0   dfail:0   fail:0   skip:60  
time:421s
fi-ivb-3520m total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:475s
fi-ivb-3770  total:285  pass:252  dwarn:0   dfail:0   fail:0   skip:33  
time:435s
fi-kbl-7500u total:285  pass:260  dwarn:1   dfail:0   fail:0   skip:24  
time:473s
fi-kbl-7567u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:466s
fi-kbl-r total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:511s
fi-pnv-d510  total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  
time:668s
fi-skl-6260u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:439s
fi-skl-6600u total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:530s
fi-skl-6700k2total:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:500s
fi-skl-6770hqtotal:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:505s
fi-skl-guc   total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:433s
fi-skl-gvtdvmtotal:285  pass:262  dwarn:0   dfail:0   fail:0   skip:23  
time:446s
fi-snb-2520m total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:578s
fi-snb-2600  total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:402s

e5a01dd0c5d224beec064e40184cc63a82ae79ce drm-tip: 2018y-04m-09d-12h-37m-09s UTC 
integration manifest
efbbf2bfa79b drm/i915/guc: Check that the breadcrumb irq is enabled

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8642/issues.html
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Re: [Intel-gfx] [PATCH] drm/i915/psr: vbt change for psr

[Jani Nikula]

On Fri, 06 Apr 2018, Rodrigo Vivi  wrote:
> On Fri, Apr 06, 2018 at 10:58:51PM +0530, vathsala nagaraju wrote:
>> From: Vathsala Nagaraju 
>> 
>> For psr block #9, the vbt description has moved to options [0-3] for
>> TP1,TP2,TP3 Wakeup time from decimal value without any change to vbt
>> structure. Since spec does not  mention from which VBT version this
>> change was added to vbt.bsf file, we cannot depend on bdb->version check
>> to change for all the platforms.
>> 
>> There is RCR inplace for GOP team to  provide the version number
>> to make generic change. Since Kabylake with bdb version 209 is having this
>> change, limiting this change to kbl and version 209+ to unblock google.
>> 
>> bspec 20131
>> 
>> Cc: Rodrigo Vivi 
>> CC: Puthikorn Voravootivat 
>> 
>> Signed-off-by: Maulik V Vaghela 
>> Signed-off-by: Vathsala Nagaraju 
>> ---
>>  drivers/gpu/drm/i915/i915_drv.h   |  1 +
>>  drivers/gpu/drm/i915/intel_bios.c |  2 +-
>>  drivers/gpu/drm/i915/intel_psr.c  | 84 
>> ++-
>>  3 files changed, 59 insertions(+), 28 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h 
>> b/drivers/gpu/drm/i915/i915_drv.h
>> index 5373b17..a47be19b 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -1075,6 +1075,7 @@ struct intel_vbt_data {
>>  enum psr_lines_to_wait lines_to_wait;
>>  int tp1_wakeup_time;
>>  int tp2_tp3_wakeup_time;
>> +int bdb_version;
>
> please keep the vbt stuff inside intel_bios.c
>
> so there at intel_bios.c you parse the vbt and based on the vbt version
> you export in a standard way to intel_psr.c

Exactly! struct intel_vbt_data is supposed to be an abstraction.

BR,
Jani.

>
>>  } psr;
>>  
>>  struct {
>> diff --git a/drivers/gpu/drm/i915/intel_bios.c 
>> b/drivers/gpu/drm/i915/intel_bios.c
>> index c5c7530..cfefd32 100644
>> --- a/drivers/gpu/drm/i915/intel_bios.c
>> +++ b/drivers/gpu/drm/i915/intel_bios.c
>> @@ -658,7 +658,7 @@ static int intel_bios_ssc_frequency(struct 
>> drm_i915_private *dev_priv,
>>  DRM_DEBUG_KMS("No PSR BDB found.\n");
>>  return;
>>  }
>> -
>> +dev_priv->vbt.psr.bdb_version = bdb->version;
>>  psr_table = >psr_table[panel_type];
>>  
>>  dev_priv->vbt.psr.full_link = psr_table->full_link;
>> diff --git a/drivers/gpu/drm/i915/intel_psr.c 
>> b/drivers/gpu/drm/i915/intel_psr.c
>> index 2d53f73..e470d5e 100644
>> --- a/drivers/gpu/drm/i915/intel_psr.c
>> +++ b/drivers/gpu/drm/i915/intel_psr.c
>> @@ -353,24 +353,45 @@ static void hsw_activate_psr1(struct intel_dp 
>> *intel_dp)
>>  if (dev_priv->psr.link_standby)
>>  val |= EDP_PSR_LINK_STANDBY;
>>  
>> -if (dev_priv->vbt.psr.tp1_wakeup_time > 5)
>> -val |= EDP_PSR_TP1_TIME_2500us;
>> -else if (dev_priv->vbt.psr.tp1_wakeup_time > 1)
>> -val |= EDP_PSR_TP1_TIME_500us;
>> -else if (dev_priv->vbt.psr.tp1_wakeup_time > 0)
>> -val |= EDP_PSR_TP1_TIME_100us;
>> -else
>> -val |= EDP_PSR_TP1_TIME_0us;
>> -
>> -if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
>> -val |= EDP_PSR_TP2_TP3_TIME_2500us;
>> -else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
>> -val |= EDP_PSR_TP2_TP3_TIME_500us;
>> -else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
>> -val |= EDP_PSR_TP2_TP3_TIME_100us;
>> -else
>> -val |= EDP_PSR_TP2_TP3_TIME_0us;
>> +if (dev_priv->vbt.psr.bdb_version >= 209 && IS_KABYLAKE(dev_priv)) {
>> +if (dev_priv->vbt.psr.tp1_wakeup_time == 0)
>> +val |= EDP_PSR_TP1_TIME_500us;
>> +else if (dev_priv->vbt.psr.tp1_wakeup_time == 1)
>> +val |= EDP_PSR_TP1_TIME_100us;
>> +else if (dev_priv->vbt.psr.tp1_wakeup_time == 2)
>> +val |= EDP_PSR_TP1_TIME_2500us;
>> +else
>> +val |= EDP_PSR_TP1_TIME_0us;
>> +} else {
>> +if (dev_priv->vbt.psr.tp1_wakeup_time > 5)
>> +val |= EDP_PSR_TP1_TIME_2500us;
>> +else if (dev_priv->vbt.psr.tp1_wakeup_time > 1)
>> +val |= EDP_PSR_TP1_TIME_500us;
>> +else if (dev_priv->vbt.psr.tp1_wakeup_time > 0)
>> +val |= EDP_PSR_TP1_TIME_100us;
>> +else
>> +val |= EDP_PSR_TP1_TIME_0us;
>> +}
>>  
>> +if (dev_priv->vbt.psr.bdb_version >= 209 && IS_KABYLAKE(dev_priv)) {
>> +if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 0)
>> +val |=  EDP_PSR_TP2_TP3_TIME_500us;
>> +else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 1)
>> +val |= EDP_PSR_TP2_TP3_TIME_100us;
>> +else if 

Re: [Intel-gfx] [PATCH 10/36] drm/i915: Replace pcu_lock with sb_lock

[Chris Wilson]

Quoting Sagar Arun Kamble (2018-03-15 12:06:57)
> On 3/14/2018 3:07 PM, Chris Wilson wrote:
> >   struct intel_rps {
> > + struct mutex lock;
> > +
> I think this lock can now become part of struct intel_gt_pm.

Maybe, haven't decided yet. Anything but rps is so infrequent as not to
really matter... And rps by the same metric deserves its own locking.

> >   /*
> >* work, interrupts_enabled and pm_iir are protected by
> >* dev_priv->irq_lock
> > @@ -1783,14 +1785,6 @@ struct drm_i915_private {
> >   /* Cannot be determined by PCIID. You must always read a register. */
> >   u32 edram_cap;
> >   
> > - /*
> > -  * Protects RPS/RC6 register access and PCU communication.
> > -  * Must be taken after struct_mutex if nested. Note that
> > -  * this lock may be held for long periods of time when
> > -  * talking to hw - so only take it when talking to hw!
> > -  */
> > - struct mutex pcu_lock;
> > -
> >   /* gen6+ GT PM state */
> >   struct intel_gen6_power_mgmt gt_pm;
> >   
> ...
> > -int sandybridge_pcode_write_timeout(struct drm_i915_private *dev_priv,
> > - u32 mbox, u32 val,
> > - int fast_timeout_us, int slow_timeout_ms)
> > +static int __sandybridge_pcode_write_timeout(struct drm_i915_private 
> > *dev_priv,
> > +  u32 mbox, u32 val,
> > +  int fast_timeout_us,
> > +  int slow_timeout_ms)
> >   {
> >   int status;
> >   
> > - WARN_ON(!mutex_is_locked(_priv->pcu_lock));
> > -
> lockdep_assert is missed here.

Because it is now static with its only pair of users immediately after,
so easy to verify both callers take the sb_lock (pair when we reduce
this to the common rw routine).
-Chris
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Re: [Intel-gfx] [PATCH 08/36] drm/i915: Reduce RPS update frequency on Valleyview/Cherryview

[Chris Wilson]

Quoting Sagar Arun Kamble (2018-03-15 09:23:25)
> 
> 
> On 3/14/2018 3:07 PM, Chris Wilson wrote:
> > Valleyview and Cherryview update the GPU frequency via the punit, which
> > is very expensive as we have to ensure the cores do not sleep during the
> > comms.
> But the patch 5 applies this workaround to only VLV.

Still using an indirect method that uses a RTT, so still true that the
punit access is noticeable.
-Chris
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[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] drm/i915/selftests: Extend partial vma coverage to check parallel creation

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915/selftests: Extend partial vma 
coverage to check parallel creation
URL   : https://patchwork.freedesktop.org/series/41359/
State : failure

== Summary ==

 Possible new issues:

Test drv_selftest:
Subgroup mock_vma:
pass   -> DMESG-FAIL (shard-hsw)
Test gem_pwrite:
Subgroup big-gtt-backwards:
skip   -> PASS   (shard-apl)

 Known issues:

Test kms_flip:
Subgroup 2x-flip-vs-expired-vblank-interruptible:
fail   -> PASS   (shard-hsw) fdo#102887
Subgroup 2x-plain-flip-fb-recreate:
fail   -> PASS   (shard-hsw) fdo#100368
Subgroup modeset-vs-vblank-race-interruptible:
pass   -> FAIL   (shard-hsw) fdo#103060 +1
Test kms_sysfs_edid_timing:
pass   -> WARN   (shard-apl) fdo#100047

fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047

shard-apltotal:2680 pass:1835 dwarn:1   dfail:0   fail:7   skip:836 
time:12777s
shard-hswtotal:2680 pass:1783 dwarn:1   dfail:1   fail:3   skip:891 
time:11456s
Blacklisted hosts:
shard-kbltotal:2680 pass:1960 dwarn:1   dfail:0   fail:9   skip:710 
time:9198s
shard-snbtotal:2680 pass:1377 dwarn:1   dfail:0   fail:3   skip:1299 
time:6941s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8639/shards.html
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gen9_lp: Increase DDI PHY0 power well enabling timeout

[Patchwork]

== Series Details ==

Series: drm/i915/gen9_lp: Increase DDI PHY0 power well enabling timeout
URL   : https://patchwork.freedesktop.org/series/41366/
State : success

== Summary ==

Series 41366v1 drm/i915/gen9_lp: Increase DDI PHY0 power well enabling timeout
https://patchwork.freedesktop.org/api/1.0/series/41366/revisions/1/mbox/

 Known issues:

Test gem_mmap_gtt:
Subgroup basic-small-bo-tiledx:
pass   -> FAIL   (fi-gdg-551) fdo#102575
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-c:
pass   -> INCOMPLETE (fi-bxt-dsi) fdo#103927
Test prime_vgem:
Subgroup basic-fence-flip:
pass   -> FAIL   (fi-ilk-650) fdo#104008

fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008

fi-bdw-5557u total:285  pass:264  dwarn:0   dfail:0   fail:0   skip:21  
time:430s
fi-bdw-gvtdvmtotal:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:446s
fi-blb-e6850 total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  
time:382s
fi-bsw-n3050 total:285  pass:239  dwarn:0   dfail:0   fail:0   skip:46  
time:536s
fi-bwr-2160  total:285  pass:180  dwarn:0   dfail:0   fail:0   skip:105 
time:299s
fi-bxt-dsi   total:243  pass:216  dwarn:0   dfail:0   fail:0   skip:26 
fi-bxt-j4205 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:512s
fi-byt-j1900 total:285  pass:250  dwarn:0   dfail:0   fail:0   skip:35  
time:521s
fi-byt-n2820 total:285  pass:246  dwarn:0   dfail:0   fail:0   skip:39  
time:508s
fi-cfl-8700k total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:409s
fi-cfl-s3total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:562s
fi-cfl-u total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:511s
fi-cnl-y3total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:587s
fi-elk-e7500 total:285  pass:226  dwarn:0   dfail:0   fail:0   skip:59  
time:425s
fi-gdg-551   total:285  pass:176  dwarn:0   dfail:0   fail:1   skip:108 
time:317s
fi-glk-1 total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:539s
fi-glk-j4005 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:487s
fi-hsw-4770  total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:411s
fi-ilk-650   total:285  pass:224  dwarn:0   dfail:0   fail:1   skip:60  
time:421s
fi-ivb-3520m total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:481s
fi-ivb-3770  total:285  pass:252  dwarn:0   dfail:0   fail:0   skip:33  
time:433s
fi-kbl-7500u total:285  pass:260  dwarn:1   dfail:0   fail:0   skip:24  
time:472s
fi-kbl-7567u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:463s
fi-kbl-r total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:519s
fi-pnv-d510  total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  
time:668s
fi-skl-6260u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:446s
fi-skl-6600u total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:531s
fi-skl-6700k2total:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:500s
fi-skl-6770hqtotal:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:504s
fi-skl-guc   total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:430s
fi-skl-gvtdvmtotal:285  pass:262  dwarn:0   dfail:0   fail:0   skip:23  
time:442s
fi-snb-2520m total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:572s
fi-snb-2600  total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:406s

e5a01dd0c5d224beec064e40184cc63a82ae79ce drm-tip: 2018y-04m-09d-12h-37m-09s UTC 
integration manifest
031e10c34d8a drm/i915/gen9_lp: Increase DDI PHY0 power well enabling timeout

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8641/issues.html
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Re: [Intel-gfx] [PATCH 4/4] drm/i915: Enable display workaround 827 for all planes.

[Ville Syrjälä]

On Mon, Apr 09, 2018 at 02:46:56PM +0200, Maarten Lankhorst wrote:
> The workaround was applied only to the primary plane, but is required
> on all planes. Iterate over all planes in the crtc atomic check to see
> if the workaround is enabled, and only perform the actual toggling in
> the pre/post plane update functions.
> 
> Signed-off-by: Maarten Lankhorst 
> ---
>  drivers/gpu/drm/i915/intel_display.c | 40 
> +---
>  drivers/gpu/drm/i915/intel_drv.h |  1 +
>  2 files changed, 24 insertions(+), 17 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c 
> b/drivers/gpu/drm/i915/intel_display.c
> index 487a6e235222..829b593a3cee 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5162,7 +5162,6 @@ static void intel_post_plane_update(struct 
> intel_crtc_state *old_crtc_state)
>   if (old_primary_state) {
>   struct drm_plane_state *new_primary_state =
>   drm_atomic_get_new_plane_state(old_state, primary);
> - struct drm_framebuffer *fb = new_primary_state->fb;
>  
>   intel_fbc_post_update(crtc);
>  
> @@ -5170,15 +5169,11 @@ static void intel_post_plane_update(struct 
> intel_crtc_state *old_crtc_state)
>   (needs_modeset(_config->base) ||
>!old_primary_state->visible))
>   intel_post_enable_primary(>base, pipe_config);
> -
> - /* Display WA 827 */
> - if ((INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv)) ||
> - IS_CANNONLAKE(dev_priv)) {
> - if (fb && fb->format->format == DRM_FORMAT_NV12)
> - skl_wa_clkgate(dev_priv, crtc->pipe, false);
> - }
> -
>   }
> +
> + /* Display WA 827 */
> + if (old_crtc_state->nv12_wa && !pipe_config->nv12_wa)
> + skl_wa_clkgate(dev_priv, crtc->pipe, false);
>  }
>  
>  static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
> @@ -5202,14 +5197,6 @@ static void intel_pre_plane_update(struct 
> intel_crtc_state *old_crtc_state,
>   struct intel_plane_state *new_primary_state =
>   intel_atomic_get_new_plane_state(old_intel_state,
>
> to_intel_plane(primary));
> - struct drm_framebuffer *fb = new_primary_state->base.fb;
> -
> - /* Display WA 827 */
> - if ((INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv)) ||
> - IS_CANNONLAKE(dev_priv)) {
> - if (fb && fb->format->format == DRM_FORMAT_NV12)
> - skl_wa_clkgate(dev_priv, crtc->pipe, true);
> - }
>  
>   intel_fbc_pre_update(crtc, pipe_config, new_primary_state);
>   /*
> @@ -5221,6 +5208,10 @@ static void intel_pre_plane_update(struct 
> intel_crtc_state *old_crtc_state,
>   intel_set_cpu_fifo_underrun_reporting(dev_priv, 
> crtc->pipe, false);
>   }
>  
> + /* Display WA 827 */
> + if (!old_crtc_state->nv12_wa && pipe_config->nv12_wa)
> + skl_wa_clkgate(dev_priv, crtc->pipe, true);
> +
>   /*
>* Vblank time updates from the shadow to live plane control register
>* are blocked if the memory self-refresh mode is active at that
> @@ -10485,6 +10476,21 @@ static int intel_crtc_atomic_check(struct drm_crtc 
> *crtc,
>   return ret;
>   }
>  
> + pipe_config->nv12_wa = false;
> +
> + /* Apply display WA 827 if required. */
> + if (crtc_state->active &&
> + ((INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv)) ||
> +  IS_CANNONLAKE(dev_priv))) {

GLK doesn't need this? That seems odd to say the least.

> + struct drm_plane *plane;
> + const struct drm_plane_state *plane_state;
> +
> + drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, 
> crtc_state)

I'd prefer a bitmask instead of that sneaky peeking of the plane states.

It should also avoid polluting this sort of central/generic piece of
code with platform specific w/as.

> + if (plane_state->fb &&
> + plane_state->fb->format->format == DRM_FORMAT_NV12)
> + pipe_config->nv12_wa = true;
> + }
> +
>   if (crtc_state->color_mgmt_changed) {
>   ret = intel_color_check(crtc, crtc_state);
>   if (ret)
> diff --git a/drivers/gpu/drm/i915/intel_drv.h 
> b/drivers/gpu/drm/i915/intel_drv.h
> index 9969309132d0..9c2b7f78d5dd 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -723,6 +723,7 @@ struct intel_crtc_state {
>   bool update_wm_pre, update_wm_post; /* watermarks are updated */
>   bool fb_changed; /* fb on any of the planes is changed */
>   bool 

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [01/18] drm/i915/execlists: Set queue priority from secondary port

[Patchwork]

== Series Details ==

Series: series starting with [01/18] drm/i915/execlists: Set queue priority 
from secondary port
URL   : https://patchwork.freedesktop.org/series/41357/
State : failure

== Summary ==

 Possible new issues:

Test gem_ctx_param:
Subgroup invalid-param-get:
pass   -> FAIL   (shard-apl)
pass   -> FAIL   (shard-hsw)
Subgroup invalid-param-set:
pass   -> FAIL   (shard-apl)
pass   -> FAIL   (shard-hsw)
Test gem_pwrite:
Subgroup big-gtt-backwards:
skip   -> PASS   (shard-apl)

 Known issues:

Test kms_flip:
Subgroup 2x-flip-vs-expired-vblank-interruptible:
fail   -> PASS   (shard-hsw) fdo#102887 +1
Subgroup plain-flip-fb-recreate-interruptible:
pass   -> FAIL   (shard-hsw) fdo#100368 +2

fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368

shard-apltotal:2680 pass:1833 dwarn:1   dfail:1   fail:9   skip:836 
time:12708s
shard-hswtotal:2680 pass:1781 dwarn:1   dfail:0   fail:6   skip:891 
time:11341s
Blacklisted hosts:
shard-kbltotal:2680 pass:1960 dwarn:1   dfail:1   fail:9   skip:709 
time:9215s
shard-snbtotal:2680 pass:1375 dwarn:1   dfail:0   fail:5   skip:1299 
time:6916s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8638/shards.html
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Re: [Intel-gfx] [PATCH 3/4] drm/i915: Remove last references to drm_atomic_get_existing* macros

[Ville Syrjälä]

On Mon, Apr 09, 2018 at 02:46:55PM +0200, Maarten Lankhorst wrote:
> All the references to get_existing_state can be converted to
> get_new_state or get_old_state, which means that i915 is now
> get_existing_state free.
> 
> Signed-off-by: Maarten Lankhorst 
> ---
>  drivers/gpu/drm/i915/intel_display.c | 51 
> 
>  1 file changed, 23 insertions(+), 28 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c 
> b/drivers/gpu/drm/i915/intel_display.c
> index d42b635c6807..487a6e235222 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5148,8 +5148,8 @@ static void intel_post_plane_update(struct 
> intel_crtc_state *old_crtc_state)
>   
> intel_atomic_get_new_crtc_state(to_intel_atomic_state(old_state),
>   crtc);
>   struct drm_plane *primary = crtc->base.primary;
> - struct drm_plane_state *old_pri_state =
> - drm_atomic_get_existing_plane_state(old_state, primary);
> + struct drm_plane_state *old_primary_state =
> + drm_atomic_get_old_plane_state(old_state, primary);
>  
>   intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
>  
> @@ -5159,19 +5159,16 @@ static void intel_post_plane_update(struct 
> intel_crtc_state *old_crtc_state)
>   if (hsw_post_update_enable_ips(old_crtc_state, pipe_config))
>   hsw_enable_ips(pipe_config);
>  
> - if (old_pri_state) {
> - struct intel_plane_state *primary_state =
> - 
> intel_atomic_get_new_plane_state(to_intel_atomic_state(old_state),
> -  
> to_intel_plane(primary));
> - struct intel_plane_state *old_primary_state =
> - to_intel_plane_state(old_pri_state);
> - struct drm_framebuffer *fb = primary_state->base.fb;
> + if (old_primary_state) {
> + struct drm_plane_state *new_primary_state =
> + drm_atomic_get_new_plane_state(old_state, primary);
> + struct drm_framebuffer *fb = new_primary_state->fb;
>  
>   intel_fbc_post_update(crtc);
>  
> - if (primary_state->base.visible &&
> + if (new_primary_state->visible &&
>   (needs_modeset(_config->base) ||
> -  !old_primary_state->base.visible))
> +  !old_primary_state->visible))
>   intel_post_enable_primary(>base, pipe_config);
>  
>   /* Display WA 827 */
> @@ -5192,8 +5189,8 @@ static void intel_pre_plane_update(struct 
> intel_crtc_state *old_crtc_state,
>   struct drm_i915_private *dev_priv = to_i915(dev);
>   struct drm_atomic_state *old_state = old_crtc_state->base.state;
>   struct drm_plane *primary = crtc->base.primary;
> - struct drm_plane_state *old_pri_state =
> - drm_atomic_get_existing_plane_state(old_state, primary);
> + struct drm_plane_state *old_primary_state =
> + drm_atomic_get_old_plane_state(old_state, primary);
>   bool modeset = needs_modeset(_config->base);
>   struct intel_atomic_state *old_intel_state =
>   to_intel_atomic_state(old_state);
> @@ -5201,13 +5198,11 @@ static void intel_pre_plane_update(struct 
> intel_crtc_state *old_crtc_state,
>   if (hsw_pre_update_disable_ips(old_crtc_state, pipe_config))
>   hsw_disable_ips(old_crtc_state);
>  
> - if (old_pri_state) {
> - struct intel_plane_state *primary_state =
> + if (old_primary_state) {
> + struct intel_plane_state *new_primary_state =
>   intel_atomic_get_new_plane_state(old_intel_state,
>
> to_intel_plane(primary));
> - struct intel_plane_state *old_primary_state =
> - to_intel_plane_state(old_pri_state);
> - struct drm_framebuffer *fb = primary_state->base.fb;
> + struct drm_framebuffer *fb = new_primary_state->base.fb;
>  
>   /* Display WA 827 */
>   if ((INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv)) ||
> @@ -5216,13 +5211,13 @@ static void intel_pre_plane_update(struct 
> intel_crtc_state *old_crtc_state,
>   skl_wa_clkgate(dev_priv, crtc->pipe, true);
>   }
>  
> - intel_fbc_pre_update(crtc, pipe_config, primary_state);
> + intel_fbc_pre_update(crtc, pipe_config, new_primary_state);
>   /*
>* Gen2 reports pipe underruns whenever all planes are disabled.
>* So disable underrun reporting before all the planes get 
> disabled.
>*/
> - if (IS_GEN2(dev_priv) && old_primary_state->base.visible &&
> - (modeset || !primary_state->base.visible))
> + if 

Re: [Intel-gfx] [PATCH 2/4] drm/i915: Remove get_existing_crtc_state

[Ville Syrjälä]

On Mon, Apr 09, 2018 at 02:46:54PM +0200, Maarten Lankhorst wrote:
> get_existing_crtc_state is currently unused, get rid of it.
> 
> Signed-off-by: Maarten Lankhorst 

Reviewed-by: Ville Syrjälä 

> ---
>  drivers/gpu/drm/i915/intel_drv.h | 14 --
>  1 file changed, 14 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_drv.h 
> b/drivers/gpu/drm/i915/intel_drv.h
> index e545aa673bd9..9969309132d0 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -2095,20 +2095,6 @@ intel_atomic_get_crtc_state(struct drm_atomic_state 
> *state,
>   return to_intel_crtc_state(crtc_state);
>  }
>  
> -static inline struct intel_crtc_state *
> -intel_atomic_get_existing_crtc_state(struct drm_atomic_state *state,
> -  struct intel_crtc *crtc)
> -{
> - struct drm_crtc_state *crtc_state;
> -
> - crtc_state = drm_atomic_get_existing_crtc_state(state, >base);
> -
> - if (crtc_state)
> - return to_intel_crtc_state(crtc_state);
> - else
> - return NULL;
> -}
> -
>  int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
>  struct intel_crtc *intel_crtc,
>  struct intel_crtc_state *crtc_state);
> -- 
> 2.16.3
> 
> ___
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Re: [Intel-gfx] [PATCH 1/4] drm/i915: Change use get_new_plane_state instead of existing plane state

[Ville Syrjälä]

On Mon, Apr 09, 2018 at 02:46:53PM +0200, Maarten Lankhorst wrote:
> The get_existing macros are deprecated and should be replaced by
> get_old/new_state for clarity.
> 
> Signed-off-by: Maarten Lankhorst 
> ---
>  drivers/gpu/drm/i915/intel_atomic.c |  5 +++--
>  drivers/gpu/drm/i915/intel_drv.h| 11 ---
>  drivers/gpu/drm/i915/intel_pm.c |  2 +-
>  3 files changed, 4 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_atomic.c 
> b/drivers/gpu/drm/i915/intel_atomic.c
> index bb8c1687823e..40285d1b91b7 100644
> --- a/drivers/gpu/drm/i915/intel_atomic.c
> +++ b/drivers/gpu/drm/i915/intel_atomic.c
> @@ -227,6 +227,7 @@ int intel_atomic_setup_scalers(struct drm_i915_private 
> *dev_priv,
>   struct intel_crtc_scaler_state *scaler_state =
>   _state->scaler_state;
>   struct drm_atomic_state *drm_state = crtc_state->base.state;
> + struct intel_atomic_state *intel_state = 
> to_intel_atomic_state(drm_state);
>   int num_scalers_need;
>   int i, j;
>  
> @@ -304,8 +305,8 @@ int intel_atomic_setup_scalers(struct drm_i915_private 
> *dev_priv,
>   continue;
>   }
>  
> - plane_state = 
> intel_atomic_get_existing_plane_state(drm_state,
> - 
> intel_plane);
> + plane_state = 
> intel_atomic_get_new_plane_state(intel_state,
> +
> intel_plane);
>   scaler_id = _state->scaler_id;
>   }
>  
> diff --git a/drivers/gpu/drm/i915/intel_drv.h 
> b/drivers/gpu/drm/i915/intel_drv.h
> index b2e0fa04ef5b..e545aa673bd9 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -2109,17 +2109,6 @@ intel_atomic_get_existing_crtc_state(struct 
> drm_atomic_state *state,
>   return NULL;
>  }
>  
> -static inline struct intel_plane_state *
> -intel_atomic_get_existing_plane_state(struct drm_atomic_state *state,
> -   struct intel_plane *plane)
> -{
> - struct drm_plane_state *plane_state;
> -
> - plane_state = drm_atomic_get_existing_plane_state(state, >base);
> -
> - return to_intel_plane_state(plane_state);
> -}
> -
>  int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
>  struct intel_crtc *intel_crtc,
>  struct intel_crtc_state *crtc_state);
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 007a12ebe725..fb24b44ec37f 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -5037,7 +5037,7 @@ skl_ddb_add_affected_planes(struct intel_crtc_state 
> *cstate)
>   struct drm_plane *plane;
>   enum pipe pipe = intel_crtc->pipe;
>  
> - WARN_ON(!drm_atomic_get_existing_crtc_state(state, crtc));
> + WARN_ON(!drm_atomic_get_new_crtc_state(state, crtc));

This assert seems rather pointless since we got the drm_atomic_state via
cstate->base.state.

Anyways, patch is
Reviewed-by: Ville Syrjälä 

>  
>   drm_for_each_plane_mask(plane, dev, cstate->base.plane_mask) {
>   enum plane_id plane_id = to_intel_plane(plane)->id;
> -- 
> 2.16.3
> 
> ___
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> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v8,01/12] drm/i915: Park before resetting the submission backend

[Patchwork]

== Series Details ==

Series: series starting with [v8,01/12] drm/i915: Park before resetting the 
submission backend
URL   : https://patchwork.freedesktop.org/series/41365/
State : success

== Summary ==

Series 41365v1 series starting with [v8,01/12] drm/i915: Park before resetting 
the submission backend
https://patchwork.freedesktop.org/api/1.0/series/41365/revisions/1/mbox/

 Known issues:

Test gem_mmap_gtt:
Subgroup basic-small-bo-tiledx:
fail   -> PASS   (fi-gdg-551) fdo#102575
Test kms_flip:
Subgroup basic-flip-vs-wf_vblank:
pass   -> FAIL   (fi-cfl-s3) fdo#100368
Test prime_vgem:
Subgroup basic-fence-flip:
fail   -> PASS   (fi-ilk-650) fdo#104008

fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008

fi-bdw-5557u total:285  pass:264  dwarn:0   dfail:0   fail:0   skip:21  
time:435s
fi-bdw-gvtdvmtotal:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:447s
fi-blb-e6850 total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  
time:380s
fi-bsw-n3050 total:285  pass:239  dwarn:0   dfail:0   fail:0   skip:46  
time:541s
fi-bwr-2160  total:285  pass:180  dwarn:0   dfail:0   fail:0   skip:105 
time:296s
fi-bxt-dsi   total:285  pass:255  dwarn:0   dfail:0   fail:0   skip:30  
time:513s
fi-bxt-j4205 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:517s
fi-byt-j1900 total:285  pass:250  dwarn:0   dfail:0   fail:0   skip:35  
time:526s
fi-byt-n2820 total:285  pass:246  dwarn:0   dfail:0   fail:0   skip:39  
time:506s
fi-cfl-8700k total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:410s
fi-cfl-s3total:285  pass:258  dwarn:0   dfail:0   fail:1   skip:26  
time:554s
fi-cfl-u total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:511s
fi-cnl-y3total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:583s
fi-elk-e7500 total:285  pass:226  dwarn:0   dfail:0   fail:0   skip:59  
time:426s
fi-gdg-551   total:285  pass:177  dwarn:0   dfail:0   fail:0   skip:108 
time:314s
fi-glk-1 total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:536s
fi-glk-j4005 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:488s
fi-hsw-4770  total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:409s
fi-ilk-650   total:285  pass:225  dwarn:0   dfail:0   fail:0   skip:60  
time:420s
fi-ivb-3520m total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:471s
fi-ivb-3770  total:285  pass:252  dwarn:0   dfail:0   fail:0   skip:33  
time:434s
fi-kbl-7500u total:285  pass:260  dwarn:1   dfail:0   fail:0   skip:24  
time:474s
fi-kbl-7567u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:461s
fi-kbl-r total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:508s
fi-pnv-d510  total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  
time:670s
fi-skl-6260u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:444s
fi-skl-6600u total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:540s
fi-skl-6700k2total:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:498s
fi-skl-6770hqtotal:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:508s
fi-skl-guc   total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:431s
fi-skl-gvtdvmtotal:285  pass:262  dwarn:0   dfail:0   fail:0   skip:23  
time:443s
fi-snb-2520m total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:586s
fi-snb-2600  total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:405s

6eef2aa99feb6e37e6252c0a0ddb78966a0b23dd drm-tip: 2018y-04m-09d-11h-44m-50s UTC 
integration manifest
058d4d58c467 HAX: Enable GuC for CI
2f326fb7 drm/i915/uc: Trivial s/dev_priv/i915 in intel_uc.c
38d4bebc3c54 drm/i915/uc: Use helper functions to detect fw load status
ecd487066952 drm/i915/uc: Use correct error code for GuC initialization failure
174c75f27d90 drm/i915/uc: Fully sanitize uC within intel_uc_fini_hw
8f30a658e3ce drm/i915/guc: Restore symmetric doorbell cleanup
2298ffab92ec drm/i915: Add i915_gem_fini_hw to i915_reset
2d5745d4f14e drm/i915: Add i915_gem_fini_hw to i915_gem_suspend
d70c468442f3 drm/i915: Introduce i915_gem_fini_hw for symmetry with 
i915_gem_init_hw
2ae7ae86b3c4 drm/i915: Move i915_gem_fini to i915_gem.c
bcc6baad8bda drm/i915: Correctly handle error path in i915_gem_init_hw
7d8134ca6ba3 drm/i915: Park before resetting the submission backend

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8640/issues.html
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[Intel-gfx] [PATCH 2/4] drm/i915: Remove get_existing_crtc_state

[Maarten Lankhorst]

get_existing_crtc_state is currently unused, get rid of it.

Signed-off-by: Maarten Lankhorst 
---
 drivers/gpu/drm/i915/intel_drv.h | 14 --
 1 file changed, 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index e545aa673bd9..9969309132d0 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -2095,20 +2095,6 @@ intel_atomic_get_crtc_state(struct drm_atomic_state 
*state,
return to_intel_crtc_state(crtc_state);
 }
 
-static inline struct intel_crtc_state *
-intel_atomic_get_existing_crtc_state(struct drm_atomic_state *state,
-struct intel_crtc *crtc)
-{
-   struct drm_crtc_state *crtc_state;
-
-   crtc_state = drm_atomic_get_existing_crtc_state(state, >base);
-
-   if (crtc_state)
-   return to_intel_crtc_state(crtc_state);
-   else
-   return NULL;
-}
-
 int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
   struct intel_crtc *intel_crtc,
   struct intel_crtc_state *crtc_state);
-- 
2.16.3

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Re: [Intel-gfx] [PATCH v8 08/12] drm/i915/uc: Fully sanitize uC within intel_uc_fini_hw

[Chris Wilson]

Quoting Michal Wajdeczko (2018-04-09 13:23:28)
> As we always call intel_uc_sanitize after every call to
> intel_uc_fini_hw we may drop redundant call and sanitize
> uC from the fini_hw function.
> 
> Signed-off-by: Michal Wajdeczko 
> Cc: Sagar Arun Kamble 
> Cc: Chris Wilson 

Not that it matters, since doing it before losing control or on resume
is the same from our pov, but I've always pencilled in sanitize as being
done on takeover (i.e. before init). Why do you favour after fini?

Gut feeling prefers keeping it as a separate step rather rolling it up
into init/fini. But that's just because before we did sanitize
elsewhere, we had many strange bugs and those bugs have left their
scars (so I like seeing sanitize, it reminds me of dead bugs).
-Chris
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[Intel-gfx] [PATCH 4/4] drm/i915: Enable display workaround 827 for all planes.

[Maarten Lankhorst]

The workaround was applied only to the primary plane, but is required
on all planes. Iterate over all planes in the crtc atomic check to see
if the workaround is enabled, and only perform the actual toggling in
the pre/post plane update functions.

Signed-off-by: Maarten Lankhorst 
---
 drivers/gpu/drm/i915/intel_display.c | 40 +---
 drivers/gpu/drm/i915/intel_drv.h |  1 +
 2 files changed, 24 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 487a6e235222..829b593a3cee 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5162,7 +5162,6 @@ static void intel_post_plane_update(struct 
intel_crtc_state *old_crtc_state)
if (old_primary_state) {
struct drm_plane_state *new_primary_state =
drm_atomic_get_new_plane_state(old_state, primary);
-   struct drm_framebuffer *fb = new_primary_state->fb;
 
intel_fbc_post_update(crtc);
 
@@ -5170,15 +5169,11 @@ static void intel_post_plane_update(struct 
intel_crtc_state *old_crtc_state)
(needs_modeset(_config->base) ||
 !old_primary_state->visible))
intel_post_enable_primary(>base, pipe_config);
-
-   /* Display WA 827 */
-   if ((INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv)) ||
-   IS_CANNONLAKE(dev_priv)) {
-   if (fb && fb->format->format == DRM_FORMAT_NV12)
-   skl_wa_clkgate(dev_priv, crtc->pipe, false);
-   }
-
}
+
+   /* Display WA 827 */
+   if (old_crtc_state->nv12_wa && !pipe_config->nv12_wa)
+   skl_wa_clkgate(dev_priv, crtc->pipe, false);
 }
 
 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
@@ -5202,14 +5197,6 @@ static void intel_pre_plane_update(struct 
intel_crtc_state *old_crtc_state,
struct intel_plane_state *new_primary_state =
intel_atomic_get_new_plane_state(old_intel_state,
 
to_intel_plane(primary));
-   struct drm_framebuffer *fb = new_primary_state->base.fb;
-
-   /* Display WA 827 */
-   if ((INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv)) ||
-   IS_CANNONLAKE(dev_priv)) {
-   if (fb && fb->format->format == DRM_FORMAT_NV12)
-   skl_wa_clkgate(dev_priv, crtc->pipe, true);
-   }
 
intel_fbc_pre_update(crtc, pipe_config, new_primary_state);
/*
@@ -5221,6 +5208,10 @@ static void intel_pre_plane_update(struct 
intel_crtc_state *old_crtc_state,
intel_set_cpu_fifo_underrun_reporting(dev_priv, 
crtc->pipe, false);
}
 
+   /* Display WA 827 */
+   if (!old_crtc_state->nv12_wa && pipe_config->nv12_wa)
+   skl_wa_clkgate(dev_priv, crtc->pipe, true);
+
/*
 * Vblank time updates from the shadow to live plane control register
 * are blocked if the memory self-refresh mode is active at that
@@ -10485,6 +10476,21 @@ static int intel_crtc_atomic_check(struct drm_crtc 
*crtc,
return ret;
}
 
+   pipe_config->nv12_wa = false;
+
+   /* Apply display WA 827 if required. */
+   if (crtc_state->active &&
+   ((INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv)) ||
+IS_CANNONLAKE(dev_priv))) {
+   struct drm_plane *plane;
+   const struct drm_plane_state *plane_state;
+
+   drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, 
crtc_state)
+   if (plane_state->fb &&
+   plane_state->fb->format->format == DRM_FORMAT_NV12)
+   pipe_config->nv12_wa = true;
+   }
+
if (crtc_state->color_mgmt_changed) {
ret = intel_color_check(crtc, crtc_state);
if (ret)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 9969309132d0..9c2b7f78d5dd 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -723,6 +723,7 @@ struct intel_crtc_state {
bool update_wm_pre, update_wm_post; /* watermarks are updated */
bool fb_changed; /* fb on any of the planes is changed */
bool fifo_changed; /* FIFO split is changed */
+   bool nv12_wa; /* Whether display WA 827 needs to be enabled. */
 
/* Pipe source size (ie. panel fitter input size)
 * All planes will be positioned inside this space,
-- 
2.16.3

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[Intel-gfx] [PATCH 1/4] drm/i915: Change use get_new_plane_state instead of existing plane state

[Maarten Lankhorst]

The get_existing macros are deprecated and should be replaced by
get_old/new_state for clarity.

Signed-off-by: Maarten Lankhorst 
---
 drivers/gpu/drm/i915/intel_atomic.c |  5 +++--
 drivers/gpu/drm/i915/intel_drv.h| 11 ---
 drivers/gpu/drm/i915/intel_pm.c |  2 +-
 3 files changed, 4 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_atomic.c 
b/drivers/gpu/drm/i915/intel_atomic.c
index bb8c1687823e..40285d1b91b7 100644
--- a/drivers/gpu/drm/i915/intel_atomic.c
+++ b/drivers/gpu/drm/i915/intel_atomic.c
@@ -227,6 +227,7 @@ int intel_atomic_setup_scalers(struct drm_i915_private 
*dev_priv,
struct intel_crtc_scaler_state *scaler_state =
_state->scaler_state;
struct drm_atomic_state *drm_state = crtc_state->base.state;
+   struct intel_atomic_state *intel_state = 
to_intel_atomic_state(drm_state);
int num_scalers_need;
int i, j;
 
@@ -304,8 +305,8 @@ int intel_atomic_setup_scalers(struct drm_i915_private 
*dev_priv,
continue;
}
 
-   plane_state = 
intel_atomic_get_existing_plane_state(drm_state,
-   
intel_plane);
+   plane_state = 
intel_atomic_get_new_plane_state(intel_state,
+  
intel_plane);
scaler_id = _state->scaler_id;
}
 
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index b2e0fa04ef5b..e545aa673bd9 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -2109,17 +2109,6 @@ intel_atomic_get_existing_crtc_state(struct 
drm_atomic_state *state,
return NULL;
 }
 
-static inline struct intel_plane_state *
-intel_atomic_get_existing_plane_state(struct drm_atomic_state *state,
- struct intel_plane *plane)
-{
-   struct drm_plane_state *plane_state;
-
-   plane_state = drm_atomic_get_existing_plane_state(state, >base);
-
-   return to_intel_plane_state(plane_state);
-}
-
 int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
   struct intel_crtc *intel_crtc,
   struct intel_crtc_state *crtc_state);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 007a12ebe725..fb24b44ec37f 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5037,7 +5037,7 @@ skl_ddb_add_affected_planes(struct intel_crtc_state 
*cstate)
struct drm_plane *plane;
enum pipe pipe = intel_crtc->pipe;
 
-   WARN_ON(!drm_atomic_get_existing_crtc_state(state, crtc));
+   WARN_ON(!drm_atomic_get_new_crtc_state(state, crtc));
 
drm_for_each_plane_mask(plane, dev, cstate->base.plane_mask) {
enum plane_id plane_id = to_intel_plane(plane)->id;
-- 
2.16.3

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[Intel-gfx] [PATCH 3/4] drm/i915: Remove last references to drm_atomic_get_existing* macros

[Maarten Lankhorst]

All the references to get_existing_state can be converted to
get_new_state or get_old_state, which means that i915 is now
get_existing_state free.

Signed-off-by: Maarten Lankhorst 
---
 drivers/gpu/drm/i915/intel_display.c | 51 
 1 file changed, 23 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index d42b635c6807..487a6e235222 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5148,8 +5148,8 @@ static void intel_post_plane_update(struct 
intel_crtc_state *old_crtc_state)

intel_atomic_get_new_crtc_state(to_intel_atomic_state(old_state),
crtc);
struct drm_plane *primary = crtc->base.primary;
-   struct drm_plane_state *old_pri_state =
-   drm_atomic_get_existing_plane_state(old_state, primary);
+   struct drm_plane_state *old_primary_state =
+   drm_atomic_get_old_plane_state(old_state, primary);
 
intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
 
@@ -5159,19 +5159,16 @@ static void intel_post_plane_update(struct 
intel_crtc_state *old_crtc_state)
if (hsw_post_update_enable_ips(old_crtc_state, pipe_config))
hsw_enable_ips(pipe_config);
 
-   if (old_pri_state) {
-   struct intel_plane_state *primary_state =
-   
intel_atomic_get_new_plane_state(to_intel_atomic_state(old_state),
-
to_intel_plane(primary));
-   struct intel_plane_state *old_primary_state =
-   to_intel_plane_state(old_pri_state);
-   struct drm_framebuffer *fb = primary_state->base.fb;
+   if (old_primary_state) {
+   struct drm_plane_state *new_primary_state =
+   drm_atomic_get_new_plane_state(old_state, primary);
+   struct drm_framebuffer *fb = new_primary_state->fb;
 
intel_fbc_post_update(crtc);
 
-   if (primary_state->base.visible &&
+   if (new_primary_state->visible &&
(needs_modeset(_config->base) ||
-!old_primary_state->base.visible))
+!old_primary_state->visible))
intel_post_enable_primary(>base, pipe_config);
 
/* Display WA 827 */
@@ -5192,8 +5189,8 @@ static void intel_pre_plane_update(struct 
intel_crtc_state *old_crtc_state,
struct drm_i915_private *dev_priv = to_i915(dev);
struct drm_atomic_state *old_state = old_crtc_state->base.state;
struct drm_plane *primary = crtc->base.primary;
-   struct drm_plane_state *old_pri_state =
-   drm_atomic_get_existing_plane_state(old_state, primary);
+   struct drm_plane_state *old_primary_state =
+   drm_atomic_get_old_plane_state(old_state, primary);
bool modeset = needs_modeset(_config->base);
struct intel_atomic_state *old_intel_state =
to_intel_atomic_state(old_state);
@@ -5201,13 +5198,11 @@ static void intel_pre_plane_update(struct 
intel_crtc_state *old_crtc_state,
if (hsw_pre_update_disable_ips(old_crtc_state, pipe_config))
hsw_disable_ips(old_crtc_state);
 
-   if (old_pri_state) {
-   struct intel_plane_state *primary_state =
+   if (old_primary_state) {
+   struct intel_plane_state *new_primary_state =
intel_atomic_get_new_plane_state(old_intel_state,
 
to_intel_plane(primary));
-   struct intel_plane_state *old_primary_state =
-   to_intel_plane_state(old_pri_state);
-   struct drm_framebuffer *fb = primary_state->base.fb;
+   struct drm_framebuffer *fb = new_primary_state->base.fb;
 
/* Display WA 827 */
if ((INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv)) ||
@@ -5216,13 +5211,13 @@ static void intel_pre_plane_update(struct 
intel_crtc_state *old_crtc_state,
skl_wa_clkgate(dev_priv, crtc->pipe, true);
}
 
-   intel_fbc_pre_update(crtc, pipe_config, primary_state);
+   intel_fbc_pre_update(crtc, pipe_config, new_primary_state);
/*
 * Gen2 reports pipe underruns whenever all planes are disabled.
 * So disable underrun reporting before all the planes get 
disabled.
 */
-   if (IS_GEN2(dev_priv) && old_primary_state->base.visible &&
-   (modeset || !primary_state->base.visible))
+   if (IS_GEN2(dev_priv) && old_primary_state->visible &&
+   (modeset || !new_primary_state->base.visible))

[Intel-gfx] [PATCH] drm/i915/guc: Check that the breadcrumb irq is enabled

[Chris Wilson]

Our execlists emulation for GuC requires use of the breadcrumb following
every request as a simulcrum for the context-switch interrupt, which we
then use to drive the submission tasklet. Therefore, when we unpark the
engine for use with the GuC, we pin the breadcrumb interrupt to keep it
enabled for the duration. This has to be remain so across all resets,
wedging and resume, so check we do have the irq enabled when we start
submitting requests to the GuC and on all submissions thereafter.

Signed-off-by: Chris Wilson 
Cc: Michal Wajdeczko 
Cc: Michał Winiarski 
---
 drivers/gpu/drm/i915/intel_guc_submission.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c 
b/drivers/gpu/drm/i915/intel_guc_submission.c
index 97121230656c..a7957b669b68 100644
--- a/drivers/gpu/drm/i915/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/intel_guc_submission.c
@@ -758,6 +758,8 @@ static void guc_submission_tasklet(unsigned long data)
struct execlist_port *port = execlists->port;
struct i915_request *rq;
 
+   GEM_BUG_ON(!READ_ONCE(engine->breadcrumbs.irq_enabled));
+
rq = port_request(port);
while (rq && i915_request_completed(rq)) {
trace_i915_request_out(rq);
-- 
2.17.0

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Re: [Intel-gfx] [PATCH v8 06/12] drm/i915: Add i915_gem_fini_hw to i915_reset

[Chris Wilson]

Quoting Michal Wajdeczko (2018-04-09 13:23:26)
> By calling in i915_reset only i915_gem_init_hw without previous
> i915_gem_fini_hw we introduced asymmetry. Let's fix that.
> 
> Signed-off-by: Michal Wajdeczko 
> Cc: Sagar Arun Kamble 
> Cc: Chris Wilson 
Reviewed-by: Chris Wilson 

> ---
>  drivers/gpu/drm/i915/i915_drv.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 854b26c..a0a5af0 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -1902,6 +1902,8 @@ void i915_reset(struct drm_i915_private *i915,
> goto error;
> }
>  
> +   i915_gem_fini_hw(i915);
> +
> for (i = 0; i < 3; i++) {
> ret = intel_gpu_reset(i915, ALL_ENGINES);
> if (ret == 0)

I still have a feeling that i915_gem_reset() will cause trouble. Hmm,
the wedged -> recovery path should be triggering the submission from
inside i915_gem_reset. So it should be exploding already...

I think where we use GEM_BUG_ON(!gt.awake) in execlists, we want a
GEM_BUG_ON(!irq_pinned) in guc_submission_tasklet().
-Chris
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[Intel-gfx] [PATCH] drm/i915/gen9_lp: Increase DDI PHY0 power well enabling timeout

[Imre Deak]

On GLK sporadic timeouts occur during PHY0 enabling. Based on logs it looks
like they happen sometime after a system suspend/resume cycle, with the
same power well enabling succeeding both before and after the failed
one and no other problems observed. The current timeout in the code is
not actually specified by BSpec, so let's try to increase that until a
BSpec update.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105771
Signed-off-by: Imre Deak 
---
 drivers/gpu/drm/i915/intel_dpio_phy.c | 11 ++-
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c 
b/drivers/gpu/drm/i915/intel_dpio_phy.c
index c8e9e44e5981..00b3ab656b06 100644
--- a/drivers/gpu/drm/i915/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
@@ -380,13 +380,14 @@ static void _bxt_ddi_phy_init(struct drm_i915_private 
*dev_priv,
 * all 1s.  Eventually they become accessible as they power up, then
 * the reserved bit will give the default 0.  Poll on the reserved bit
 * becoming 0 to find when the PHY is accessible.
-* HW team confirmed that the time to reach phypowergood status is
-* anywhere between 50 us and 100us.
+* The flag should get set in 100us according to the HW team, but
+* use 1ms due to occasional timeouts observed with that.
 */
-   if (wait_for_us(((I915_READ(BXT_PORT_CL1CM_DW0(phy)) &
-   (PHY_RESERVED | PHY_POWER_GOOD)) == PHY_POWER_GOOD), 100)) {
+   if (intel_wait_for_register_fw(dev_priv, BXT_PORT_CL1CM_DW0(phy),
+  PHY_RESERVED | PHY_POWER_GOOD,
+  PHY_POWER_GOOD,
+  1))
DRM_ERROR("timeout during PHY%d power on\n", phy);
-   }
 
/* Program PLL Rcomp code offset */
val = I915_READ(BXT_PORT_CL1CM_DW9(phy));
-- 
2.13.2

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Re: [Intel-gfx] [igt-dev] [PATCH i-g-t v6] intel-gpu-top: Rewrite the tool to be safe to use

[Tvrtko Ursulin]

[Adding some people to Cc for more ack/nack type feedback.]

Executive question is ack or nack on replacing intel_gpu_top with a new 
implementation which uses only perf PMU for counter gathering.


A short history on how this came to be:

There was a recent external patch contribution from Rinat Ibragimov to 
support more platforms from the existing intel_gpu_top. But as the tool 
is not safe to use Chris Wilson suggested to maybe just replace it.


As it happens I had a good start to do this quickly and cheaply, in the 
form of one prototype I did recently, which only needed ripping some 
bits out, and polishing the rest.


Eero and Rinat kindly did a lot of platform coverage testing and the 
rewrite seems ready for next steps.


I need to stress that as the commit notes, the new tool has a slightly 
different scope as that it doesn't expose GPU functional level data, but 
only overall stats like power, frequencies, RC6, interrupts, IMC memory 
bandwidth and per command streamer busyness, mi_semaphore and mi_event 
waits. My thinking was that for more functional level profiling gpu-top 
(OA) should be used.


Also the "run a command" and CSV output features are not not supported 
since both can be done directly via perf stat.


Regards,

Tvrtko

On 04/04/2018 16:26, Tvrtko Ursulin wrote:

From: Tvrtko Ursulin 

intel-gpu-top is a dangerous tool which can hang machines due unsafe mmio
register access. This patch rewrites it to use only PMU.

Only overall command streamer busyness and GPU global data such as power
and frequencies are included in this new version.

For access to more GPU functional unit level data, an OA metric based tool
like gpu-top should be used instead.

v2:
  * Sort engines by class and instance.
  * Do not wait for one sampling period to display something on screen.
  * Move code out of the asserts. (Rinat Ibragimov)
  * Continuously adapt to terminal size. (Rinat Ibragimov)

v3:
  * Change layout and precision of some field. (Chris Wilson)
  Eero Tamminen:
  * Use more user friendly engine names.
  * Don't error out if a counter is missing.
  * Add IMC read/write bandwidth.
  * Report minimum required kernel version.

v4:
  * Really support 4.16 by skipping of missing engines.
  * Simpler and less hacky float printing.
  * Preserve copyright header. (Antonio Argenziano)
  * Simplify engines_ptr macro. (Rinat Ibragimov)

v5:
  * Get RAPL unit from sysfs.
  * Consolidate sysfs paths with a macro.
  * Tidy error handling by carrying over and reporting errno.
  * Check against console height on all prints.
  * More readable minimum kernel version message. (Eero Tamminen)
  * Column banner for per engine stats. (Eero Tamminen)

v6:
  * Man page update. (Eero Tamminen)

Signed-off-by: Tvrtko Ursulin 
Cc: Chris Wilson 
Cc: Lionel Landwerlin 
Cc: Petri Latvala 
Cc: Eero Tamminen 
Cc: Rinat Ibragimov 
Reviewed-by: Lionel Landwerlin  # v1
Reviewed-by: Chris Wilson  # v0.5
---
  lib/igt_perf.c|6 +
  lib/igt_perf.h|1 +
  man/intel_gpu_top.rst |   41 +-
  tools/Makefile.am |2 +
  tools/intel_gpu_top.c | 1250 +++--
  tools/meson.build |6 +-
  6 files changed, 719 insertions(+), 587 deletions(-)

diff --git a/lib/igt_perf.c b/lib/igt_perf.c
index 99d82ea51c9b..e3dec2cc29c7 100644
--- a/lib/igt_perf.c
+++ b/lib/igt_perf.c
@@ -69,3 +69,9 @@ int igt_perf_open(uint64_t type, uint64_t config)
return _perf_open(type, config, -1,
  PERF_FORMAT_TOTAL_TIME_ENABLED);
  }
+
+int igt_perf_open_group(uint64_t type, uint64_t config, int group)
+{
+   return _perf_open(type, config, group,
+ PERF_FORMAT_TOTAL_TIME_ENABLED | PERF_FORMAT_GROUP);
+}
diff --git a/lib/igt_perf.h b/lib/igt_perf.h
index 614ea5d23fa6..e00718f4769a 100644
--- a/lib/igt_perf.h
+++ b/lib/igt_perf.h
@@ -55,5 +55,6 @@ uint64_t i915_type_id(void);
  int perf_i915_open(uint64_t config);
  int perf_i915_open_group(uint64_t config, int group);
  int igt_perf_open(uint64_t type, uint64_t config);
+int igt_perf_open_group(uint64_t type, uint64_t config, int group);
  
  #endif /* I915_PERF_H */

diff --git a/man/intel_gpu_top.rst b/man/intel_gpu_top.rst
index a5f7175bb1a0..19c712307d28 100644
--- a/man/intel_gpu_top.rst
+++ b/man/intel_gpu_top.rst
@@ -7,9 +7,9 @@ Display a top-like summary of Intel GPU usage
  -
  .. include:: defs.rst
  :Author: IGT Developers 
-:Date: 2016-03-01
+:Date: 2018-04-04
  :Version: |PACKAGE_STRING|
-:Copyright: 2009,2011,2012,2016 Intel Corporation
+:Copyright: 2009,2011,2012,2016,2018 Intel Corporation
  :Manual section: |MANUAL_SECTION|
  :Manual group: 

[Intel-gfx] [PATCH v8 05/12] drm/i915: Add i915_gem_fini_hw to i915_gem_suspend

[Michal Wajdeczko]

By calling i915_gem_init_hw in i915_gem_resume and not calling
i915_gem_fini_hw in i915_gem_suspend we introduced asymmetry
in init_hw/fini_hw calls. Let's fix that.

Signed-off-by: Michal Wajdeczko 
Cc: Sagar Arun Kamble 
Cc: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_gem.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 6f71099..ceec5a0 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -5061,6 +5061,7 @@ int i915_gem_suspend(struct drm_i915_private *dev_priv)
 * machines is a good idea, we don't - just in case it leaves the
 * machine in an unusable condition.
 */
+   i915_gem_fini_hw(dev_priv);
intel_uc_sanitize(dev_priv);
i915_gem_sanitize(dev_priv);
 
-- 
1.9.1

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[Intel-gfx] [PATCH v8 11/12] drm/i915/uc: Trivial s/dev_priv/i915 in intel_uc.c

[Michal Wajdeczko]

Some functions already use i915 name instead of dev_priv.
Let's rename this param in all remaining functions, except
those that still use legacy macros.

v2: don't forget about function descriptions (Sagar)
v3: rebased

Signed-off-by: Michal Wajdeczko 
Reviewed-by: Sagar Arun Kamble 
---
 drivers/gpu/drm/i915/intel_uc.c | 133 
 1 file changed, 66 insertions(+), 67 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index ed39273..ccf75aa 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -50,10 +50,10 @@ static int __intel_uc_reset_hw(struct drm_i915_private 
*dev_priv)
return ret;
 }
 
-static int __get_platform_enable_guc(struct drm_i915_private *dev_priv)
+static int __get_platform_enable_guc(struct drm_i915_private *i915)
 {
-   struct intel_uc_fw *guc_fw = _priv->guc.fw;
-   struct intel_uc_fw *huc_fw = _priv->huc.fw;
+   struct intel_uc_fw *guc_fw = >guc.fw;
+   struct intel_uc_fw *huc_fw = >huc.fw;
int enable_guc = 0;
 
/* Default is to enable GuC/HuC if we know their firmwares */
@@ -67,11 +67,11 @@ static int __get_platform_enable_guc(struct 
drm_i915_private *dev_priv)
return enable_guc;
 }
 
-static int __get_default_guc_log_level(struct drm_i915_private *dev_priv)
+static int __get_default_guc_log_level(struct drm_i915_private *i915)
 {
int guc_log_level;
 
-   if (!HAS_GUC(dev_priv) || !intel_uc_is_using_guc())
+   if (!HAS_GUC(i915) || !intel_uc_is_using_guc())
guc_log_level = GUC_LOG_LEVEL_DISABLED;
else if (IS_ENABLED(CONFIG_DRM_I915_DEBUG) ||
 IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
@@ -86,7 +86,7 @@ static int __get_default_guc_log_level(struct 
drm_i915_private *dev_priv)
 
 /**
  * sanitize_options_early - sanitize uC related modparam options
- * @dev_priv: device private
+ * @i915: device private
  *
  * In case of "enable_guc" option this function will attempt to modify
  * it only if it was initially set to "auto(-1)". Default value for this
@@ -101,14 +101,14 @@ static int __get_default_guc_log_level(struct 
drm_i915_private *dev_priv)
  * unless GuC is enabled on given platform and the driver is compiled with
  * debug config when this modparam will default to "enable(1..4)".
  */
-static void sanitize_options_early(struct drm_i915_private *dev_priv)
+static void sanitize_options_early(struct drm_i915_private *i915)
 {
-   struct intel_uc_fw *guc_fw = _priv->guc.fw;
-   struct intel_uc_fw *huc_fw = _priv->huc.fw;
+   struct intel_uc_fw *guc_fw = >guc.fw;
+   struct intel_uc_fw *huc_fw = >huc.fw;
 
/* A negative value means "use platform default" */
if (i915_modparams.enable_guc < 0)
-   i915_modparams.enable_guc = __get_platform_enable_guc(dev_priv);
+   i915_modparams.enable_guc = __get_platform_enable_guc(i915);
 
DRM_DEBUG_DRIVER("enable_guc=%d (submission:%s huc:%s)\n",
 i915_modparams.enable_guc,
@@ -119,28 +119,28 @@ static void sanitize_options_early(struct 
drm_i915_private *dev_priv)
if (intel_uc_is_using_guc() && !intel_uc_fw_is_selected(guc_fw)) {
DRM_WARN("Incompatible option detected: %s=%d, %s!\n",
 "enable_guc", i915_modparams.enable_guc,
-!HAS_GUC(dev_priv) ? "no GuC hardware" :
- "no GuC firmware");
+!HAS_GUC(i915) ? "no GuC hardware" :
+ "no GuC firmware");
}
 
/* Verify HuC firmware availability */
if (intel_uc_is_using_huc() && !intel_uc_fw_is_selected(huc_fw)) {
DRM_WARN("Incompatible option detected: %s=%d, %s!\n",
 "enable_guc", i915_modparams.enable_guc,
-!HAS_HUC(dev_priv) ? "no HuC hardware" :
- "no HuC firmware");
+!HAS_HUC(i915) ? "no HuC hardware" :
+ "no HuC firmware");
}
 
/* A negative value means "use platform/config default" */
if (i915_modparams.guc_log_level < 0)
i915_modparams.guc_log_level =
-   __get_default_guc_log_level(dev_priv);
+   __get_default_guc_log_level(i915);
 
if (i915_modparams.guc_log_level > 0 && !intel_uc_is_using_guc()) {
DRM_WARN("Incompatible option detected: %s=%d, %s!\n",
 "guc_log_level", i915_modparams.guc_log_level,
-!HAS_GUC(dev_priv) ? "no GuC hardware" :
- "GuC not enabled");
+!HAS_GUC(i915) ? "no GuC hardware" :
+ "GuC not enabled");
   

[Intel-gfx] [PATCH v8 12/12] HAX: Enable GuC for CI

[Michal Wajdeczko]

Signed-off-by: Michal Wajdeczko 
---
 drivers/gpu/drm/i915/i915_params.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_params.h 
b/drivers/gpu/drm/i915/i915_params.h
index c963603..53037b5 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -47,7 +47,7 @@
param(int, disable_power_well, -1) \
param(int, enable_ips, 1) \
param(int, invert_brightness, 0) \
-   param(int, enable_guc, 0) \
+   param(int, enable_guc, -1) \
param(int, guc_log_level, -1) \
param(char *, guc_firmware_path, NULL) \
param(char *, huc_firmware_path, NULL) \
-- 
1.9.1

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[Intel-gfx] [PATCH v8 10/12] drm/i915/uc: Use helper functions to detect fw load status

[Michal Wajdeczko]

We don't have to check load status values.

Signed-off-by: Michal Wajdeczko 
Cc: Sagar Arun Kamble 
Cc: Chris Wilson 
Reviewed-by: Sagar Arun Kamble 
---
 drivers/gpu/drm/i915/intel_huc.c | 2 +-
 drivers/gpu/drm/i915/intel_uc.c  | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_huc.c b/drivers/gpu/drm/i915/intel_huc.c
index 2912852..975ae61 100644
--- a/drivers/gpu/drm/i915/intel_huc.c
+++ b/drivers/gpu/drm/i915/intel_huc.c
@@ -51,7 +51,7 @@ int intel_huc_auth(struct intel_huc *huc)
u32 status;
int ret;
 
-   if (huc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
+   if (!intel_uc_fw_is_loaded(>fw))
return -ENOEXEC;
 
vma = i915_gem_object_ggtt_pin(huc->fw.obj, NULL, 0, 0,
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 7862731..ed39273 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -459,7 +459,7 @@ int intel_uc_suspend(struct drm_i915_private *i915)
if (!USES_GUC(i915))
return 0;
 
-   if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
+   if (!intel_guc_is_loaded(guc))
return 0;
 
err = intel_guc_suspend(guc);
@@ -481,7 +481,7 @@ int intel_uc_resume(struct drm_i915_private *i915)
if (!USES_GUC(i915))
return 0;
 
-   if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
+   if (!intel_guc_is_loaded(guc))
return 0;
 
gen9_enable_guc_interrupts(i915);
-- 
1.9.1

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[Intel-gfx] [PATCH v8 06/12] drm/i915: Add i915_gem_fini_hw to i915_reset

[Michal Wajdeczko]

By calling in i915_reset only i915_gem_init_hw without previous
i915_gem_fini_hw we introduced asymmetry. Let's fix that.

Signed-off-by: Michal Wajdeczko 
Cc: Sagar Arun Kamble 
Cc: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_drv.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 854b26c..a0a5af0 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1902,6 +1902,8 @@ void i915_reset(struct drm_i915_private *i915,
goto error;
}
 
+   i915_gem_fini_hw(i915);
+
for (i = 0; i < 3; i++) {
ret = intel_gpu_reset(i915, ALL_ENGINES);
if (ret == 0)
-- 
1.9.1

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[Intel-gfx] [PATCH v8 07/12] drm/i915/guc: Restore symmetric doorbell cleanup

[Michal Wajdeczko]

In commit 9192d4fb811e ("drm/i915/guc: Extract doorbell creation
from client allocation") we introduced asymmetry in doorbell cleanup
to avoid warnings due to failed communication with already reset GuC.
As we improved our reset/unload paths, we can restore symmetry in
doorbell cleanup, as GuC should be still active by now.

Suggested-by: Sagar Arun Kamble 
Signed-off-by: Michal Wajdeczko 
Cc: Sagar Arun Kamble 
Cc: Michal Winiarski 
Cc: Chris Wilson 
Reviewed-by: Sagar Arun Kamble 
---
 drivers/gpu/drm/i915/intel_guc_submission.c | 15 +++
 1 file changed, 3 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c 
b/drivers/gpu/drm/i915/intel_guc_submission.c
index 9712123..3b6d7f5 100644
--- a/drivers/gpu/drm/i915/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/intel_guc_submission.c
@@ -848,18 +848,9 @@ static int guc_clients_doorbell_init(struct intel_guc *guc)
 
 static void guc_clients_doorbell_fini(struct intel_guc *guc)
 {
-   /*
-* By the time we're here, GuC has already been reset.
-* Instead of trying (in vain) to communicate with it, let's just
-* cleanup the doorbell HW and our internal state.
-*/
-   if (guc->preempt_client) {
-   __destroy_doorbell(guc->preempt_client);
-   __update_doorbell_desc(guc->preempt_client,
-  GUC_DOORBELL_INVALID);
-   }
-   __destroy_doorbell(guc->execbuf_client);
-   __update_doorbell_desc(guc->execbuf_client, GUC_DOORBELL_INVALID);
+   if (guc->preempt_client)
+   destroy_doorbell(guc->preempt_client);
+   destroy_doorbell(guc->execbuf_client);
 }
 
 /**
-- 
1.9.1

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[Intel-gfx] [PATCH v8 08/12] drm/i915/uc: Fully sanitize uC within intel_uc_fini_hw

[Michal Wajdeczko]

As we always call intel_uc_sanitize after every call to
intel_uc_fini_hw we may drop redundant call and sanitize
uC from the fini_hw function.

Signed-off-by: Michal Wajdeczko 
Cc: Sagar Arun Kamble 
Cc: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_gem.c | 2 --
 drivers/gpu/drm/i915/intel_uc.c | 9 +++--
 drivers/gpu/drm/i915/intel_uc.h | 1 -
 3 files changed, 3 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index ceec5a0..decda1a 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3077,7 +3077,6 @@ int i915_gem_reset_prepare(struct drm_i915_private 
*dev_priv)
}
 
i915_gem_revoke_fences(dev_priv);
-   intel_uc_sanitize(dev_priv);
 
return err;
 }
@@ -5062,7 +5061,6 @@ int i915_gem_suspend(struct drm_i915_private *dev_priv)
 * machine in an unusable condition.
 */
i915_gem_fini_hw(dev_priv);
-   intel_uc_sanitize(dev_priv);
i915_gem_sanitize(dev_priv);
 
intel_runtime_pm_put(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 1cffaf7..0439966 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -322,18 +322,13 @@ void intel_uc_fini(struct drm_i915_private *dev_priv)
intel_guc_fini(guc);
 }
 
-void intel_uc_sanitize(struct drm_i915_private *i915)
+static void __uc_sanitize(struct drm_i915_private *i915)
 {
struct intel_guc *guc = >guc;
struct intel_huc *huc = >huc;
 
-   if (!USES_GUC(i915))
-   return;
-
GEM_BUG_ON(!HAS_GUC(i915));
 
-   guc_disable_communication(guc);
-
intel_huc_sanitize(huc);
intel_guc_sanitize(guc);
 
@@ -445,6 +440,8 @@ void intel_uc_fini_hw(struct drm_i915_private *dev_priv)
intel_guc_submission_disable(guc);
 
guc_disable_communication(guc);
+
+   __uc_sanitize(dev_priv);
 }
 
 int intel_uc_suspend(struct drm_i915_private *i915)
diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
index 25d73ad..64aaf93 100644
--- a/drivers/gpu/drm/i915/intel_uc.h
+++ b/drivers/gpu/drm/i915/intel_uc.h
@@ -33,7 +33,6 @@
 void intel_uc_init_mmio(struct drm_i915_private *dev_priv);
 int intel_uc_init_misc(struct drm_i915_private *dev_priv);
 void intel_uc_fini_misc(struct drm_i915_private *dev_priv);
-void intel_uc_sanitize(struct drm_i915_private *dev_priv);
 int intel_uc_init_hw(struct drm_i915_private *dev_priv);
 void intel_uc_fini_hw(struct drm_i915_private *dev_priv);
 int intel_uc_init(struct drm_i915_private *dev_priv);
-- 
1.9.1

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[Intel-gfx] [PATCH v8 03/12] drm/i915: Move i915_gem_fini to i915_gem.c

[Michal Wajdeczko]

We should keep i915_gem_init/fini functions together for easier
tracking of their symmetry.

Signed-off-by: Michal Wajdeczko 
Cc: Sagar Arun Kamble 
Cc: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_drv.c | 20 
 drivers/gpu/drm/i915/i915_drv.h |  1 +
 drivers/gpu/drm/i915/i915_gem.c | 20 
 3 files changed, 21 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index f770be1..854b26c 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -625,26 +625,6 @@ static bool i915_switcheroo_can_switch(struct pci_dev 
*pdev)
.can_switch = i915_switcheroo_can_switch,
 };
 
-static void i915_gem_fini(struct drm_i915_private *dev_priv)
-{
-   /* Flush any outstanding unpin_work. */
-   i915_gem_drain_workqueue(dev_priv);
-
-   mutex_lock(_priv->drm.struct_mutex);
-   intel_uc_fini_hw(dev_priv);
-   intel_uc_fini(dev_priv);
-   i915_gem_cleanup_engines(dev_priv);
-   i915_gem_contexts_fini(dev_priv);
-   mutex_unlock(_priv->drm.struct_mutex);
-
-   intel_uc_fini_misc(dev_priv);
-   i915_gem_cleanup_userptr(dev_priv);
-
-   i915_gem_drain_freed_objects(dev_priv);
-
-   WARN_ON(!list_empty(_priv->contexts.list));
-}
-
 static int i915_load_modeset_init(struct drm_device *dev)
 {
struct drm_i915_private *dev_priv = to_i915(dev);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 9bca104..f8bc276 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3143,6 +3143,7 @@ void i915_gem_reset_engine(struct intel_engine_cs *engine,
 int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
 int __must_check i915_gem_init_hw(struct drm_i915_private *dev_priv);
 void i915_gem_init_swizzling(struct drm_i915_private *dev_priv);
+void i915_gem_fini(struct drm_i915_private *dev_priv);
 void i915_gem_cleanup_engines(struct drm_i915_private *dev_priv);
 int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
   unsigned int flags);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 26294e8..fb99485 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -5520,6 +5520,26 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
return ret;
 }
 
+void i915_gem_fini(struct drm_i915_private *dev_priv)
+{
+   /* Flush any outstanding unpin_work. */
+   i915_gem_drain_workqueue(dev_priv);
+
+   mutex_lock(_priv->drm.struct_mutex);
+   intel_uc_fini_hw(dev_priv);
+   intel_uc_fini(dev_priv);
+   i915_gem_cleanup_engines(dev_priv);
+   i915_gem_contexts_fini(dev_priv);
+   mutex_unlock(_priv->drm.struct_mutex);
+
+   intel_uc_fini_misc(dev_priv);
+   i915_gem_cleanup_userptr(dev_priv);
+
+   i915_gem_drain_freed_objects(dev_priv);
+
+   WARN_ON(!list_empty(_priv->contexts.list));
+}
+
 void i915_gem_init_mmio(struct drm_i915_private *i915)
 {
i915_gem_sanitize(i915);
-- 
1.9.1

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[Intel-gfx] [PATCH v8 04/12] drm/i915: Introduce i915_gem_fini_hw for symmetry with i915_gem_init_hw

[Michal Wajdeczko]

We have i915_gem_init_hw function that on failure requires some
cleanup in uC and then in other places we were trying to do
such cleanup directly. Let's fix that by adding i915_gem_fini_hw
for nice symmetry with init_hw and call it on cleanup paths.

Signed-off-by: Michal Wajdeczko 
Cc: Sagar Arun Kamble 
Cc: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_drv.h |  1 +
 drivers/gpu/drm/i915/i915_gem.c | 13 +++--
 2 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f8bc276..dbd95a4 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3144,6 +3144,7 @@ void i915_gem_reset_engine(struct intel_engine_cs *engine,
 int __must_check i915_gem_init_hw(struct drm_i915_private *dev_priv);
 void i915_gem_init_swizzling(struct drm_i915_private *dev_priv);
 void i915_gem_fini(struct drm_i915_private *dev_priv);
+void i915_gem_fini_hw(struct drm_i915_private *dev_priv);
 void i915_gem_cleanup_engines(struct drm_i915_private *dev_priv);
 int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
   unsigned int flags);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index fb99485..6f71099 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -5257,6 +5257,15 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
goto out;
 }
 
+void i915_gem_fini_hw(struct drm_i915_private *dev_priv)
+{
+   intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
+
+   intel_uc_fini_hw(dev_priv);
+
+   intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+}
+
 static int __intel_engines_record_defaults(struct drm_i915_private *i915)
 {
struct i915_gem_context *ctx;
@@ -5482,7 +5491,7 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
 err_init_hw:
i915_gem_wait_for_idle(dev_priv, I915_WAIT_LOCKED);
i915_gem_contexts_lost(dev_priv);
-   intel_uc_fini_hw(dev_priv);
+   i915_gem_fini_hw(dev_priv);
 err_uc_init:
intel_uc_fini(dev_priv);
 err_pm:
@@ -5526,7 +5535,7 @@ void i915_gem_fini(struct drm_i915_private *dev_priv)
i915_gem_drain_workqueue(dev_priv);
 
mutex_lock(_priv->drm.struct_mutex);
-   intel_uc_fini_hw(dev_priv);
+   i915_gem_fini_hw(dev_priv);
intel_uc_fini(dev_priv);
i915_gem_cleanup_engines(dev_priv);
i915_gem_contexts_fini(dev_priv);
-- 
1.9.1

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[Intel-gfx] [PATCH v8 09/12] drm/i915/uc: Use correct error code for GuC initialization failure

[Michal Wajdeczko]

Since commit 6ca9a2beb54a ("drm/i915: Unwind i915_gem_init() failure")
we believed that we correctly handle all errors encountered during
GuC initialization, including special one that indicates request to
run driver with disabled GPU submission (-EIO).

Unfortunately since commit 121981fafe69 ("drm/i915/guc: Combine
enable_guc_loading|submission modparams") we stopped using that
error code to avoid unwanted fallback to execlist submission mode.

In result any GuC initialization failure was treated as non-recoverable
error leading to driver load abort, so we could not even read related
GuC error log to investigate cause of the problem.

Fix that by always returning -EIO on uC hardware related failure.

v2: don't allow -EIO from uc_init
don't call uc_fini[_misc] on -EIO
mark guc fw as failed on hw init failure
prepare uc_fini_hw to run after earlier -EIO

v3: update comments (Sagar)
use sanitize functions on failure in init_hw (Michal)
and also sanitize guc/huc fw in fini_hw (Michal)

v4: rebase
v5: rebase

Signed-off-by: Michal Wajdeczko 
Cc: Chris Wilson 
Cc: Michal Winiarski 
Cc: Daniele Ceraolo Spurio 
Cc: Sagar Arun Kamble 
Reviewed-by: Sagar Arun Kamble 
---
 drivers/gpu/drm/i915/i915_gem.c| 17 ++---
 drivers/gpu/drm/i915/intel_guc.h   |  5 +
 drivers/gpu/drm/i915/intel_uc.c| 15 +++
 drivers/gpu/drm/i915/intel_uc_fw.h |  5 +
 4 files changed, 31 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index decda1a..532246a 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -5444,8 +5444,10 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
intel_init_gt_powersave(dev_priv);
 
ret = intel_uc_init(dev_priv);
-   if (ret)
+   if (ret) {
+   GEM_BUG_ON(ret == -EIO);
goto err_pm;
+   }
 
ret = i915_gem_init_hw(dev_priv);
if (ret)
@@ -5492,7 +5494,8 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
i915_gem_contexts_lost(dev_priv);
i915_gem_fini_hw(dev_priv);
 err_uc_init:
-   intel_uc_fini(dev_priv);
+   if (ret != -EIO)
+   intel_uc_fini(dev_priv);
 err_pm:
if (ret != -EIO) {
intel_cleanup_gt_powersave(dev_priv);
@@ -5506,15 +5509,15 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
mutex_unlock(_priv->drm.struct_mutex);
 
-   intel_uc_fini_misc(dev_priv);
-
-   if (ret != -EIO)
+   if (ret != -EIO) {
+   intel_uc_fini_misc(dev_priv);
i915_gem_cleanup_userptr(dev_priv);
+   }
 
if (ret == -EIO) {
/*
-* Allow engine initialisation to fail by marking the GPU as
-* wedged. But we only want to do this where the GPU is angry,
+* Allow engines or uC initialization to fail by marking the GPU
+* as wedged. But we only want to do this when the GPU is angry,
 * for all other failure, such as an allocation failure, bail.
 */
if (!i915_terminally_wedged(_priv->gpu_error)) {
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index f1265e1..c587068 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -176,6 +176,11 @@ static inline int intel_guc_sanitize(struct intel_guc *guc)
return 0;
 }
 
+static inline bool intel_guc_is_loaded(struct intel_guc *guc)
+{
+   return intel_uc_fw_is_loaded(>fw);
+}
+
 static inline void intel_guc_enable_msg(struct intel_guc *guc, u32 mask)
 {
spin_lock_irq(>irq_lock);
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 0439966..7862731 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -332,6 +332,8 @@ static void __uc_sanitize(struct drm_i915_private *i915)
intel_huc_sanitize(huc);
intel_guc_sanitize(guc);
 
+   GEM_BUG_ON(intel_guc_is_loaded(guc));
+
__intel_uc_reset_hw(i915);
 }
 
@@ -420,11 +422,13 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv)
 * Note that there is no fallback as either user explicitly asked for
 * the GuC or driver default option was to run with the GuC enabled.
 */
-   if (GEM_WARN_ON(ret == -EIO))
-   ret = -EINVAL;
-
dev_err(dev_priv->drm.dev, "GuC initialization failed %d\n", ret);
-   return ret;
+
+   /* Sanitize GuC/HuC to avoid clean-up on wedged */
+   __uc_sanitize(dev_priv);
+
+   /* We want to disable GPU submission but keep KMS alive */
+   return -EIO;
 }
 
 void intel_uc_fini_hw(struct 

[Intel-gfx] [PATCH v8 02/12] drm/i915: Correctly handle error path in i915_gem_init_hw

[Michal Wajdeczko]

In function gem_init_hw() we are calling uc_init_hw() but in case
of error later in function, we missed to call matching uc_fini_hw()

Signed-off-by: Michal Wajdeczko 
Cc: Sagar Arun Kamble 
Cc: Chris Wilson 
Reviewed-by: Sagar Arun Kamble 
---
 drivers/gpu/drm/i915/i915_gem.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index dd3e292..26294e8 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -5246,9 +5246,15 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
 
/* Only when the HW is re-initialised, can we replay the requests */
ret = __i915_gem_restart_engines(dev_priv);
+   if (ret)
+   goto cleanup_uc;
 out:
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
return ret;
+
+cleanup_uc:
+   intel_uc_fini_hw(dev_priv);
+   goto out;
 }
 
 static int __intel_engines_record_defaults(struct drm_i915_private *i915)
-- 
1.9.1

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[Intel-gfx] [PATCH v8 01/12] drm/i915: Park before resetting the submission backend

[Michal Wajdeczko]

From: Chris Wilson 

As different backends may have different park/unpark callbacks, we
should only ever switch backends (reset_default_submission on wedge
recovery, or on enabling the guc) while parked.

v2: Remove the assert from the guc code, as we are currently trying to
modify the engine vfuncs pointer on a live system after reset (not just
wedging). We will just have to hope that the system is balanced.
v3: Rebase onto __i915_gem_park and improve grammar.

Signed-off-by: Chris Wilson 
Cc: Michal Wajdeczko 
Cc: Sagar Arun Kamble 
Cc: Tvrtko Ursulin 
Cc: Mika Kuoppala 
Reviewed-by: Sagar Arun Kamble 
Reviewed-by: Michal Wajdeczko 
---
 drivers/gpu/drm/i915/i915_gem.c| 15 ---
 drivers/gpu/drm/i915/intel_engine_cs.c |  3 +++
 2 files changed, 15 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 28ab0be..dd3e292 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -144,8 +144,6 @@ static u32 __i915_gem_park(struct drm_i915_private *i915)
if (!i915->gt.awake)
return I915_EPOCH_INVALID;
 
-   GEM_BUG_ON(i915->gt.epoch == I915_EPOCH_INVALID);
-
/*
 * Be paranoid and flush a concurrent interrupt to make sure
 * we don't reactivate any irq tasklets after parking.
@@ -173,6 +171,7 @@ static u32 __i915_gem_park(struct drm_i915_private *i915)
 
intel_runtime_pm_put(i915);
 
+   GEM_BUG_ON(i915->gt.epoch == I915_EPOCH_INVALID);
return i915->gt.epoch;
 }
 
@@ -3435,7 +3434,17 @@ bool i915_gem_unset_wedged(struct drm_i915_private *i915)
}
}
i915_retire_requests(i915);
-   GEM_BUG_ON(i915->gt.active_requests);
+
+   /*
+* Park before disengaging the old submit mechanism as different
+* backends may have different park/unpack callbacks.
+*
+* We are idle; the idle-worker will be queued, but we need to run
+* it now. As we already hold the struct mutex, we can park the GPU
+* right away, letting the lazy worker see that we are already active
+* again by the time it acquires the mutex.
+*/
+   __i915_gem_park(i915);
 
/*
 * Undo nop_submit_request. We prevent all new i915 requests from
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 12486d8..b4ea77a 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1651,6 +1651,9 @@ void intel_engines_reset_default_submission(struct 
drm_i915_private *i915)
struct intel_engine_cs *engine;
enum intel_engine_id id;
 
+   /* Must be parked first! */
+   GEM_BUG_ON(i915->gt.awake);
+
for_each_engine(engine, i915, id)
engine->set_default_submission(engine);
 }
-- 
1.9.1

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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/selftests: Extend partial vma coverage to check parallel creation

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915/selftests: Extend partial vma 
coverage to check parallel creation
URL   : https://patchwork.freedesktop.org/series/41359/
State : success

== Summary ==

Series 41359v1 series starting with [1/2] drm/i915/selftests: Extend partial 
vma coverage to check parallel creation
https://patchwork.freedesktop.org/api/1.0/series/41359/revisions/1/mbox/

 Known issues:

Test debugfs_test:
Subgroup read_all_entries:
incomplete -> PASS   (fi-snb-2520m) fdo#103713
Test gem_ctx_param:
Subgroup basic-default:
incomplete -> PASS   (fi-cnl-y3) fdo#105086
Test kms_chamelium:
Subgroup dp-edid-read:
fail   -> PASS   (fi-kbl-7500u) fdo#102505
Test kms_flip:
Subgroup basic-flip-vs-wf_vblank:
fail   -> PASS   (fi-cfl-s3) fdo#100368

fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#105086 https://bugs.freedesktop.org/show_bug.cgi?id=105086
fdo#102505 https://bugs.freedesktop.org/show_bug.cgi?id=102505
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368

fi-bdw-5557u total:285  pass:264  dwarn:0   dfail:0   fail:0   skip:21  
time:429s
fi-bdw-gvtdvmtotal:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:440s
fi-blb-e6850 total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  
time:380s
fi-bsw-n3050 total:285  pass:239  dwarn:0   dfail:0   fail:0   skip:46  
time:538s
fi-bwr-2160  total:285  pass:180  dwarn:0   dfail:0   fail:0   skip:105 
time:297s
fi-bxt-dsi   total:285  pass:255  dwarn:0   dfail:0   fail:0   skip:30  
time:515s
fi-bxt-j4205 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:514s
fi-byt-j1900 total:285  pass:250  dwarn:0   dfail:0   fail:0   skip:35  
time:519s
fi-byt-n2820 total:285  pass:246  dwarn:0   dfail:0   fail:0   skip:39  
time:506s
fi-cfl-8700k total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:411s
fi-cfl-s3total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:559s
fi-cfl-u total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:511s
fi-cnl-y3total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:583s
fi-elk-e7500 total:285  pass:226  dwarn:0   dfail:0   fail:0   skip:59  
time:431s
fi-gdg-551   total:285  pass:176  dwarn:0   dfail:0   fail:1   skip:108 
time:314s
fi-glk-1 total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:535s
fi-glk-j4005 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:486s
fi-hsw-4770  total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:404s
fi-ilk-650   total:285  pass:225  dwarn:0   dfail:0   fail:0   skip:60  
time:428s
fi-ivb-3520m total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:476s
fi-ivb-3770  total:285  pass:252  dwarn:0   dfail:0   fail:0   skip:33  
time:440s
fi-kbl-7500u total:285  pass:260  dwarn:1   dfail:0   fail:0   skip:24  
time:472s
fi-kbl-7567u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:462s
fi-kbl-r total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:511s
fi-pnv-d510  total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  
time:670s
fi-skl-6260u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:447s
fi-skl-6600u total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:533s
fi-skl-6700k2total:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:501s
fi-skl-6770hqtotal:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:502s
fi-skl-guc   total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:426s
fi-skl-gvtdvmtotal:285  pass:262  dwarn:0   dfail:0   fail:0   skip:23  
time:445s
fi-snb-2520m total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:581s
fi-snb-2600  total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:398s

1be073153147c5c39cdcbdfdeb4e2595ba595bf7 drm-tip: 2018y-04m-07d-22h-26m-31s UTC 
integration manifest
d9b8dd829776 drm/i915/selftests: Compare mappable vma against instance in 
unmappable region
6a326fc76a03 drm/i915/selftests: Extend partial vma coverage to check parallel 
creation

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8639/issues.html
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Re: [Intel-gfx] [PATCH v3] drm/i915/execlists: Log fence context & seqno throughout GEM_TRACE

[Chris Wilson]

Quoting Tvrtko Ursulin (2018-04-06 13:35:14)
> From: Tvrtko Ursulin 
> 
> Include fence context and seqno in low level tracing so it is easier to
> follow flows of individual requests when things go bad.
> 
> Also added tracing on the reset side of things.
> 
> v2:
>  Chris Wilson:
>  * Standardize global_seqno and seqno as global.
>  * Include current hws seqno in execlists_cancel_port_requests.
> 
> v3:
>  * Fix port printk format for all builds.
> 
> Signed-off-by: Tvrtko Ursulin 
> Reviewed-by: Chris Wilson  # v2

Since I didn't spot the printk kerfuffle, it's fair to assume my rb
would stand for a minor change :)

Reviewed-by: Chris Wilson 
-Chris
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Re: [Intel-gfx] [PATCH 3/7] drm/i915: Keep a count of requests submitted from userspace

[Chris Wilson]

Quoting Tvrtko Ursulin (2018-04-09 12:43:50)
> 
> On 09/04/2018 11:51, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2018-04-09 11:40:08)
> >>
> >> On 09/04/2018 11:27, Chris Wilson wrote:
> >>> Quoting Tvrtko Ursulin (2018-04-09 11:17:04)
> 
>  On 09/04/2018 10:25, Chris Wilson wrote:
> > Downside being that we either then use atomic64 throughout or we mix
> > atomic32/atomic64 knowing that we're on x86. (I feel like someone else
> > must have solved this problem in a much neater way, before they went to
> > per-cpu stats ;)
> 
>  Is the winky implying you know who and where? :) We have three potential
>  solutions now, even for if the winky is suggesting something.
> >>>
> >>> Nah, just that atomic/locked counters are so old hat. Not sure if there
> >>> remain any good examples for hotpath counters that remain applicable to
> >>> our code.
> >>
> >> Leave it as is then for now and improve if we discover it is not good
> >> enough?
> > 
> > I did have an ulterior motive in that the cmpxchg did resolve one issue
> > that irked me with the two counters being updated out of sync. Minor,
> > minor glitches :)
> > 
> > I don't have a strong preference either way. These instructions on the
> > submit are not likely to stand out, as compared to the biggest fish of
> > ksoftirqd, execlists_schedule() and execlists_dequeue().
> 
> I could move the queued decrement from submit_notify to backends, right 
> next to runnable++? Then both would be under the engine->timeline->lock 
> so any inconsistencies in readout I'd hope should be dismissable?

Fair. I have this itch to add a request->state,
switch (request->state) {
case QUEUED:
stats->queued--;
switch (now) {
case QUEUED:
BUG();
case: READY:
stats->runnable++;
case EXEC:
break;
}
break;
case ...
}
request->state = now;

Stop me. Please, stop me.
-Chris
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