Re: [Intel-gfx] linux-next: build failure after merge of the drm-intel tree

Hi Christoph, On Wed, 9 May 2018 07:08:55 +0200 Christoph Hellwig wrote: > > FYI, because the dma_configure change touch so much code and the author > wants to base more work on it it actually is in a guranteed stable > branch with just those patches: > >

Re: [Intel-gfx] linux-next: build failure after merge of the drm-intel tree

On Wed, May 09, 2018 at 03:02:55PM +1000, Stephen Rothwell wrote: > > - ret = of_dma_configure(dev, NULL); > > + ret = of_dma_configure(dev, NULL, true); > > if (ret < 0) { > > DRM_ERROR("Cannot setup DMA ops, ret %d", ret); > > return ret; > > -- > > 2.17.0 > >

Re: [Intel-gfx] linux-next: build failure after merge of the drm-intel tree

Hi all, On Tue, 8 May 2018 11:07:16 +1000 Stephen Rothwell wrote: > > After merging the drm-intel tree, today's linux-next build (x86_64 > allmodconfig) failed like this: > > drivers/gpu/drm/xen/xen_drm_front.c: In function 'xen_drv_probe': >

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/psr: Check if VBT says PSR can be enabled.

== Series Details == Series: drm/i915/psr: Check if VBT says PSR can be enabled. URL : https://patchwork.freedesktop.org/series/42909/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4160_full -> Patchwork_8954_full = == Summary - WARNING == Minor unknown changes coming

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/psr: Nuke PSR support for VLV and CHV

== Series Details == Series: drm/i915/psr: Nuke PSR support for VLV and CHV URL : https://patchwork.freedesktop.org/series/42915/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_4160 -> Patchwork_8955 = == Summary - FAILURE == Serious unknown changes coming with

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gvt: fix spelling mistake: "resseting" -> "resetting"

== Series Details == Series: drm/i915/gvt: fix spelling mistake: "resseting" -> "resetting" URL : https://patchwork.freedesktop.org/series/42903/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4160_full -> Patchwork_8953_full = == Summary - WARNING == Minor unknown

[Intel-gfx] [RFC] drm/i915/psr: Nuke PSR support for VLV and CHV

1) PSR hardware and hence the driver code deviates a lot from the DDI implementations. Retaining support for VLV and CHV is maintenance burden, we've had to refactor to keep the code clean. 2) There is no PSR capable VLV/CHV platform in CI to ensure code is correct. 3) There are likely no users

[Intel-gfx] ✓ Fi.CI.IGT: success for Workarounds for Icelake (rev3)

== Series Details == Series: Workarounds for Icelake (rev3) URL : https://patchwork.freedesktop.org/series/42055/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4160_full -> Patchwork_8952_full = == Summary - WARNING == Minor unknown changes coming with

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/selftests: Create mock_engine() under struct_mutex

== Series Details == Series: drm/i915/selftests: Create mock_engine() under struct_mutex URL : https://patchwork.freedesktop.org/series/42898/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4160_full -> Patchwork_8951_full = == Summary - WARNING == Minor unknown changes

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [CI,1/2] drm/i915/execlists: Make submission tasklet hardirq safe

== Series Details == Series: series starting with [CI,1/2] drm/i915/execlists: Make submission tasklet hardirq safe URL : https://patchwork.freedesktop.org/series/42896/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4160_full -> Patchwork_8950_full = == Summary - WARNING

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/psr: Check if VBT says PSR can be enabled.

== Series Details == Series: drm/i915/psr: Check if VBT says PSR can be enabled. URL : https://patchwork.freedesktop.org/series/42909/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4160 -> Patchwork_8954 = == Summary - SUCCESS == No regressions found. External URL:

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/psr: Check if VBT says PSR can be enabled.

== Series Details == Series: drm/i915/psr: Check if VBT says PSR can be enabled. URL : https://patchwork.freedesktop.org/series/42909/ State : warning == Summary == $ dim sparse origin/drm-tip Commit: drm/i915/psr: Check if VBT says PSR can be enabled.

[Intel-gfx] [PATCH] drm/i915/psr: Check if VBT says PSR can be enabled.

Driver features data block has a boolean flag for PSR, use this to decide whether PSR should be enabled on a platform. The module parameter can still be used to override this. Note: The feature currently remains disabled by default for all platforms irrespective of what VBT says. Cc: Rodrigo

Re: [Intel-gfx] [PATCH 5/5] drm/i915/icl/huc: Define the HuC firmware version for Icelake

On Wed, 2018-05-02 at 12:03 -0700, Oscar Mateo wrote: > This patch adds the support to load HuC on ICL. > Version 8.02.2678 > > v2 (James): Rebase > > Signed-off-by: Oscar Mateo > Cc: Tony Ye > Cc: Vinay Belgaumkar > Cc:

Re: [Intel-gfx] [PATCH 4/5] drm/i915/icl/huc: Correctly authenticate the HuC for Icelake

On Wed, 2018-05-02 at 12:03 -0700, Oscar Mateo wrote: > The register to check for correct HuC authentication by the GuC > has changed in Icelake. Look into the right register & bit. > > v2: rebased. > v3: rebased. > v4: Fix I915_PARAM_HUC_STATUS as well (Tony) > v5: Fix duplicate Cc > > BSpec:

Re: [Intel-gfx] [PATCH 3/5] drm/i915/icl/guc: Define the GuC firmware version for Icelake

On Wed, 2018-05-02 at 12:03 -0700, Oscar Mateo wrote: > A GuC firmware for Icelake is now available. Let's use it. > > v2: Split out the Cannonlake stuff in a separate patch (Michal) > > v3: Rebased > > v4: >   - Rebased >   - Split out MODULE_FIRMWARE so we don't accidentally push it >

Re: [Intel-gfx] [PATCH 1/5] drm/i915/icl/guc: Do not allow GuC submission on Icelake for now

On Wed, 2018-05-02 at 12:03 -0700, Oscar Mateo wrote: > Sanitize the enable_guc option so that we can enable HuC > authentication, > but nothing else. The firmware interface has changed quite > dramatically > in Gen11, so it will take a while before we can submit workloads to > the > GuC with

Re: [Intel-gfx] [PATCH 2/5] drm/i915/icl/guc: Pass the bare minimum GuC init parameters for Icelake

On Wed, 2018-05-02 at 12:03 -0700, Oscar Mateo wrote: > Only enough to achieve HuC authentication. No GuC submission > or any other feature for the time being. > > v2: Fix extra space > > Signed-off-by: Oscar Mateo > Cc: Joonas Lahtinen >

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gvt: fix spelling mistake: "resseting" -> "resetting"

== Series Details == Series: drm/i915/gvt: fix spelling mistake: "resseting" -> "resetting" URL : https://patchwork.freedesktop.org/series/42903/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4160 -> Patchwork_8953 = == Summary - SUCCESS == No regressions found.

[Intel-gfx] ✓ Fi.CI.BAT: success for Workarounds for Icelake (rev3)

== Series Details == Series: Workarounds for Icelake (rev3) URL : https://patchwork.freedesktop.org/series/42055/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4160 -> Patchwork_8952 = == Summary - SUCCESS == No regressions found. External URL:

Re: [Intel-gfx] [PATCH v2 1/3] drm/i915: Replace vbt edp.support with int_lvds_support

Hi Ville, Thank you for the patch! Perhaps something to improve: [auto build test WARNING on drm-intel/for-linux-next] [also build test WARNING on v4.17-rc4 next-20180508] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url: https

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Workarounds for Icelake (rev3)

== Series Details == Series: Workarounds for Icelake (rev3) URL : https://patchwork.freedesktop.org/series/42055/ State : warning == Summary == $ dim sparse origin/drm-tip Commit: drm/i915/icl: Introduce initial Icelake Workarounds -drivers/gpu/drm/i915/selftests/../i915_drv.h:3653:16:

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: per context slice/subslice powergating (rev2)

== Series Details == Series: drm/i915: per context slice/subslice powergating (rev2) URL : https://patchwork.freedesktop.org/series/42285/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_4158_full -> Patchwork_8949_full = == Summary - FAILURE == Serious unknown changes

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Workarounds for Icelake (rev3)

== Series Details == Series: Workarounds for Icelake (rev3) URL : https://patchwork.freedesktop.org/series/42055/ State : warning == Summary == $ dim checkpatch origin/drm-tip e15ebaa57f79 drm/i915/icl: Introduce initial Icelake Workarounds -:54: CHECK:MACRO_ARG_REUSE: Macro argument reuse

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftests: Create mock_engine() under struct_mutex

== Series Details == Series: drm/i915/selftests: Create mock_engine() under struct_mutex URL : https://patchwork.freedesktop.org/series/42898/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4160 -> Patchwork_8951 = == Summary - WARNING == Minor unknown changes coming

[Intel-gfx] [PATCH] drm/i915/gvt: fix spelling mistake: "resseting" -> "resetting"

From: Colin Ian King Trivial fix to spelling mistake in gvt_dbg_core debug message Signed-off-by: Colin Ian King --- drivers/gpu/drm/i915/gvt/vgpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915/execlists: Use rmb() to order CSB reads

== Series Details == Series: series starting with [1/2] drm/i915/execlists: Use rmb() to order CSB reads URL : https://patchwork.freedesktop.org/series/42884/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4158_full -> Patchwork_8948_full = == Summary - WARNING == Minor

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/2] drm/i915/execlists: Make submission tasklet hardirq safe

== Series Details == Series: series starting with [CI,1/2] drm/i915/execlists: Make submission tasklet hardirq safe URL : https://patchwork.freedesktop.org/series/42896/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4160 -> Patchwork_8950 = == Summary - WARNING ==

Re: [Intel-gfx] [PATCH v2 5/9] drm/i915/psr: Handle PSR RFB storage error

On Mon, 2018-04-30 at 23:28 +, Souza, Jose wrote: > On Thu, 2018-04-26 at 15:37 -0700, Dhinakaran Pandiyan wrote: > > > > > > > > On Wed, 2018-04-18 at 15:43 -0700, José Roberto de Souza wrote: > > > > > > Sink will interrupt source when it have any problem saving or > > > reading > > >

Re: [Intel-gfx] [PATCH v2 8/9] drm/i915/dp: Improve intel_dp_aux_is_busy()

On Wed, 2018-04-18 at 15:43 -0700, José Roberto de Souza wrote: > - Doing earlier return when not busy > - using u32 instead of uint32_t > - counting from 3 to 0 as it is is the most common in the driver Hmm. I see more instances that increment the loop variable than the opposite. > - using

Re: [Intel-gfx] [PATCH 4/5] drm/i915/icl/huc: Correctly authenticate the HuC for Icelake

On 05/04/2018 03:26 PM, John Spotswood wrote: On Wed, 2018-05-02 at 12:03 -0700, Oscar Mateo wrote: The register to check for correct HuC authentication by the GuC has changed in Icelake. Look into the right register & bit. v2: rebased. v3: rebased. v4: Fix I915_PARAM_HUC_STATUS as well

[Intel-gfx] [PATCH 14/22] drm/i915/icl: WaDisableImprovedTdlClkGating

Revert to the legacy implementation. v2: GEN7_ROW_CHICKEN2 is masked v3: - Rebased - Renamed to Wa_2006611047 - A0 and B0 only v4: - Add spaces around '<<' (and fix the surrounding code as well) - Mark the WA as pre-prod v5: Rebased on top of the WA refactoring v6: Added References

[Intel-gfx] [PATCH 07/22] drm/i915/icl: WaCL2SFHalfMaxAlloc

This workarounds an issue with insufficient storage for the CL2 and SF units. v2: Renamed to Wa_1405766107 v3: Wrapped the commit message v4: Rebased on top of the WA refactoring v5: Added References (Mika) v6: - Rebased - s/MACALLOC/MAXALLOC (Mika) - C, not lisp (Chris) References:

[Intel-gfx] [PATCH 18/22] drm/i915/icl: WaSendPushConstantsFromMMIO

Allows UMDs to set 'Disable Gather at Set Shader Common Slice'. Do Linux UMDs make use of this? This change has been security reviewed and the whitelisting approved. Virtualization of other OSes could certainly use it... v2: Rebased v3: Rebased on top of the WA refactoring v4: Rebased on top of

[Intel-gfx] [PATCH 21/22] drm/i915/icl: WaAllowUmdWriteTRTTRootTable

Required for TR-TT (Tiled Resource Translation Table) support. Do Linux UMDs make use of this? This change has been security reviewed and the whitelisting approved. Virtualization of other OSes could certainly use it. v2: For whatever reason, this ended up in KBL (??!!) v3: Rebased on top of the

[Intel-gfx] [PATCH 04/22] drm/i915/icl: WaL3BankAddressHashing

Revert to an L3 non-hash model, for performance reasons. v2: - Place the WA name above the actual change - Improve the register naming v3: - Rebased - Renamed to Wa_1604223664 v4: Rebased on top of the WA refactoring v5: - Added References (Mika) - Fixed wrong mask and value (Mika)

[Intel-gfx] [PATCH 10/22] drm/i915/icl: Wa_1406680159

Disable GWL clock gating to prevent an issue that might cause hangs. v2: Rebased on top of the WA refactoring v3: Wa_2201832410 officially merged with Wa_1406680159 v4: Added References (Mika) v5: - Rebased - C, not lisp (Chris) - Add reference where WA is better explained (Rodrigo) - Add

[Intel-gfx] [PATCH 09/22] drm/i915/icl: Wa_1405779004

Disable MSC clock gating to prevent data corruption. BSpec: 19257 v2: Rebased on top of the WA refactoring v3: Added References (Mika) v4: - Rebased - C, not lisp (Chris) - A0 only (Mika) References: HSDES#1405779004 Signed-off-by: Oscar Mateo Reviewed-by: Mika

Re: [Intel-gfx] [PATCH v2 7/9] drm/i915/dp: Move code to check if aux ch is busy to a function

On Mon, 2018-04-30 at 23:39 +, Souza, Jose wrote: > On Thu, 2018-04-26 at 15:51 -0700, Dhinakaran Pandiyan wrote: > > > > > > > > On Wed, 2018-04-18 at 15:43 -0700, José Roberto de Souza wrote: > > > > > > This reduces the spaghetti that intel_dp_aux_xfer(). > > > > > > Moved doing less

[Intel-gfx] [PATCH 02/22] drm/i915/icl: Enable Sampler DFR

Sampler Dynamic Frequency Rebalancing (DFR) aims to reduce Sampler power by dynamically changing its clock frequency in low-throughput conditions. This patches enables it by default on Gen11. v2: Wrong operation to clear the bit (Praveen) v3: Rebased on top of the WA refactoring v4: Move to

[Intel-gfx] [PATCH 08/22] drm/i915/icl: WaDisCtxReload

Revert to the legacy implementation to avoid a system hang. v2: Correct the address for GAMW_ECO_DEV_RW_IA_REG v3: Renamed to Wa_220166154 v4: Rebased on top of the WA refactoring v5: Added References (Mika) v6: - Rebased - C, not lisp (Chris) References: HSDES#220166154 Signed-off-by: Oscar

[Intel-gfx] [PATCH 16/22] drm/i915/icl: Wa_2006665173

Disable blend embellishment in RCC. Also, some other registers style fixed in passing. v2: Rebased on top of the WA refactoring v3: Added References (Mika) v4: - Fixed in B0 - Mentioned style fixes in commit message References: HSDES#2006665173 Cc: Mika Kuoppala

[Intel-gfx] [PATCH 12/22] drm/i915/icl: Wa_1406838659

Disable CGPSF unit clock gating to prevent an issue. v2: Rebased on top of the WA refactoring v3: Added References (Mika) v4: - Rebased - C, not lisp (Chris) - Remove unintentional whitespaces (Mika) - Fixed in C0 (Mika) References: HSDES#1406838659 Signed-off-by: Oscar Mateo

[Intel-gfx] [PATCH 20/22] drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken7

Required to dinamically set 'Trilinear Filter Quality Mode' Do Linux UMDs make use of this? This change has been security reviewed and the whitelisting approved. Virtualization of other OSes could certainly use it. v2: For whatever reason, this ended up in KBL (??!!) v3: Rebased on top of the WA

[Intel-gfx] [PATCH 17/22] drm/i915/icl: WaEnableFloatBlendOptimization

Enables blend optimization for floating point RTs v2: Rebased on top of the WA refactoring v3: Added References (Mika) References: HSDES#1406393558 Cc: Mika Kuoppala Signed-off-by: Oscar Mateo --- drivers/gpu/drm/i915/i915_reg.h |

[Intel-gfx] [PATCH 06/22] drm/i915/icl: WaDisableCleanEvicts

Avoids an undefined LLC behavior. BSpec: 9613 v2: Renamed to Wa_1405733216 v3: Spaces around '<<' and fix surrounding code v4: Rebased on top of the WA refactoring v5: Added References (Mika) v6: - Rebased - C, not lisp (Chris) References: HSDES#1405733216 Signed-off-by: Oscar Mateo

[Intel-gfx] [PATCH 05/22] drm/i915/icl: WaModifyGamTlbPartitioning

Adjust default GAM TLB partitioning for performance reasons. v2: Only touch the bits that we really need v3: Rebased on top of the WA refactoring v4: - Added References (Mika) - Rebased v5: - Rebased - C, not lisp (Chris) - Correct reference number (Mika) References: HSDES#220160670

[Intel-gfx] [PATCH 11/22] drm/i915/icl: Wa_1604302699

Disable I2M Write for performance reasons. v2: Rebased on top of the WA refactoring v3: Added References (Mika) v4: - Rebased - C, not lisp (Chris) - GEN7 chicken bit in the wrong side of the fence (Mika) - Use two spaces to align bit macros References: HSDES#1604302699 Signed-off-by:

[Intel-gfx] [PATCH 13/22] drm/i915/icl: WaForwardProgressSoftReset

Avoids a hang during soft reset. v2: Rebased on top of the WA refactoring v3: Added References (Mika) v4: - Rebased - C, not lisp (Chris) - Which steppings affected by this are not clear. For the moment, apply unconditionally as per the BSpec (Mika) - Add reference to another HSD

[Intel-gfx] [PATCH v3 00/22] Workarounds for Icelake

List of GT workarounds for Icelake that we have been carrying in internal. Applied lots of review comments from Mika and stamped rv-b's from him and Rodrigo. Oscar Mateo (22): drm/i915/icl: Introduce initial Icelake Workarounds drm/i915/icl: Enable Sampler DFR drm/i915/icl:

[Intel-gfx] [PATCH 22/22] drm/i915/icl: WaAllowUMDToModifySamplerMode

Required for Bindless samplers. Do Linux UMDs make use of this? This change has been security reviewed and the whitelisting approved. Virtualization of other OSes could certainly use it. v2: Rebased on top of the WA refactoring (Michel) v3: Added References (Mika) References: HSDES#1404695891

[Intel-gfx] [PATCH 15/22] drm/i915/icl: WaEnableStateCacheRedirectToCS

Redirects the state cache to the CS Command buffer section for performance reasons. v2: Rebased v3: Rebased on top of the WA refactoring v3: Added References (Mika) References: HSDES#1604325460 Cc: Mika Kuoppala Signed-off-by: Oscar Mateo

[Intel-gfx] [PATCH 19/22] drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken2

Required to dinamically set 'Small PL Lossless Fix Enable' Do Linux UMDs make use of this? This change has been security reviewed and the whitelisting approved. Virtualization of other OSes could certainly use it. v2: For whatever reason, this ended up in KBL (??!!) v3: Rebased on top of the WA

[Intel-gfx] [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds

Inherit workarounds from previous platforms that are still valid for Icelake. v2: GEN7_ROW_CHICKEN2 is masked v3: - Since it has been fixed already in upstream, removed the TODO comment about WA_SET_BIT for WaInPlaceDecompressionHang. - Squashed with this patch: drm/i915/icl: add

[Intel-gfx] [PATCH 03/22] drm/i915/icl: WaGAPZPriorityScheme

The default GAPZ arbitrer priority value at power-on has been found to be incorrect. v2: Now renamed to Wa_1405543622 v3: Rebased on top of the WA refactoring v4: Added HSDES reference number (Mika) v5: - Rebased - C, not lisp (Chris) References: HSDES#1405543622 Signed-off-by: Oscar Mateo

Re: [Intel-gfx] [PATCH] drm/i915/selftests: Create mock_engine() under struct_mutex

On 05/08/2018 02:10 PM, Chris Wilson wrote: Calling mock_engine() calls i915_timeline_init() and that requires struct_mutex to be held as it adds itself to the global list of timelines. This error was introduced by commit a89d1f921c15 ("drm/i915: Split i915_gem_timeline into individual

Re: [Intel-gfx] [PATCH v2 1/3] drm/i915: Replace vbt edp.support with int_lvds_support

Hi Ville, Thank you for the patch! Yet something to improve: [auto build test ERROR on drm-intel/for-linux-next] [also build test ERROR on v4.17-rc4 next-20180508] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url: https://github.com

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Annotate timeline lock nesting

Quoting Patchwork (2018-05-08 21:58:09) > == Series Details == > > Series: drm/i915: Annotate timeline lock nesting > URL : https://patchwork.freedesktop.org/series/42881/ > State : failure > > == Summary == > > = CI Bug Log - changes from CI_DRM_4158_full -> Patchwork_8946_full = > > ==

[Intel-gfx] [PATCH] drm/i915/selftests: Create mock_engine() under struct_mutex

Calling mock_engine() calls i915_timeline_init() and that requires struct_mutex to be held as it adds itself to the global list of timelines. This error was introduced by commit a89d1f921c15 ("drm/i915: Split i915_gem_timeline into individual timelines") but the issue was masked in CI by the

[Intel-gfx] [CI 2/2] drm/i915/guc: Make submission tasklet hardirq safe

Prepare to allow the GuC submission to be run from underneath a hardirq timer context (and not just the current softirq context) as is required for fast preemption resets and context switches. Signed-off-by: Chris Wilson Reviewed-by: Tvrtko Ursulin

[Intel-gfx] [CI 1/2] drm/i915/execlists: Make submission tasklet hardirq safe

Prepare to allow the execlists submission to be run from underneath a hardirq timer context (and not just the current softirq context) as is required for fast preemption resets and context switches. Signed-off-by: Chris Wilson Reviewed-by: Tvrtko Ursulin

Re: [Intel-gfx] [PATCH v2 3/7] drm/i915/execlists: Make submission tasklet hardirq safe

Quoting Tvrtko Ursulin (2018-05-08 18:45:44) > > On 07/05/2018 14:57, Chris Wilson wrote: > > Prepare to allow the execlists submission to be run from underneath a > > hardirq timer context (and not just the current softirq context) as is > > required for fast preemption resets and context

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Annotate timeline lock nesting

== Series Details == Series: drm/i915: Annotate timeline lock nesting URL : https://patchwork.freedesktop.org/series/42881/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_4158_full -> Patchwork_8946_full = == Summary - FAILURE == Serious unknown changes coming with

Re: [Intel-gfx] [PATCH 8/8] drm/i915: Expose RPCS (SSEU) configuration to userspace

Quoting Tvrtko Ursulin (2018-05-03 18:18:43) > > On 25/04/2018 12:45, Lionel Landwerlin wrote: > > From: Chris Wilson > > > > We want to allow userspace to reconfigure the subslice configuration for > > its own use case. To do so, we expose a context parameter to allow

Re: [Intel-gfx] [PATCH] drm/i915: Remove unused i915_flip tracepoints

Quoting Ville Syrjälä (2018-05-08 16:35:18) > On Tue, May 08, 2018 at 04:15:52PM +0100, Chris Wilson wrote: > > The i915_flip* tracepoints are no longer in use since the removal of CS > > flip in commit 8b5d27b911d7 ("drm/i915: Remove intel_flip_work > > infrastructure") > > > > References:

Re: [Intel-gfx] [PATCH] drm/i915: Annotate timeline lock nesting

Quoting Michel Thierry (2018-05-08 18:30:22) > On 05/08/2018 08:35 AM, Chris Wilson wrote: > > CI noticed > > > > <4>[ 23.430701] > > <4>[ 23.430706] WARNING: possible recursive locking detected > > <4>[ 23.430713] 4.17.0-rc4-CI-CI_DRM_4156+ #1

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Remove unused i915_flip tracepoints

== Series Details == Series: drm/i915: Remove unused i915_flip tracepoints URL : https://patchwork.freedesktop.org/series/42879/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_4158_full -> Patchwork_8945_full = == Summary - FAILURE == Serious unknown changes coming with

Re: [Intel-gfx] [PATCH] drm/i915: Annotate timeline lock nesting

Quoting Tvrtko Ursulin (2018-05-08 18:47:42) > > On 08/05/2018 16:35, Chris Wilson wrote: > > CI noticed > > > > <4>[ 23.430701] > > <4>[ 23.430706] WARNING: possible recursive locking detected > > <4>[ 23.430713] 4.17.0-rc4-CI-CI_DRM_4156+ #1

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v2,1/3] drm/i915: Replace vbt edp.support with int_lvds_support (rev3)

== Series Details == Series: series starting with [v2,1/3] drm/i915: Replace vbt edp.support with int_lvds_support (rev3) URL : https://patchwork.freedesktop.org/series/42874/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4158_full -> Patchwork_8944_full = == Summary -

Re: [Intel-gfx] [PATCH] drm/dp: add module parameter for the dpcd access max retries

On Wed, 09 May 2018, Feng Tang wrote: > >> > > > On Mon, May 07, 2018 at 11:40:45AM +0100, Chris Wilson wrote: >> >> > > > > Quoting Feng Tang (2018-05-07 11:36:09) >> >> > > > > > To fulfil the Dell 4K monitor, the dpcd max retries has been >> >> > > > > > bumped >> >> > >

Re: [Intel-gfx] [PATCH 2/2] drm/dp: Correctly mask DP_TRAINING_AUX_RD_INTERVAL values for DP 1.4

On Fri, May 04, 2018 at 03:18:00PM -0700, matthew.s.atw...@intel.com wrote: > From: Matt Atwood > > DP_TRAINING_AUX_RD_INTERVAL with DP 1.3 spec changed bit scheeme from 8 > bits to 7 in DPCD 0x000e. The 8th bit is used to identify extended > receiver capabilities.

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: per context slice/subslice powergating (rev2)

== Series Details == Series: drm/i915: per context slice/subslice powergating (rev2) URL : https://patchwork.freedesktop.org/series/42285/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4158 -> Patchwork_8949 = == Summary - SUCCESS == No regressions found. External

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/execlists: Use rmb() to order CSB reads (rev2)

== Series Details == Series: drm/i915/execlists: Use rmb() to order CSB reads (rev2) URL : https://patchwork.freedesktop.org/series/42867/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4158_full -> Patchwork_8943_full = == Summary - WARNING == Minor unknown changes

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: per context slice/subslice powergating (rev2)

== Series Details == Series: drm/i915: per context slice/subslice powergating (rev2) URL : https://patchwork.freedesktop.org/series/42285/ State : warning == Summary == $ dim sparse origin/drm-tip Commit: drm/i915: Program RPCS for Broadwell Okay! Commit: drm/i915: Record the sseu

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: per context slice/subslice powergating (rev2)

== Series Details == Series: drm/i915: per context slice/subslice powergating (rev2) URL : https://patchwork.freedesktop.org/series/42285/ State : warning == Summary == $ dim checkpatch origin/drm-tip adb11ec2e377 drm/i915: Program RPCS for Broadwell 48dc54799480 drm/i915: Record the sseu

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/execlists: Use rmb() to order CSB reads

== Series Details == Series: series starting with [1/2] drm/i915/execlists: Use rmb() to order CSB reads URL : https://patchwork.freedesktop.org/series/42884/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4158 -> Patchwork_8948 = == Summary - SUCCESS == No regressions

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/execlists: Use rmb() to order CSB reads

== Series Details == Series: series starting with [1/2] drm/i915/execlists: Use rmb() to order CSB reads URL : https://patchwork.freedesktop.org/series/42884/ State : warning == Summary == $ dim checkpatch origin/drm-tip 1bab7a77636f drm/i915/execlists: Use rmb() to order CSB reads -:32:

[Intel-gfx] ✗ Fi.CI.BAT: failure for RFT agp/intel: Hit Grantsdale with a sledgehammer

== Series Details == Series: RFT agp/intel: Hit Grantsdale with a sledgehammer URL : https://patchwork.freedesktop.org/series/42882/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_4158 -> Patchwork_8947 = == Summary - FAILURE == Serious unknown changes coming with

[Intel-gfx] [PATCH v3 4/6] drm/i915: reprogram NOA muxes on context switch when using perf

If some of the contexts submitting workloads to the GPU have been configured to shutdown slices/subslices, we might loose the NOA configurations written in the NOA muxes. We need to reprogram them when we detect a powergating configuration change. In this change i915/perf is responsible for

[Intel-gfx] [PATCH v3 1/6] drm/i915: Program RPCS for Broadwell

From: Chris Wilson Currently we only configure the power gating for Skylake and above, but the configuration should equally apply to Broadwell and Braswell. Even though, there is not as much variation as for later generations, we want to expose control over the

[Intel-gfx] [PATCH v3 0/6] drm/i915: per context slice/subslice powergating

Hi all, Another update, trying to minimize the number of reprogramming issued due to powergating configuration changes. This is achieved by tracking the last submitted powergating configuration in the engine submission mechanism and reprogramming only on configuration changes. Another

[Intel-gfx] [PATCH v3 6/6] drm/i915: Expose RPCS (SSEU) configuration to userspace

From: Chris Wilson We want to allow userspace to reconfigure the subslice configuration for its own use case. To do so, we expose a context parameter to allow adjustment of the RPCS register stored within the context image (and currently not accessible via LRI). If the

[Intel-gfx] [PATCH v3 3/6] drm/i915/perf: simplify configure all context function

We don't need any special treatment on error so just return as soon as possible. Signed-off-by: Lionel Landwerlin --- drivers/gpu/drm/i915/i915_perf.c | 11 --- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_perf.c

[Intel-gfx] [PATCH v3 5/6] drm/i915: count powergating transitions per engine

This can be used to monitor the number of powergating transition changes for a particular workload. Signed-off-by: Lionel Landwerlin --- drivers/gpu/drm/i915/intel_engine_cs.c | 2 ++ drivers/gpu/drm/i915/intel_lrc.c| 1 +

[Intel-gfx] [PATCH v3 2/6] drm/i915: Record the sseu configuration per-context & engine

From: Chris Wilson We want to expose the ability to reconfigure the slices, subslice and eu per context and per engine. To facilitate that, store the current configuration on the context for each engine, which is initially set to the device default upon creation. v2:

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for RFT agp/intel: Hit Grantsdale with a sledgehammer

== Series Details == Series: RFT agp/intel: Hit Grantsdale with a sledgehammer URL : https://patchwork.freedesktop.org/series/42882/ State : warning == Summary == $ dim checkpatch origin/drm-tip e6af4f2b7d53 RFT agp/intel: Hit Grantsdale with a sledgehammer -:20: ERROR:MISSING_SIGN_OFF:

Re: [Intel-gfx] [PATCH] drm/i915: Annotate timeline lock nesting

On 08/05/2018 16:35, Chris Wilson wrote: CI noticed <4>[ 23.430701] <4>[ 23.430706] WARNING: possible recursive locking detected <4>[ 23.430713] 4.17.0-rc4-CI-CI_DRM_4156+ #1 Not tainted <4>[ 23.430720]

Re: [Intel-gfx] [PATCH v2 3/7] drm/i915/execlists: Make submission tasklet hardirq safe

On 07/05/2018 14:57, Chris Wilson wrote: Prepare to allow the execlists submission to be run from underneath a hardirq timer context (and not just the current softirq context) as is required for fast preemption resets and context switches. Signed-off-by: Chris Wilson

Re: [Intel-gfx] [PATCH v2 4/7] drm/i915/guc: Make submission tasklet hardirq safe

On 07/05/2018 14:57, Chris Wilson wrote: Prepare to allow the GuC submission to be run from underneath a hardirq timer context (and not just the current softirq context) as is required for fast preemption resets and context switches. Signed-off-by: Chris Wilson ---

Re: [Intel-gfx] [PATCH v2 3/7] drm/i915/execlists: Make submission tasklet hardirq safe

On 07/05/2018 14:57, Chris Wilson wrote: Prepare to allow the execlists submission to be run from underneath a hardirq timer context (and not just the current softirq context) as is required for fast preemption resets and context switches. Signed-off-by: Chris Wilson

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gtt: Trust the uncached store to flush wcb (rev2)

== Series Details == Series: drm/i915/gtt: Trust the uncached store to flush wcb (rev2) URL : https://patchwork.freedesktop.org/series/42873/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4157_full -> Patchwork_8942_full = == Summary - SUCCESS == No regressions found.

[Intel-gfx] [PATCH i-g-t 1/7] trace.pl: Add support for colouring context execution

From: Tvrtko Ursulin Add the command line switch which uses different colours for different context execution boxes. v2: * Use HSL to simplify color generation. (Lionel) * Colour other boxes in the same colour but different shade so it is easier to follow the

[Intel-gfx] [PATCH i-g-t 7/7] trace.pl: Fix request split mode

From: Tvrtko Ursulin Request split mode had several bugs, both in the original version and also after the recent refactorings. One big one was that it wasn't considering different submit ports as a reason to split execution, and also that it was too time based instead

[Intel-gfx] [PATCH i-g-t 4/7] trace.pl: Fix engine busy accounting in split mode

From: Tvrtko Ursulin In split mode all requests have to be added up since they were previously re-arranged so there is no overlap. Signed-off-by: Tvrtko Ursulin Cc: John Harrison --- scripts/trace.pl | 3 ++- 1

[Intel-gfx] [PATCH i-g-t 3/7] trace.pl: Remove context squashing option

From: Tvrtko Ursulin Timeline id allocation order is not tied with engine ids any more. Remove the option which assumed that was the case in attempt to provide more readable timeline. Signed-off-by: Tvrtko Ursulin --- scripts/media-bench.pl

[Intel-gfx] [PATCH i-g-t 2/7] trace.pl: Improve readability of graphical timeline representation

From: Tvrtko Ursulin We add stripes for different stages of request execution so it is easier to follow one context in the multi-colour mode. Vertical stripe pattern indicates pipeline "blockages" - requests waiting for dependencies before they are runnable. Diagonal

[Intel-gfx] [PATCH i-g-t 5/7] trace.pl: Fix incomplete request handling

From: Tvrtko Ursulin Incomplete requests (no notify, no context complete) have to be corrected by looking at the engine timeline, and not the sorted-by-start-time view as was previously used. Per-engine timelines are generated on demand and cached for later use. v2:

[Intel-gfx] [PATCH i-g-t 6/7] trace.pl: Basic preemption support

From: Tvrtko Ursulin Just forget about earlier request_in events. Signed-off-by: Tvrtko Ursulin --- scripts/trace.pl | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/scripts/trace.pl b/scripts/trace.pl index

Re: [Intel-gfx] [PATCH] drm/i915: Annotate timeline lock nesting

On 05/08/2018 08:35 AM, Chris Wilson wrote: CI noticed <4>[ 23.430701] <4>[ 23.430706] WARNING: possible recursive locking detected <4>[ 23.430713] 4.17.0-rc4-CI-CI_DRM_4156+ #1 Not tainted <4>[ 23.430720]

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Annotate timeline lock nesting

== Series Details == Series: drm/i915: Annotate timeline lock nesting URL : https://patchwork.freedesktop.org/series/42881/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4158 -> Patchwork_8946 = == Summary - WARNING == Minor unknown changes coming with Patchwork_8946

  1   2   3   >