== Series Details ==
Series: drm/i915/selftests: Fix selftest_mocs for DGFX
URL : https://patchwork.freedesktop.org/series/73387/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7926 -> Patchwork_16551
Summary
---
== Series Details ==
Series: drm/i915/selftests: Fix selftest_mocs for DGFX
URL : https://patchwork.freedesktop.org/series/73387/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
682894ca6774 drm/i915/selftests: Fix selftest_mocs for DGFX
-:10: WARNING:COMMIT_LOG_LONG_LINE:
== Series Details ==
Series: drm/i915/tgl: Add Wa_1808121037 to tgl.
URL : https://patchwork.freedesktop.org/series/73379/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7926 -> Patchwork_16550
Summary
---
== Series Details ==
Series: drm/i915: Use engine wa list for Wa_1607090982
URL : https://patchwork.freedesktop.org/series/73374/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7926 -> Patchwork_16549
Summary
---
== Series Details ==
Series: drm: Add support for DP 1.4 Compliance edid corruption test (rev6)
URL : https://patchwork.freedesktop.org/series/70530/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7926 -> Patchwork_16548
== Series Details ==
Series: drm/i915: pfit/scaler rework prep stuff (rev2)
URL : https://patchwork.freedesktop.org/series/68409/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7926 -> Patchwork_16547
Summary
---
== Series Details ==
Series: series starting with [1/2] MAINTAINERS: Update drm/i915 bug filing URL
URL : https://patchwork.freedesktop.org/series/73371/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7926 -> Patchwork_16546
tree: git://anongit.freedesktop.org/drm-intel drm-intel-next-queued
head: c616d2387aeeb987f03eee848f04ffdc248c7aae
commit: c616d2387aeeb987f03eee848f04ffdc248c7aae [5/5] drm/i915/gt: Expand bad
CS completion event debug
config: i386-randconfig-h003-20200213 (attached as .config)
compiler:
== Series Details ==
Series: drm/i915: Ensure no conflicts with BIOS when updating Dbuf
URL : https://patchwork.freedesktop.org/series/73369/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7926 -> Patchwork_16545
Summary
== Series Details ==
Series: drm/i915: Force state->modeset=true when distrust_bios_wm==true
URL : https://patchwork.freedesktop.org/series/73367/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7926 -> Patchwork_16544
== Series Details ==
Series: series starting with [1/2] drm/i915: terminate reauth at stream
management failure
URL : https://patchwork.freedesktop.org/series/73282/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7909_full -> Patchwork_16517_full
== Series Details ==
Series: drm/i915/dsb: Pre allocate and late cleanup of cmd buffer (rev2)
URL : https://patchwork.freedesktop.org/series/73036/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7926 -> Patchwork_16543
== Series Details ==
Series: series starting with [1/2] drm/i915: split out vlv/chv specific
suspend/resume code
URL : https://patchwork.freedesktop.org/series/73365/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7926 -> Patchwork_16542
== Series Details ==
Series: series starting with [1/2] drm/i915: split out vlv/chv specific
suspend/resume code
URL : https://patchwork.freedesktop.org/series/73365/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
ae72e53c4c88 drm/i915: split out vlv/chv specific
== Series Details ==
Series: drm/i915: Move cec_notifier to intel_hdmi_connector_unregister, v2.
URL : https://patchwork.freedesktop.org/series/73362/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7926 -> Patchwork_16541
== Series Details ==
Series: drm/i915/hdcp: conversion to struct drm_device based logging macros.
URL : https://patchwork.freedesktop.org/series/73354/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7926 -> Patchwork_16540
Modify previous i915/gem_ctx_isolation "Check engine relative registers"
for modified mmio_base infrastructure.
Signed-off-by: Dale B Stimson
---
tests/i915/gem_ctx_isolation.c | 87 +++---
1 file changed, 48 insertions(+), 39 deletions(-)
diff --git
Signed-off-by: Dale B Stimson
---
lib/Makefile.sources | 2 +
lib/i915/gem_mmio_base.c | 353 +++
lib/i915/gem_mmio_base.h | 19 +++
lib/igt.h| 1 +
lib/meson.build | 1 +
5 files changed, 376 insertions(+)
create mode
At the start of igt_main, failure of the initial tests for successful
initialization transfer control to the end of an igt_fixture block.
>From there, execution of the main per-engine loop is attempted.
Instead, the test should be caused to exit.
If initialization fails, exit.
Signed-off-by:
From: Chris Wilson
Some of the non-privileged registers are at the same offset on each
engine. We can improve our coverage for unknown HW layout by using the
reported engine->mmio_base for relative offsets.
Signed-off-by: Chris Wilson
Reviewed-by: Dale B Stimson
---
Call igt_exit() after dealing with assumptions not valid for early calls.
In particular:
igt_exit() assumes that subtests have been considered for execution.
With --run-subtest, for an early exit (where subtests had not yet been
considered):
- igt_exit() would complain about "Unknown subtest"
-
v2:
- Introduce and use igt_exit_early() so that a failed initialization
(in igt_fixture) will not attempt to invoke the per-engine loop.
- Initialize mmio_base db inside initial igt_fixture instead of after.
- Some additional functions handle NULL input mmio_base db pointer.
- Variables mbp and
== Series Details ==
Series: drm/i915/hdcp: conversion to struct drm_device based logging macros.
URL : https://patchwork.freedesktop.org/series/73354/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
7a0324dd9a39 drm/i915/hdcp: conversion to struct drm_device based logging
== Series Details ==
Series: HDCP misc (rev2)
URL : https://patchwork.freedesktop.org/series/73345/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7926 -> Patchwork_16539
Summary
---
**SUCCESS**
No regressions
On 2/12/2020 4:34 PM, Chris Wilson wrote:
> Quoting Brian Welty (2020-02-13 00:14:18)
>> For DGFX devices, the MOCS control value is not initialized or used.
>
> Then why is the table populated?
> -Chris
>
The format has changed (been reduced?) for DGFX.
drm_i915_mocs_entry.l3cc_value is
== Series Details ==
Series: drm/dp, i915: eDP DPCD backlight control detection fixes (rev2)
URL : https://patchwork.freedesktop.org/series/72991/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7926 -> Patchwork_16538
Quoting Brian Welty (2020-02-13 00:14:18)
> For DGFX devices, the MOCS control value is not initialized or used.
Then why is the table populated?
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
== Series Details ==
Series: HDCP misc (rev2)
URL : https://patchwork.freedesktop.org/series/73345/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
3498b51721f6 drm/hdcp: optimizing the srm handling
cf23cf2eff64 drm/hdcp: fix DRM_HDCP_2_KSV_COUNT_2_LSBITS
d18de5c49d15 drm/i915:
For DGFX devices, the MOCS control value is not initialized or used.
Update the selftest to skip reading and checking control values
for these devices.
References: e6e2ac07118b ("drm/i915: do not set MOCS control values on dgfx")
Fixes: 3fb33cd32ffd ("drm/i915/selftests: Add coverage of mocs
== Series Details ==
Series: series starting with [v2,1/2] drm/i915/mst: Set intel_dp_set_m_n() for
MST slaves
URL : https://patchwork.freedesktop.org/series/7/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7926 -> Patchwork_16536
== Series Details ==
Series: series starting with [CI,1/2] drm/i915: Poison rings after use
URL : https://patchwork.freedesktop.org/series/73327/
State : failure
== Summary ==
Applying: drm/i915: Poison rings after use
Using index info to reconstruct a base tree...
M
My apologies for the multiple submissions of this patch series. I had to
work out an issue with an unsuspected git config value in order to make the
references function with patchwork.
On 2020-02-12 14:34:28, Dale B Stimson wrote:
> This patch series provides infrastructure to allow
From: Chris Wilson
Some of the non-privileged registers are at the same offset on each
engine. We can improve our coverage for unknown HW layout by using the
reported engine->mmio_base for relative offsets.
Signed-off-by: Chris Wilson
Reviewed-by: Dale B Stimson
---
This patch series provides infrastructure to allow determination of i915
per-engine mmio_base (which is otherwise sometimes hard to get). The provided
method uses debugfs mmio_base information if present. Otherwise, a default
determination is provided when possible. Also, gem_ctx_isolation is
Signed-off-by: Dale B Stimson
---
lib/Makefile.sources | 2 +
lib/i915/gem_mmio_base.c | 346 +++
lib/i915/gem_mmio_base.h | 19 +++
lib/igt.h| 1 +
lib/meson.build | 1 +
5 files changed, 369 insertions(+)
create mode
Modify previous i915/gem_ctx_isolation "Check engine relative registers"
for modified mmio_base infrastructure.
Signed-off-by: Dale B Stimson
---
tests/i915/gem_ctx_isolation.c | 87 +++---
1 file changed, 48 insertions(+), 39 deletions(-)
diff --git
On 11/02/2020 21:06, Andi Shyti wrote:
Hi Tvrtko,
+void intel_gt_sysfs_register(struct intel_gt *gt)
+{
+ struct kobject *parent =
kobject_get(>i915->drm.primary->kdev->kobj);
Does this needs a kobject_put to balance out somewhere?
Yes, I forgot the two kobject_put that are
== Series Details ==
Series: Commit early to GuC (rev3)
URL : https://patchwork.freedesktop.org/series/72031/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7925 -> Patchwork_16535
Summary
---
**SUCCESS**
No
On 2/11/20 5:47 PM, Andi Shyti wrote:
Hi Daniele,
+ if (intel_uc_uses_huc(uc)) {
+ ret = intel_huc_init(huc);
are we ever going to call intel_huc_init() if
!intel_uc_uses_huc()? if not, why don't check intel_uc_uses_huc()
inside intel_huc_init()? just to avoid always
== Series Details ==
Series: Commit early to GuC (rev3)
URL : https://patchwork.freedesktop.org/series/72031/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
86c2261830f8 drm/i915/debugfs: Pass guc_log struct to i915_guc_log_info
434763d74348 drm/i915/guc: Kill USES_GUC macro
== Series Details ==
Series: 3 display pipes combination system support (rev3)
URL : https://patchwork.freedesktop.org/series/72468/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7924 -> Patchwork_16534
Summary
---
== Series Details ==
Series: 3 display pipes combination system support (rev3)
URL : https://patchwork.freedesktop.org/series/72468/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
81842e985a7d drm/i915: Iterate over pipe and skip the disabled one
-:17:
== Series Details ==
Series: drm/i915/gt: Expand bad CS completion event debug
URL : https://patchwork.freedesktop.org/series/73335/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7924 -> Patchwork_16532
Summary
---
== Series Details ==
Series: drm/i915/gt: make a gt sysfs group and move power management files
(rev2)
URL : https://patchwork.freedesktop.org/series/73190/
State : failure
== Summary ==
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
DESCEND objtool
CHK
== Series Details ==
Series: series starting with [1/1] drm/i915: MCHBAR memory info registers are
moved since GEN 12.
URL : https://patchwork.freedesktop.org/series/73332/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7924 -> Patchwork_16531
It's not clear whether this workaround is final yet, but the BSpec
indicates that userspace needs to set bit 9 of this register on demand:
"To avoid sporadic corruptions “Set 0x7010[9] when Depth Buffer
Surface Format is D16_UNORM , surface type is not NULL & 1X_MSAA"
BugLink:
On Tue, Feb 11, 2020 at 10:50:08AM -0800, José Roberto de Souza wrote:
> The hotplug interruption detection was not being enabled for TC5 and
> TC6 in the north detection side.
TC5 and TC6 would be ports H & I. We're lacking handling in a few other
places as well (e.g., aux channels). I sent
Modify previous i915/gem_ctx_isolation "Check engine relative registers"
for modified mmio_base infrastructure.
Signed-off-by: Dale B Stimson
---
tests/i915/gem_ctx_isolation.c | 87 +++---
1 file changed, 48 insertions(+), 39 deletions(-)
diff --git
From: Chris Wilson
Some of the non-privileged registers are at the same offset on each
engine. We can improve our coverage for unknown HW layout by using the
reported engine->mmio_base for relative offsets.
Signed-off-by: Chris Wilson
Reviewed-by: Dale B Stimson
---
This patch series provides infrastructure to allow determination of i915
per-engine mmio_base (which is otherwise sometimes hard to get). The provided
method uses debugfs mmio_base information if present. Otherwise, a default
determination is provided when possible. Also, gem_ctx_isolation is
Signed-off-by: Dale B Stimson
---
lib/Makefile.sources | 2 +
lib/i915/gem_mmio_base.c | 346 +++
lib/i915/gem_mmio_base.h | 19 +++
lib/igt.h| 1 +
lib/meson.build | 1 +
5 files changed, 369 insertions(+)
create mode
== Series Details ==
Series: In order to readout DP SDPs, refactors the handling of DP SDPs (rev7)
URL : https://patchwork.freedesktop.org/series/72853/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7905_full -> Patchwork_16516_full
On Wed, 12 Feb 2020, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> We have to write quite a few registers when programming the
> pipe scaler. Let's use intel_de_write_fw() for these to reduce
> the lockdep overhead a bit. All plane registers (including plane
> scaler) already do this.
>
> We
On Wed, 12 Feb 2020, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Make the PFIT_PIPE stuff less ugly via parametrization.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_panel.c | 3 +--
> drivers/gpu/drm/i915/i915_reg.h| 1 +
> 2 files changed, 2
== Series Details ==
Series: drm/i915/tgl: Implement Wa_1606931601 (rev5)
URL : https://patchwork.freedesktop.org/series/72433/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7922 -> Patchwork_16530
Summary
---
On 2/12/20 11:56 AM, Alexey Budankov wrote:
On 12.02.2020 18:45, Stephen Smalley wrote:
On 2/12/20 10:21 AM, Stephen Smalley wrote:
On 2/12/20 8:53 AM, Alexey Budankov wrote:
On 12.02.2020 16:32, Stephen Smalley wrote:
On 2/12/20 3:53 AM, Alexey Budankov wrote:
Hi Stephen,
On 22.01.2020
On 2020-02-12 6:07 p.m., Nathan Chancellor wrote:
> On Wed, Feb 12, 2020 at 09:52:52AM +0100, Michel Dänzer wrote:
>> On 2020-02-11 9:39 p.m., Nathan Chancellor wrote:
>>> On Tue, Feb 11, 2020 at 10:41:48AM +0100, Michel Dänzer wrote:
On 2020-02-11 7:13 a.m., Nathan Chancellor wrote:
> A
Chris Wilson writes:
> BIT(14) is not sticking in 0xe4f4 so we have no idea if the w/a is still
Now we have some idea. It was in mcr range register thus verification
was doomed to fail. Fix in list.
-Mika
> in effect when it needs to be. Until that is resolved, remove the
> failing bit.
>
>
On Wed, Feb 12, 2020 at 09:52:52AM +0100, Michel Dänzer wrote:
> On 2020-02-11 9:39 p.m., Nathan Chancellor wrote:
> > On Tue, Feb 11, 2020 at 10:41:48AM +0100, Michel Dänzer wrote:
> >> On 2020-02-11 7:13 a.m., Nathan Chancellor wrote:
> >>> A recent commit in clang added -Wtautological-compare
== Series Details ==
Series: Revert "drm/i915: Implement Wa_1607090982"
URL : https://patchwork.freedesktop.org/series/73324/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7922 -> Patchwork_16529
Summary
---
This is in mcr range of register, thus we can only verify
it through mmio. Use engine wa list with mcr range verification
skip.
Fixes: 0db1a5f8706a ("drm/i915: Implement Wa_1607090982")
Cc: Chris Wilson
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 8 +---
On 12.02.2020 18:45, Stephen Smalley wrote:
> On 2/12/20 10:21 AM, Stephen Smalley wrote:
>> On 2/12/20 8:53 AM, Alexey Budankov wrote:
>>> On 12.02.2020 16:32, Stephen Smalley wrote:
On 2/12/20 3:53 AM, Alexey Budankov wrote:
> Hi Stephen,
>
> On 22.01.2020 17:07, Stephen
Unlike DP 1.2 edid corruption test, DP 1.4 requires to calculate
real CRC value of the last edid data block, and write it back.
Current edid CRC calculates routine adds the last CRC byte,
and check if non-zero.
This behavior is not accurate; actually, we need to return
the actual CRC value when
it's not the patch "Track engine round-trip times".
it's "drm/i915/gem: Asynchronous cmdparser" "drm/i915/gem: Prepare
gen7 cmdparser for async execution" bad for my Bay trail device.
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
Hi Dave, Daniel,
Now that -rc1 is out, here's the first drm-misc-next PR. All things
considered it's been pretty quiet, the diffstat being scary mostly
because of the conversion of device tree bindings to YAML and a new
driver.
Maxime
drm-misc-next-2020-02-10:
drm-misc-next for 5.7:
UAPI
Hi Daniele,
On Tue, Feb 11, 2020 at 04:31:17PM -0800, Daniele Ceraolo Spurio wrote:
> use intel_uc_uses_guc_submission() directly instead, to be consistent in
> the way we check what we want to do with the GuC.
>
> v2: do not go through ctx->vm->gt, use i915->gt instead
>
> Signed-off-by:
From: Ville Syrjälä
Follow the new naming convention and call the crtc state
"crtc_state", and while at it drop the redundant crtc argument.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/icl_dsi.c | 3 +-
drivers/gpu/drm/i915/display/intel_dp.c| 8 +-
From: Ville Syrjälä
We have to write quite a few registers when programming the
pipe scaler. Let's use intel_de_write_fw() for these to reduce
the lockdep overhead a bit. All plane registers (including plane
scaler) already do this.
We already had a few accidental intel_de_write_fw() in there.
From: Ville Syrjälä
Most of the pfit functions are of the form:
func()
{
if (pfit_enabled) {
...
}
}
Flip the pfit_enabled check around to flatten the functions.
And while we're touching all this let's do the usual
s/pipe_config/crtc_state/ replacement.
From: Ville Syrjälä
Pass the entire connector state to intel_{gmch,pch}_panel_fitting().
For now we just need to get at .scaling_mode but in the future we'll
want access to the margin properties as well.
v2: Deal with intel_dp_ycbcr420_config()
Signed-off-by: Ville Syrjälä
---
From: Ville Syrjälä
Change intel_{gmch,pch}_panel_fitting() to return a normal
error vs. success int. We'll need this later to validate that
the margin properties aren't misconfigured.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/icl_dsi.c | 10 +++---
From: Ville Syrjälä
Make the PFIT_PIPE stuff less ugly via parametrization.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_panel.c | 3 +--
drivers/gpu/drm/i915/i915_reg.h| 1 +
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git
From: Ville Syrjälä
Rebased pfit/scaler rework prep stuff. The eventual aim is to expose
margin properties for external displays. Main use of which is to
squish the image down a bit to avoid overscan on displays that insist
on always overscanning. That will happen via the pfit/pipe scaler.
And
From: Ville Syrjälä
Fix skl_update_scaler_crtc() to deal with different scaling
modes correctly. The current implementation assumes
DRM_MODE_SCALE_FULLSCREEN. Fortunately we don't expose any
border properties currently so the code does actually end
up doing the right thing (assigning a scaler
From: Ville Syrjälä
Make things a bit more abstract by replacing the pch_pfit.pos/size
raw register values with a drm_rect. Makes it slighly more convenient
to eg. compute the scaling factors.
v2: Use drm_rect_init()
Signed-off-by: Ville Syrjälä
---
On 12.02.2020 18:21, Stephen Smalley wrote:
> On 2/12/20 8:53 AM, Alexey Budankov wrote:
>> On 12.02.2020 16:32, Stephen Smalley wrote:
>>> On 2/12/20 3:53 AM, Alexey Budankov wrote:
Hi Stephen,
On 22.01.2020 17:07, Stephen Smalley wrote:
> On 1/22/20 5:45 AM, Alexey Budankov
We've moved from bugzilla to gitlab.
Cc: sta...@vger.kernel.org
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/Kconfig | 5 ++---
drivers/gpu/drm/i915/i915_gpu_error.c | 3 ++-
drivers/gpu/drm/i915/i915_utils.c | 5 ++---
3 files changed, 6 insertions(+), 7 deletions(-)
diff
We've moved from bugzilla to gitlab.
Cc: sta...@vger.kernel.org
Signed-off-by: Jani Nikula
---
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index b9d8f6c2fd24..3f9a78a726ae 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -8416,7 +8416,7
On 2/12/20 10:21 AM, Stephen Smalley wrote:
On 2/12/20 8:53 AM, Alexey Budankov wrote:
On 12.02.2020 16:32, Stephen Smalley wrote:
On 2/12/20 3:53 AM, Alexey Budankov wrote:
Hi Stephen,
On 22.01.2020 17:07, Stephen Smalley wrote:
On 1/22/20 5:45 AM, Alexey Budankov wrote:
On 21.01.2020
On Wed, 2020-02-12 at 17:36 +0200, Jani Nikula wrote:
> On Wed, 12 Feb 2020, Stanislav Lisovskiy <
> stanislav.lisovs...@intel.com> wrote:
> > TGL BIOS seems to enable both DBuf slices ocasionally, depending
> > how many displays are connected, while i915 according to BSpec
> > was powering on S1
On Wed, Feb 12, 2020 at 05:36:40PM +0200, Jani Nikula wrote:
> On Wed, 12 Feb 2020, Stanislav Lisovskiy
> wrote:
> > TGL BIOS seems to enable both DBuf slices ocasionally, depending
> > how many displays are connected, while i915 according to BSpec
> > was powering on S1 DBuf slice, until a
On 2/12/20 8:53 AM, Alexey Budankov wrote:
On 12.02.2020 16:32, Stephen Smalley wrote:
On 2/12/20 3:53 AM, Alexey Budankov wrote:
Hi Stephen,
On 22.01.2020 17:07, Stephen Smalley wrote:
On 1/22/20 5:45 AM, Alexey Budankov wrote:
On 21.01.2020 21:27, Alexey Budankov wrote:
On 21.01.2020
On Wed, 12 Feb 2020, Stanislav Lisovskiy wrote:
> TGL BIOS seems to enable both DBuf slices ocasionally, depending
> how many displays are connected, while i915 according to BSpec
> was powering on S1 DBuf slice, until a modeset was done.
>
> This was causing a brief flash during the boot as we
TGL BIOS seems to enable both DBuf slices ocasionally, depending
how many displays are connected, while i915 according to BSpec
was powering on S1 DBuf slice, until a modeset was done.
This was causing a brief flash during the boot as we were
disabling slice, previously used by BIOS with that.
On Wed, Feb 12, 2020 at 02:54:45PM +0100, Maarten Lankhorst wrote:
> This fixes the following KASAN splash on module reload:
> [ 145.136327]
> ==
> [ 145.136502] BUG: KASAN: use-after-free in intel_hdmi_destroy+0x74/0x80
> [i915]
On Wed, 2020-02-12 at 17:01 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Currently when we load the driver we set distrust_bios_wm=true, which
> will cause active_pipe_changes to get flagged even when we're not
> toggling any pipes on/off. The reason being that we want to fully
>
From: Ville Syrjälä
Currently when we load the driver we set distrust_bios_wm=true, which
will cause active_pipe_changes to get flagged even when we're not
toggling any pipes on/off. The reason being that we want to fully
redistribute the dbuf among the active pipes and ignore whatever
state the
Pre-allocate command buffer in atomic_commit using intel_dsb_prepare
function which also includes pinning and map in cpu domain.
No change is dsb write/commit functions.
Now dsb get/put function is refactored and currently used only for
reference counting. Below dsb api added to do respective
On Wed, 12 Feb 2020, Zhenyu Wang wrote:
> Hi,
>
> Here's two fixes for gvt. One for missed locking and another for
> firmware allocation change for late load.
Pulled, thanks.
BR,
Jani.
>
> Thanks
> --
> The following changes since commit 5e822e44cecec1ea48925630aa31dfac827fd202:
>
>
== Series Details ==
Series: drm/i915/display/tgl: Enable hotplug detection in TC5 and TC6
URL : https://patchwork.freedesktop.org/series/73267/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7904_full -> Patchwork_16513_full
i915_drv.c is a fairly big file, and having very specific vlv/chv
suspend/resume code in it is a distraction. Split it out to a new
vlv_suspend.[ch] file.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/Makefile | 3 +-
drivers/gpu/drm/i915/i915_drv.c| 498
Prefer intel_uncore_* over I915_READ, I915_WRITE, and POSTING_READ.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/vlv_suspend.c | 237 +++--
1 file changed, 121 insertions(+), 116 deletions(-)
diff --git a/drivers/gpu/drm/i915/vlv_suspend.c
On Mon, Jan 27, 2020 at 12:18:17PM +, Chris Wilson wrote:
> We [will] expose various per-engine scheduling controls. One of which,
> 'heartbeat_duration_ms', defines how often we send a heartbeat down the
> engine to check upon the health of the engine. If a heartbeat does not
> complete
On Mon, Jan 27, 2020 at 12:18:16PM +, Chris Wilson wrote:
> We [will] expose various per-engine scheduling controls. One of which,
> 'preempt_timeout_ms', defines how we wait for a preemption request to be
> honoured by the currently executing context. If it fails to relieve the
> GPU within
This fixes the following KASAN splash on module reload:
[ 145.136327]
==
[ 145.136502] BUG: KASAN: use-after-free in intel_hdmi_destroy+0x74/0x80 [i915]
[ 145.136514] Read of size 8 at addr 888216641830 by task kworker/1:1/134
On 12.02.2020 16:32, Stephen Smalley wrote:
> On 2/12/20 3:53 AM, Alexey Budankov wrote:
>> Hi Stephen,
>>
>> On 22.01.2020 17:07, Stephen Smalley wrote:
>>> On 1/22/20 5:45 AM, Alexey Budankov wrote:
On 21.01.2020 21:27, Alexey Budankov wrote:
>
> On 21.01.2020 20:55, Alexei
On Tue, Feb 11, 2020 at 10:55:26PM +0530, Anshuman Gupta wrote:
> It should not be assumed that a disabled display pipe will be
> always last the pipe.
> for_each_pipe() should iterate over I915_MAX_PIPES and check
> for the disabled pipe and skip that pipe so that it should not
> initialize the
On 2/12/20 3:53 AM, Alexey Budankov wrote:
Hi Stephen,
On 22.01.2020 17:07, Stephen Smalley wrote:
On 1/22/20 5:45 AM, Alexey Budankov wrote:
On 21.01.2020 21:27, Alexey Budankov wrote:
On 21.01.2020 20:55, Alexei Starovoitov wrote:
On Tue, Jan 21, 2020 at 9:31 AM Alexey Budankov
wrote:
== Series Details ==
Series: HDCP 2.2 Comp fixes
URL : https://patchwork.freedesktop.org/series/73323/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7919 -> Patchwork_16528
Summary
---
**SUCCESS**
No regressions
Chris Wilson writes:
> Show the ring/request/context state if we see what we believe is an
> early CS completion.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gt/intel_context.c | 3 ++-
> drivers/gpu/drm/i915/gt/intel_lrc.c | 31
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