Re: [Intel-gfx] [PATCH 14/14] Doc/gpu/rfc/i915: i915 DG2 uAPI
On Mon, Oct 11, 2021 at 9:10 AM Ramalingam C wrote: > > Details of the new features getting added as part of DG2 enabling and their > implicit impact on the uAPI. > > Signed-off-by: Ramalingam C > cc: Daniel Vetter > cc: Matthew Auld > --- > Documentation/gpu/rfc/i915_dg2.rst | 47 ++ > Documentation/gpu/rfc/index.rst| 3 ++ > 2 files changed, 50 insertions(+) > create mode 100644 Documentation/gpu/rfc/i915_dg2.rst > > diff --git a/Documentation/gpu/rfc/i915_dg2.rst > b/Documentation/gpu/rfc/i915_dg2.rst > new file mode 100644 > index ..a83ca26cd758 > --- /dev/null > +++ b/Documentation/gpu/rfc/i915_dg2.rst > @@ -0,0 +1,47 @@ > + > +I915 DG2 RFC Section > + > + > +Upstream plan > += > +Plan to upstream the DG2 enabling is: > + > +* Merge basic HW enabling for DG2(Still without pciid) here and everywhere below, missing space before ( > +* Merge the 64k support for lmem > +* Merge the flat CCS enabling patches > +* Add the pciid for DG2 and enable the DG2 in CI > + > + > +64K page support for lmem > += > +On DG2 hw, local-memory supports minimum GTT page size of 64k only. 4k is > not supported anymore. > + > +DG2 hw dont support the 64k(lmem) and 4k(smem) pages in the same ppgtt Page > table. Refer the s/hw dont/doesn't/ > +struct drm_i915_gem_create_ext for the implication of handling the 64k page > size. > + > +.. kernel-doc:: include/uapi/drm/i915_drm.h > +:functions: drm_i915_gem_create_ext > + > + > +flat CCS support for lmem Flat > += > +Gen 12+ devices support 3D surfaces compression and compression formats. > This is > +accomplished by an additional compression control state (CCS) stored for > each surface. > + > +Gen 12 devices(TGL and DG1) stores compression state in a separate region of > memory. s/stores/store/ > +It is managed by userspace and has an associated set of userspace managed > page tables > +used by hardware for address translation. > + > +In Gen 12.5 devices(XEXPSDV and DG2) Flat CCS is introduced to replace the > userspace There is no such thing as Gen 12.5. The "Gen" nomenclature stopped on Gen 12. Lucas De Marchi > +managed AUX pagetable with the flat indexed region of device memory for > storing the > +compression state > + > +GOP Driver steals a chunk of memory for the CCS surface corresponding to the > entire > +range of local memory. The memory required for the CCS of the entire local > memory is > +1/256 of the main local memory. The Gop driver will also program a secure > register > +(XEHPSDV_FLAT_CCS_BASE_ADDR 0x4910) with this address value. > + > +So the Total local memory available for driver allocation is Total lmem size > - CCS data size > + > +Flat CCS data needs to be cleared when a lmem object is allocated. And CCS > data can > +be copied in and out of CCS region through XY_CTRL_SURF_COPY_BLT. > diff --git a/Documentation/gpu/rfc/index.rst b/Documentation/gpu/rfc/index.rst > index 91e93a705230..afb320ed4028 100644 > --- a/Documentation/gpu/rfc/index.rst > +++ b/Documentation/gpu/rfc/index.rst > @@ -20,6 +20,9 @@ host such documentation: > > i915_gem_lmem.rst > > +.. toctree:: > +i915_dg2.rst > + > .. toctree:: > > i915_scheduler.rst > -- > 2.20.1 >
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display: refactor plane config + pin out (rev2)
== Series Details ==
Series: drm/i915/display: refactor plane config + pin out (rev2)
URL : https://patchwork.freedesktop.org/series/95541/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10720 -> Patchwork_21314
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21314/index.html
Known issues
Here are the changes found in Patchwork_21314 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@cs-compute:
- fi-elk-e7500: NOTRUN -> [SKIP][1] ([fdo#109271]) +49 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21314/fi-elk-e7500/igt@amdgpu/amd_ba...@cs-compute.html
* igt@amdgpu/amd_basic@semaphore:
- fi-bdw-5557u: NOTRUN -> [SKIP][2] ([fdo#109271]) +23 similar issues
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21314/fi-bdw-5557u/igt@amdgpu/amd_ba...@semaphore.html
* igt@i915_selftest@live@hangcheck:
- fi-snb-2600:[PASS][3] -> [INCOMPLETE][4] ([i915#3921])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10720/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21314/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
* igt@kms_frontbuffer_tracking@basic:
- fi-cml-u2: [PASS][5] -> [DMESG-WARN][6] ([i915#4269])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10720/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21314/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
[i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
[i915#4269]: https://gitlab.freedesktop.org/drm/intel/issues/4269
Participating hosts (35 -> 33)
--
Additional (1): fi-elk-e7500
Missing(3): fi-jsl-1 fi-bsw-cyan fi-ilk-650
Build changes
-
* Linux: CI_DRM_10720 -> Patchwork_21314
CI-20190529: 20190529
CI_DRM_10720: 8a8d1f74b64edddbbb43fa4be5e438a12ba70707 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6242: 721fd85ee95225ed5df322f7182bdfa9b86a3e68 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_21314: 71cfd613f6977b69d62e8c42e20c9819a5e2b7e3 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
71cfd613f697 drm/i915/display: drop unused parameter to dpt pin
11c921fdcfbf drm/i915/display: move fbdev pin code into fb_pin
e08334b38c2a drm/i915/display: refactor fbdev pin/unpin out into functions.
32d63dc32c0a drm/i915/display: move pin/unpin fb/plane code to a new file.
db2228c1c8b5 drm/i915/display: refactor initial plane config to a separate file
fe9de0be3625 drm/i915/display: refactor out initial plane config for crtcs
719e999a3ade drm/i915/display: let intel_plane_uses_fence be used from other
places.
569a494f9314 drm/i915/display: move plane prepare/cleanup to
intel_atomic_plane.c
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21314/index.html
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/display: refactor plane config + pin out (rev2)
== Series Details == Series: drm/i915/display: refactor plane config + pin out (rev2) URL : https://patchwork.freedesktop.org/series/95541/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/display/intel_fbdev.c:222:60:expected void **vaddr +drivers/gpu/drm/i915/display/intel_fbdev.c:222:60:got void [noderef] __iomem ** +drivers/gpu/drm/i915/display/intel_fbdev.c:222:60: warning: incorrect type in argument 3 (different address spaces) +drivers/gpu/drm/i915/display/intel_fb_pin.c:290:16:expected void * +drivers/gpu/drm/i915/display/intel_fb_pin.c:290:16:got void [noderef] __iomem * +drivers/gpu/drm/i915/display/intel_fb_pin.c:290:16: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_reset.c:1392:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/i915_perf.c:1442:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1496:15: warning: memset with byte count of 16777216 +./include/asm-generic/bitops/find.h:112:45: warning: shift count is negative (-262080) +./include/asm-generic/bitops/find.h:32:31: warning: shift count is negative (-262080) +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/display: refactor plane config + pin out (rev2)
== Series Details ==
Series: drm/i915/display: refactor plane config + pin out (rev2)
URL : https://patchwork.freedesktop.org/series/95541/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
569a494f9314 drm/i915/display: move plane prepare/cleanup to
intel_atomic_plane.c
-:38: WARNING:UNSPECIFIED_INT: Prefer 'unsigned int' to bare use of 'unsigned'
#38: FILE: drivers/gpu/drm/i915/display/intel_atomic_plane.c:613:
+ unsigned mode, int sync, void *key)
-:157: CHECK:LINE_SPACING: Please don't use multiple blank lines
#157: FILE: drivers/gpu/drm/i915/display/intel_atomic_plane.c:732:
+
+
total: 0 errors, 1 warnings, 1 checks, 456 lines checked
719e999a3ade drm/i915/display: let intel_plane_uses_fence be used from other
places.
fe9de0be3625 drm/i915/display: refactor out initial plane config for crtcs
db2228c1c8b5 drm/i915/display: refactor initial plane config to a separate file
-:363: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#363:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 626 lines checked
32d63dc32c0a drm/i915/display: move pin/unpin fb/plane code to a new file.
-:351: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#351:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 621 lines checked
e08334b38c2a drm/i915/display: refactor fbdev pin/unpin out into functions.
-:29: WARNING:BRACES: braces {} are not necessary for single statement blocks
#29: FILE: drivers/gpu/drm/i915/display/intel_fbdev.c:184:
+ if (IS_ERR(ifbdev->vma)) {
+ return PTR_ERR(ifbdev->vma);
+ }
-:74: WARNING:BRACES: braces {} are not necessary for single statement blocks
#74: FILE: drivers/gpu/drm/i915/display/intel_fbdev.c:252:
+ if (ret) {
goto out_unlock;
}
total: 0 errors, 2 warnings, 0 checks, 117 lines checked
11c921fdcfbf drm/i915/display: move fbdev pin code into fb_pin
-:49: WARNING:BRACES: braces {} are not necessary for single statement blocks
#49: FILE: drivers/gpu/drm/i915/display/intel_fb_pin.c:287:
+ if (IS_ERR(ifbdev->vma)) {
+ return PTR_ERR(ifbdev->vma);
+ }
total: 0 errors, 1 warnings, 0 checks, 111 lines checked
71cfd613f697 drm/i915/display: drop unused parameter to dpt pin
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/selftests: Allow engine reset failure to do a GT reset in hangcheck selftest
== Series Details == Series: drm/i915/selftests: Allow engine reset failure to do a GT reset in hangcheck selftest URL : https://patchwork.freedesktop.org/series/95702/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10719_full -> Patchwork_21313_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_21313_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_21313_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_21313_full: ### IGT changes ### Possible regressions * igt@gem_fenced_exec_thrash@no-spare-fences-interruptible: - shard-snb: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10719/shard-snb2/igt@gem_fenced_exec_thr...@no-spare-fences-interruptible.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21313/shard-snb2/igt@gem_fenced_exec_thr...@no-spare-fences-interruptible.html * igt@kms_flip_tiling@flip-changes-tiling-yf: - shard-tglb: NOTRUN -> [SKIP][3] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21313/shard-tglb3/igt@kms_flip_til...@flip-changes-tiling-yf.html * igt@kms_frontbuffer_tracking@fbc-suspend: - shard-kbl: [PASS][4] -> [INCOMPLETE][5] [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10719/shard-kbl1/igt@kms_frontbuffer_track...@fbc-suspend.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21313/shard-kbl3/igt@kms_frontbuffer_track...@fbc-suspend.html Known issues Here are the changes found in Patchwork_21313_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_create@create-massive: - shard-apl: NOTRUN -> [DMESG-WARN][6] ([i915#3002]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21313/shard-apl8/igt@gem_cre...@create-massive.html * igt@gem_ctx_persistence@legacy-engines-queued: - shard-snb: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#1099]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21313/shard-snb7/igt@gem_ctx_persiste...@legacy-engines-queued.html * igt@gem_exec_fair@basic-flow@rcs0: - shard-tglb: [PASS][8] -> [FAIL][9] ([i915#2842]) +1 similar issue [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10719/shard-tglb1/igt@gem_exec_fair@basic-f...@rcs0.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21313/shard-tglb6/igt@gem_exec_fair@basic-f...@rcs0.html * igt@gem_exec_fair@basic-none-rrul@rcs0: - shard-glk: [PASS][10] -> [FAIL][11] ([i915#2842]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10719/shard-glk7/igt@gem_exec_fair@basic-none-r...@rcs0.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21313/shard-glk3/igt@gem_exec_fair@basic-none-r...@rcs0.html * igt@gem_exec_fair@basic-none-share@rcs0: - shard-iclb: [PASS][12] -> [FAIL][13] ([i915#2842]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10719/shard-iclb5/igt@gem_exec_fair@basic-none-sh...@rcs0.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21313/shard-iclb3/igt@gem_exec_fair@basic-none-sh...@rcs0.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-tglb: NOTRUN -> [FAIL][14] ([i915#2842]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21313/shard-tglb3/igt@gem_exec_fair@basic-pace-sh...@rcs0.html * igt@gem_exec_fair@basic-pace@vcs1: - shard-iclb: NOTRUN -> [FAIL][15] ([i915#2842]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21313/shard-iclb4/igt@gem_exec_fair@basic-p...@vcs1.html * igt@gem_exec_fair@basic-pace@vecs0: - shard-kbl: [PASS][16] -> [FAIL][17] ([i915#2842]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10719/shard-kbl7/igt@gem_exec_fair@basic-p...@vecs0.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21313/shard-kbl4/igt@gem_exec_fair@basic-p...@vecs0.html * igt@gem_pxp@reject-modify-context-protection-off-2: - shard-tglb: NOTRUN -> [SKIP][18] ([i915#4270]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21313/shard-tglb3/igt@gem_...@reject-modify-context-protection-off-2.html * igt@gem_userptr_blits@coherency-sync: - shard-tglb: NOTRUN -> [SKIP][19] ([fdo#110542]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21313/shard-tglb3/igt@gem_userptr_bl...@coherency-sync.html * igt@gem_workarounds@suspend-resume-context: - shard-tglb: [PASS][20] -> [INCOMPLETE][21] ([i915#456]) [20]:
[Intel-gfx] [PATCH 8/8] drm/i915/display: drop unused parameter to dpt pin
From: Dave Airlie
The uses_fence isn't used.
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_fb_pin.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fb_pin.c
b/drivers/gpu/drm/i915/display/intel_fb_pin.c
index 7233a2d3c326..1005d36318d1 100644
--- a/drivers/gpu/drm/i915/display/intel_fb_pin.c
+++ b/drivers/gpu/drm/i915/display/intel_fb_pin.c
@@ -18,7 +18,6 @@
static struct i915_vma *
intel_pin_fb_obj_dpt(struct drm_framebuffer *fb,
const struct i915_ggtt_view *view,
-bool uses_fence,
unsigned long *out_flags,
struct i915_address_space *vm)
{
@@ -236,7 +235,7 @@ int intel_plane_pin_fb(struct intel_plane_state
*plane_state)
plane_state->ggtt_vma = vma;
- vma = intel_pin_fb_obj_dpt(fb, _state->view.gtt, false,
+ vma = intel_pin_fb_obj_dpt(fb, _state->view.gtt,
_state->flags,
intel_fb->dpt_vm);
if (IS_ERR(vma)) {
intel_dpt_unpin(intel_fb->dpt_vm);
--
2.25.4
[Intel-gfx] [PATCH 7/8] drm/i915/display: move fbdev pin code into fb_pin
From: Dave Airlie
This moves the fbdev pin code over and moves the internal
interfaces to static.
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_fb_pin.c | 34 +++--
drivers/gpu/drm/i915/display/intel_fb_pin.h | 15 -
drivers/gpu/drm/i915/display/intel_fbdev.c | 29 --
3 files changed, 38 insertions(+), 40 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fb_pin.c
b/drivers/gpu/drm/i915/display/intel_fb_pin.c
index 3f77f3013584..7233a2d3c326 100644
--- a/drivers/gpu/drm/i915/display/intel_fb_pin.c
+++ b/drivers/gpu/drm/i915/display/intel_fb_pin.c
@@ -71,7 +71,7 @@ intel_pin_fb_obj_dpt(struct drm_framebuffer *fb,
return vma;
}
-struct i915_vma *
+static struct i915_vma *
intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
bool phys_cursor,
const struct i915_ggtt_view *view,
@@ -199,7 +199,8 @@ intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
return vma;
}
-void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags)
+static void
+intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags)
{
if (flags & PLANE_HAS_FENCE)
i915_vma_unpin_fence(vma);
@@ -272,3 +273,32 @@ void intel_plane_unpin_fb(struct intel_plane_state
*old_plane_state)
intel_dpt_unpin(intel_fb->dpt_vm);
}
}
+
+int intel_fbdev_pin_and_fence(struct drm_i915_private *dev_priv,
+ struct intel_fbdev *ifbdev,
+ void **vaddr)
+{
+ const struct i915_ggtt_view view = {
+ .type = I915_GGTT_VIEW_NORMAL,
+ };
+ ifbdev->vma = intel_pin_and_fence_fb_obj(>fb->base, false,
+, false,
>vma_flags);
+
+ if (IS_ERR(ifbdev->vma)) {
+ return PTR_ERR(ifbdev->vma);
+ }
+
+ *vaddr = i915_vma_pin_iomap(ifbdev->vma);
+ if (IS_ERR(*vaddr)) {
+ drm_err(_priv->drm,
+ "Failed to remap framebuffer into virtual memory\n");
+ return PTR_ERR(vaddr);
+ }
+ return 0;
+}
+
+void intel_fbdev_unpin(struct intel_fbdev *ifbdev)
+{
+ if (ifbdev->vma)
+ intel_unpin_fb_vma(ifbdev->vma, ifbdev->vma_flags);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_fb_pin.h
b/drivers/gpu/drm/i915/display/intel_fb_pin.h
index e4fcd0218d9d..88d736264348 100644
--- a/drivers/gpu/drm/i915/display/intel_fb_pin.h
+++ b/drivers/gpu/drm/i915/display/intel_fb_pin.h
@@ -8,21 +8,18 @@
#include
+struct drm_i915_private;
struct drm_framebuffer;
+struct intel_fbdev;
struct i915_vma;
struct intel_plane_state;
struct i915_ggtt_view;
-struct i915_vma *
-intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
- bool phys_cursor,
- const struct i915_ggtt_view *view,
- bool uses_fence,
- unsigned long *out_flags);
-
-void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags);
-
int intel_plane_pin_fb(struct intel_plane_state *plane_state);
void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state);
+int intel_fbdev_pin_and_fence(struct drm_i915_private *dev_priv,
+ struct intel_fbdev *ifbdev,
+ void **vaddr);
+void intel_fbdev_unpin(struct intel_fbdev *ifbdev);
#endif
diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c
b/drivers/gpu/drm/i915/display/intel_fbdev.c
index 7ac9348d20c5..cee85fcc2085 100644
--- a/drivers/gpu/drm/i915/display/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/display/intel_fbdev.c
@@ -171,35 +171,6 @@ static int intelfb_alloc(struct drm_fb_helper *helper,
return 0;
}
-static int intel_fbdev_pin_and_fence(struct drm_i915_private *dev_priv,
-struct intel_fbdev *ifbdev,
-void **vaddr)
-{
- const struct i915_ggtt_view view = {
- .type = I915_GGTT_VIEW_NORMAL,
- };
- ifbdev->vma = intel_pin_and_fence_fb_obj(>fb->base, false,
-, false,
>vma_flags);
-
- if (IS_ERR(ifbdev->vma)) {
- return PTR_ERR(ifbdev->vma);
- }
-
- *vaddr = i915_vma_pin_iomap(ifbdev->vma);
- if (IS_ERR(*vaddr)) {
- drm_err(_priv->drm,
- "Failed to remap framebuffer into virtual memory\n");
- return PTR_ERR(vaddr);
- }
- return 0;
-}
-
-static void intel_fbdev_unpin(struct intel_fbdev *ifbdev)
-{
- if (ifbdev->vma)
- intel_unpin_fb_vma(ifbdev->vma, ifbdev->vma_flags);
-}
-
static int intelfb_create(struct drm_fb_helper *helper,
struct drm_fb_helper_surface_size *sizes)
{
--
2.25.4
[Intel-gfx] [PATCH 6/8] drm/i915/display: refactor fbdev pin/unpin out into functions.
From: Dave Airlie
This just cleans up the calls a bit.
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_fbdev.c | 64 +-
1 file changed, 38 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c
b/drivers/gpu/drm/i915/display/intel_fbdev.c
index adc3a81be9f7..7ac9348d20c5 100644
--- a/drivers/gpu/drm/i915/display/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/display/intel_fbdev.c
@@ -171,6 +171,35 @@ static int intelfb_alloc(struct drm_fb_helper *helper,
return 0;
}
+static int intel_fbdev_pin_and_fence(struct drm_i915_private *dev_priv,
+struct intel_fbdev *ifbdev,
+void **vaddr)
+{
+ const struct i915_ggtt_view view = {
+ .type = I915_GGTT_VIEW_NORMAL,
+ };
+ ifbdev->vma = intel_pin_and_fence_fb_obj(>fb->base, false,
+, false,
>vma_flags);
+
+ if (IS_ERR(ifbdev->vma)) {
+ return PTR_ERR(ifbdev->vma);
+ }
+
+ *vaddr = i915_vma_pin_iomap(ifbdev->vma);
+ if (IS_ERR(*vaddr)) {
+ drm_err(_priv->drm,
+ "Failed to remap framebuffer into virtual memory\n");
+ return PTR_ERR(vaddr);
+ }
+ return 0;
+}
+
+static void intel_fbdev_unpin(struct intel_fbdev *ifbdev)
+{
+ if (ifbdev->vma)
+ intel_unpin_fb_vma(ifbdev->vma, ifbdev->vma_flags);
+}
+
static int intelfb_create(struct drm_fb_helper *helper,
struct drm_fb_helper_surface_size *sizes)
{
@@ -181,13 +210,8 @@ static int intelfb_create(struct drm_fb_helper *helper,
struct drm_i915_private *dev_priv = to_i915(dev);
struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
struct i915_ggtt *ggtt = _priv->ggtt;
- const struct i915_ggtt_view view = {
- .type = I915_GGTT_VIEW_NORMAL,
- };
intel_wakeref_t wakeref;
struct fb_info *info;
- struct i915_vma *vma;
- unsigned long flags = 0;
bool prealloc = false;
void __iomem *vaddr;
struct drm_i915_gem_object *obj;
@@ -224,10 +248,8 @@ static int intelfb_create(struct drm_fb_helper *helper,
* This also validates that any existing fb inherited from the
* BIOS is suitable for own access.
*/
- vma = intel_pin_and_fence_fb_obj(>fb->base, false,
-, false, );
- if (IS_ERR(vma)) {
- ret = PTR_ERR(vma);
+ ret = intel_fbdev_pin_and_fence(dev_priv, ifbdev, );
+ if (ret) {
goto out_unlock;
}
@@ -261,19 +283,12 @@ static int intelfb_create(struct drm_fb_helper *helper,
/* Our framebuffer is the entirety of fbdev's system memory */
info->fix.smem_start =
- (unsigned long)(ggtt->gmadr.start + vma->node.start);
- info->fix.smem_len = vma->node.size;
+ (unsigned long)(ggtt->gmadr.start +
ifbdev->vma->node.start);
+ info->fix.smem_len = ifbdev->vma->node.size;
}
- vaddr = i915_vma_pin_iomap(vma);
- if (IS_ERR(vaddr)) {
- drm_err(_priv->drm,
- "Failed to remap framebuffer into virtual memory\n");
- ret = PTR_ERR(vaddr);
- goto out_unpin;
- }
info->screen_base = vaddr;
- info->screen_size = vma->node.size;
+ info->screen_size = ifbdev->vma->node.size;
drm_fb_helper_fill_info(info, >helper, sizes);
@@ -281,23 +296,21 @@ static int intelfb_create(struct drm_fb_helper *helper,
* If the object is stolen however, it will be full of whatever
* garbage was left in there.
*/
- if (!i915_gem_object_is_shmem(vma->obj) && !prealloc)
+ if (!i915_gem_object_is_shmem(ifbdev->vma->obj) && !prealloc)
memset_io(info->screen_base, 0, info->screen_size);
/* Use default scratch pixmap (info->pixmap.flags = FB_PIXMAP_SYSTEM) */
drm_dbg_kms(_priv->drm, "allocated %dx%d fb: 0x%08x\n",
ifbdev->fb->base.width, ifbdev->fb->base.height,
- i915_ggtt_offset(vma));
- ifbdev->vma = vma;
- ifbdev->vma_flags = flags;
+ i915_ggtt_offset(ifbdev->vma));
intel_runtime_pm_put(_priv->runtime_pm, wakeref);
vga_switcheroo_client_fb_set(pdev, info);
return 0;
out_unpin:
- intel_unpin_fb_vma(vma, flags);
+ intel_fbdev_unpin(ifbdev);
out_unlock:
intel_runtime_pm_put(_priv->runtime_pm, wakeref);
return ret;
@@ -316,8 +329,7 @@ static void intel_fbdev_destroy(struct intel_fbdev *ifbdev)
drm_fb_helper_fini(>helper);
- if (ifbdev->vma)
- intel_unpin_fb_vma(ifbdev->vma, ifbdev->vma_flags);
+ intel_fbdev_unpin(ifbdev);
[Intel-gfx] [PATCH 5/8] drm/i915/display: move pin/unpin fb/plane code to a new file.
From: Dave Airlie
This just moves this code out of the i915_display.c into a new
standalone file.
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/Makefile | 1 +
.../gpu/drm/i915/display/intel_atomic_plane.c | 1 +
drivers/gpu/drm/i915/display/intel_cursor.c | 2 +-
drivers/gpu/drm/i915/display/intel_display.c | 258 -
drivers/gpu/drm/i915/display/intel_display.h | 8 -
drivers/gpu/drm/i915/display/intel_fb_pin.c | 274 ++
drivers/gpu/drm/i915/display/intel_fb_pin.h | 28 ++
drivers/gpu/drm/i915/display/intel_fbdev.c| 1 +
8 files changed, 306 insertions(+), 267 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_fb_pin.c
create mode 100644 drivers/gpu/drm/i915/display/intel_fb_pin.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 5d9794d80bc2..f35485806ec5 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -216,6 +216,7 @@ i915-y += \
display/intel_drrs.o \
display/intel_dsb.o \
display/intel_fb.o \
+ display/intel_fb_pin.o \
display/intel_fbc.o \
display/intel_fdi.o \
display/intel_fifo_underrun.o \
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index 53ee56453270..0be8c00e3db9 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -39,6 +39,7 @@
#include "intel_atomic_plane.h"
#include "intel_cdclk.h"
#include "intel_display_types.h"
+#include "intel_fb_pin.h"
#include "intel_pm.h"
#include "intel_sprite.h"
#include "gt/intel_rps.h"
diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c
b/drivers/gpu/drm/i915/display/intel_cursor.c
index f6dcb5aa63f6..11842f212613 100644
--- a/drivers/gpu/drm/i915/display/intel_cursor.c
+++ b/drivers/gpu/drm/i915/display/intel_cursor.c
@@ -17,7 +17,7 @@
#include "intel_display_types.h"
#include "intel_display.h"
#include "intel_fb.h"
-
+#include "intel_fb_pin.h"
#include "intel_frontbuffer.h"
#include "intel_pm.h"
#include "intel_psr.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index b0684537f987..0fe3c2f50971 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -862,198 +862,6 @@ bool intel_plane_uses_fence(const struct
intel_plane_state *plane_state)
plane_state->view.gtt.type == I915_GGTT_VIEW_NORMAL);
}
-static struct i915_vma *
-intel_pin_fb_obj_dpt(struct drm_framebuffer *fb,
-const struct i915_ggtt_view *view,
-bool uses_fence,
-unsigned long *out_flags,
-struct i915_address_space *vm)
-{
- struct drm_device *dev = fb->dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
- struct drm_i915_gem_object *obj = intel_fb_obj(fb);
- struct i915_vma *vma;
- u32 alignment;
- int ret;
-
- if (WARN_ON(!i915_gem_object_is_framebuffer(obj)))
- return ERR_PTR(-EINVAL);
-
- alignment = 4096 * 512;
-
- atomic_inc(_priv->gpu_error.pending_fb_pin);
-
- ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
- if (ret) {
- vma = ERR_PTR(ret);
- goto err;
- }
-
- vma = i915_vma_instance(obj, vm, view);
- if (IS_ERR(vma))
- goto err;
-
- if (i915_vma_misplaced(vma, 0, alignment, 0)) {
- ret = i915_vma_unbind(vma);
- if (ret) {
- vma = ERR_PTR(ret);
- goto err;
- }
- }
-
- ret = i915_vma_pin(vma, 0, alignment, PIN_GLOBAL);
- if (ret) {
- vma = ERR_PTR(ret);
- goto err;
- }
-
- vma->display_alignment = max_t(u64, vma->display_alignment, alignment);
-
- i915_gem_object_flush_if_display(obj);
-
- i915_vma_get(vma);
-err:
- atomic_dec(_priv->gpu_error.pending_fb_pin);
-
- return vma;
-}
-
-struct i915_vma *
-intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
- bool phys_cursor,
- const struct i915_ggtt_view *view,
- bool uses_fence,
- unsigned long *out_flags)
-{
- struct drm_device *dev = fb->dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
- struct drm_i915_gem_object *obj = intel_fb_obj(fb);
- intel_wakeref_t wakeref;
- struct i915_gem_ww_ctx ww;
- struct i915_vma *vma;
- unsigned int pinctl;
- u32 alignment;
- int ret;
-
- if (drm_WARN_ON(dev, !i915_gem_object_is_framebuffer(obj)))
- return ERR_PTR(-EINVAL);
-
- if (phys_cursor)
- alignment = intel_cursor_alignment(dev_priv);
-
[Intel-gfx] [PATCH 4/8] drm/i915/display: refactor initial plane config to a separate file
From: Dave Airlie
This moves this functionality out of intel_display.c to separate
self-contained file.
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/display/intel_display.c | 279 +
drivers/gpu/drm/i915/display/intel_display.h | 2 +
.../drm/i915/display/intel_plane_initial.c| 283 ++
.../drm/i915/display/intel_plane_initial.h| 13 +
5 files changed, 302 insertions(+), 276 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_plane_initial.c
create mode 100644 drivers/gpu/drm/i915/display/intel_plane_initial.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index c36c8a4f0716..5d9794d80bc2 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -225,6 +225,7 @@ i915-y += \
display/intel_hotplug.o \
display/intel_lpe_audio.o \
display/intel_overlay.o \
+ display/intel_plane_initial.o \
display/intel_psr.o \
display/intel_quirks.o \
display/intel_sprite.o \
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 39a7b24135c9..b0684537f987 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -95,6 +95,7 @@
#include "intel_overlay.h"
#include "intel_panel.h"
#include "intel_pipe_crc.h"
+#include "intel_plane_initial.h"
#include "intel_pm.h"
#include "intel_pps.h"
#include "intel_psr.h"
@@ -1238,123 +1239,6 @@ u32 intel_plane_fb_max_stride(struct drm_i915_private
*dev_priv,
DRM_MODE_ROTATE_0);
}
-static struct i915_vma *
-initial_plane_vma(struct drm_i915_private *i915,
- struct intel_initial_plane_config *plane_config)
-{
- struct drm_i915_gem_object *obj;
- struct i915_vma *vma;
- u32 base, size;
-
- if (plane_config->size == 0)
- return NULL;
-
- base = round_down(plane_config->base,
- I915_GTT_MIN_ALIGNMENT);
- size = round_up(plane_config->base + plane_config->size,
- I915_GTT_MIN_ALIGNMENT);
- size -= base;
-
- /*
-* If the FB is too big, just don't use it since fbdev is not very
-* important and we should probably use that space with FBC or other
-* features.
-*/
- if (IS_ENABLED(CONFIG_FRAMEBUFFER_CONSOLE) &&
- size * 2 > i915->stolen_usable_size)
- return NULL;
-
- obj = i915_gem_object_create_stolen_for_preallocated(i915, base, size);
- if (IS_ERR(obj))
- return NULL;
-
- /*
-* Mark it WT ahead of time to avoid changing the
-* cache_level during fbdev initialization. The
-* unbind there would get stuck waiting for rcu.
-*/
- i915_gem_object_set_cache_coherency(obj, HAS_WT(i915) ?
- I915_CACHE_WT : I915_CACHE_NONE);
-
- switch (plane_config->tiling) {
- case I915_TILING_NONE:
- break;
- case I915_TILING_X:
- case I915_TILING_Y:
- obj->tiling_and_stride =
- plane_config->fb->base.pitches[0] |
- plane_config->tiling;
- break;
- default:
- MISSING_CASE(plane_config->tiling);
- goto err_obj;
- }
-
- vma = i915_vma_instance(obj, >ggtt.vm, NULL);
- if (IS_ERR(vma))
- goto err_obj;
-
- if (i915_ggtt_pin(vma, NULL, 0, PIN_MAPPABLE | PIN_OFFSET_FIXED | base))
- goto err_obj;
-
- if (i915_gem_object_is_tiled(obj) &&
- !i915_vma_is_map_and_fenceable(vma))
- goto err_obj;
-
- return vma;
-
-err_obj:
- i915_gem_object_put(obj);
- return NULL;
-}
-
-static bool
-intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
- struct intel_initial_plane_config *plane_config)
-{
- struct drm_device *dev = crtc->base.dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
- struct drm_mode_fb_cmd2 mode_cmd = { 0 };
- struct drm_framebuffer *fb = _config->fb->base;
- struct i915_vma *vma;
-
- switch (fb->modifier) {
- case DRM_FORMAT_MOD_LINEAR:
- case I915_FORMAT_MOD_X_TILED:
- case I915_FORMAT_MOD_Y_TILED:
- break;
- default:
- drm_dbg(_priv->drm,
- "Unsupported modifier for initial FB: 0x%llx\n",
- fb->modifier);
- return false;
- }
-
- vma = initial_plane_vma(dev_priv, plane_config);
- if (!vma)
- return false;
-
- mode_cmd.pixel_format = fb->format->format;
- mode_cmd.width = fb->width;
- mode_cmd.height = fb->height;
- mode_cmd.pitches[0] = fb->pitches[0];
-
[Intel-gfx] [PATCH 3/8] drm/i915/display: refactor out initial plane config for crtcs
From: Dave Airlie
This just pulls this out into a function so it can be moved to
another file easier.
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_display.c | 44 +++-
1 file changed, 25 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 5254180934bb..39a7b24135c9 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -11460,6 +11460,30 @@ int intel_modeset_init_noirq(struct drm_i915_private
*i915)
return ret;
}
+static void
+intel_crtc_initial_plane_config(struct intel_crtc *crtc)
+{
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ struct intel_initial_plane_config plane_config = {};
+
+ /*
+* Note that reserving the BIOS fb up front prevents us
+* from stuffing other stolen allocations like the ring
+* on top. This prevents some ugliness at boot time, and
+* can even allow for smooth boot transitions if the BIOS
+* fb is large enough for the active pipe configuration.
+*/
+ dev_priv->display->get_initial_plane_config(crtc, _config);
+
+ /*
+* If the fb is shared between multiple heads, we'll
+* just get the first one.
+*/
+ intel_find_initial_plane_obj(crtc, _config);
+
+ plane_config_fini(_config);
+}
+
/* part #2: call after irq install, but before gem init */
int intel_modeset_init_nogem(struct drm_i915_private *i915)
{
@@ -11521,27 +11545,9 @@ int intel_modeset_init_nogem(struct drm_i915_private
*i915)
drm_modeset_unlock_all(dev);
for_each_intel_crtc(dev, crtc) {
- struct intel_initial_plane_config plane_config = {};
-
if (!to_intel_crtc_state(crtc->base.state)->uapi.active)
continue;
-
- /*
-* Note that reserving the BIOS fb up front prevents us
-* from stuffing other stolen allocations like the ring
-* on top. This prevents some ugliness at boot time, and
-* can even allow for smooth boot transitions if the BIOS
-* fb is large enough for the active pipe configuration.
-*/
- i915->display->get_initial_plane_config(crtc, _config);
-
- /*
-* If the fb is shared between multiple heads, we'll
-* just get the first one.
-*/
- intel_find_initial_plane_obj(crtc, _config);
-
- plane_config_fini(_config);
+ intel_crtc_initial_plane_config(crtc);
}
/*
--
2.25.4
[Intel-gfx] [PATCH 1/8] drm/i915/display: move plane prepare/cleanup to intel_atomic_plane.c
From: Dave Airlie
Start to refactor more stuff out of intel_display.c. These fit
better in this file.
This moves the rps boosting code as well as this is the only user of it.
Signed-off-by: Dave Airlie
---
.../gpu/drm/i915/display/intel_atomic_plane.c | 208 ++
drivers/gpu/drm/i915/display/intel_display.c | 208 --
drivers/gpu/drm/i915/display/intel_display.h | 4 -
3 files changed, 208 insertions(+), 212 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index 47234d898549..53ee56453270 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -41,6 +41,7 @@
#include "intel_display_types.h"
#include "intel_pm.h"
#include "intel_sprite.h"
+#include "gt/intel_rps.h"
static void intel_plane_state_reset(struct intel_plane_state *plane_state,
struct intel_plane *plane)
@@ -601,6 +602,213 @@ int intel_atomic_plane_check_clipping(struct
intel_plane_state *plane_state,
return 0;
}
+struct wait_rps_boost {
+ struct wait_queue_entry wait;
+
+ struct drm_crtc *crtc;
+ struct i915_request *request;
+};
+
+static int do_rps_boost(struct wait_queue_entry *_wait,
+ unsigned mode, int sync, void *key)
+{
+ struct wait_rps_boost *wait = container_of(_wait, typeof(*wait), wait);
+ struct i915_request *rq = wait->request;
+
+ /*
+* If we missed the vblank, but the request is already running it
+* is reasonable to assume that it will complete before the next
+* vblank without our intervention, so leave RPS alone.
+*/
+ if (!i915_request_started(rq))
+ intel_rps_boost(rq);
+ i915_request_put(rq);
+
+ drm_crtc_vblank_put(wait->crtc);
+
+ list_del(>wait.entry);
+ kfree(wait);
+ return 1;
+}
+
+static void add_rps_boost_after_vblank(struct drm_crtc *crtc,
+ struct dma_fence *fence)
+{
+ struct wait_rps_boost *wait;
+
+ if (!dma_fence_is_i915(fence))
+ return;
+
+ if (DISPLAY_VER(to_i915(crtc->dev)) < 6)
+ return;
+
+ if (drm_crtc_vblank_get(crtc))
+ return;
+
+ wait = kmalloc(sizeof(*wait), GFP_KERNEL);
+ if (!wait) {
+ drm_crtc_vblank_put(crtc);
+ return;
+ }
+
+ wait->request = to_request(dma_fence_get(fence));
+ wait->crtc = crtc;
+
+ wait->wait.func = do_rps_boost;
+ wait->wait.flags = 0;
+
+ add_wait_queue(drm_crtc_vblank_waitqueue(crtc), >wait);
+}
+
+/**
+ * intel_prepare_plane_fb - Prepare fb for usage on plane
+ * @_plane: drm plane to prepare for
+ * @_new_plane_state: the plane state being prepared
+ *
+ * Prepares a framebuffer for usage on a display plane. Generally this
+ * involves pinning the underlying object and updating the frontbuffer tracking
+ * bits. Some older platforms need special physical address handling for
+ * cursor planes.
+ *
+ * Returns 0 on success, negative error code on failure.
+ */
+static int
+intel_prepare_plane_fb(struct drm_plane *_plane,
+ struct drm_plane_state *_new_plane_state)
+{
+ struct i915_sched_attr attr = { .priority = I915_PRIORITY_DISPLAY };
+ struct intel_plane *plane = to_intel_plane(_plane);
+ struct intel_plane_state *new_plane_state =
+ to_intel_plane_state(_new_plane_state);
+ struct intel_atomic_state *state =
+ to_intel_atomic_state(new_plane_state->uapi.state);
+ struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
+ const struct intel_plane_state *old_plane_state =
+ intel_atomic_get_old_plane_state(state, plane);
+ struct drm_i915_gem_object *obj = intel_fb_obj(new_plane_state->hw.fb);
+ struct drm_i915_gem_object *old_obj =
intel_fb_obj(old_plane_state->hw.fb);
+ int ret;
+
+ if (old_obj) {
+ const struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state,
+
to_intel_crtc(old_plane_state->hw.crtc));
+
+ /* Big Hammer, we also need to ensure that any pending
+* MI_WAIT_FOR_EVENT inside a user batch buffer on the
+* current scanout is retired before unpinning the old
+* framebuffer. Note that we rely on userspace rendering
+* into the buffer attached to the pipe they are waiting
+* on. If not, userspace generates a GPU hang with IPEHR
+* point to the MI_WAIT_FOR_EVENT.
+*
+* This should only fail upon a hung GPU, in which case we
+* can safely continue.
+*/
+ if
[Intel-gfx] [PATCH 2/8] drm/i915/display: let intel_plane_uses_fence be used from other places.
From: Dave Airlie
I want to refactor some stuff using this so make it shared.
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
drivers/gpu/drm/i915/display/intel_display.h | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index d1fa17929b1f..5254180934bb 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -851,7 +851,7 @@ unsigned int intel_remapped_info_size(const struct
intel_remapped_info *rem_info
return size;
}
-static bool intel_plane_uses_fence(const struct intel_plane_state *plane_state)
+bool intel_plane_uses_fence(const struct intel_plane_state *plane_state)
{
struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
diff --git a/drivers/gpu/drm/i915/display/intel_display.h
b/drivers/gpu/drm/i915/display/intel_display.h
index a08903bb7647..d655d996d465 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -615,6 +615,7 @@ void ilk_pfit_disable(const struct intel_crtc_state
*old_crtc_state);
int bdw_get_pipemisc_bpp(struct intel_crtc *crtc);
unsigned int intel_plane_fence_y_offset(const struct intel_plane_state
*plane_state);
+bool intel_plane_uses_fence(const struct intel_plane_state *plane_state);
bool
intel_format_info_is_yuv_semiplanar(const struct drm_format_info *info,
u64 modifier);
--
2.25.4
[Intel-gfx] [RFC PATCH 0/8] drm/i915/display: refactor plane config + pin out (v2)
This is another series in the refactor intel_display.c into more manageable places. This moves the initial plane config and all the fb pin/unpin code out. It also refactors both a little to make the interfaces cleaner. v2: just address the minor comments from Jani. Jani, I think Ville doesn't mind the resulting layout. Dave.
Re: [Intel-gfx] [RFC PATCH 0/8] drm/i915/display: refactor plane config + pin out
On Thu, 7 Oct 2021 at 21:09, Ville Syrjälä wrote: > > On Thu, Oct 07, 2021 at 01:52:42PM +0300, Jani Nikula wrote: > > On Thu, 07 Oct 2021, Dave Airlie wrote: > > > This is another series in the refactor intel_display.c into more > > > manageable > > > places. > > > > > > This moves the initial plane config and all the fb pin/unpin code out. > > > > > > It also refactors both a little to make the interfaces cleaner. > > > > I had a few nitpicks I commented on. Overall this looks good to me, but > > I'd like Ville's input on the code movement at the high level, are the > > split and files sane etc. I can do the detailed review after that. > > Some of it feels a bit ad-hoc, but I don't really have a better > idea for splitting some of these right now. So might as well go > with this I guess. cscope will find the stuff for me in the end, > at least after I remember to have it reindex. My main goal was separation of things that interface with gem into separate files for now. I'd like to formalise that interface a bit more if we can, it might not bear fruit but I think it would be independently useful cleanup anyways. Dave.
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/selftests: Skip hangcheck selftest on DG1
== Series Details == Series: drm/i915/selftests: Skip hangcheck selftest on DG1 URL : https://patchwork.freedesktop.org/series/95693/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10719_full -> Patchwork_21312_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_21312_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_21312_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_21312_full: ### IGT changes ### Possible regressions * igt@kms_cursor_edge_walk@pipe-c-128x128-left-edge: - shard-tglb: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10719/shard-tglb1/igt@kms_cursor_edge_w...@pipe-c-128x128-left-edge.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21312/shard-tglb8/igt@kms_cursor_edge_w...@pipe-c-128x128-left-edge.html * igt@kms_flip_tiling@flip-changes-tiling-yf: - shard-tglb: NOTRUN -> [SKIP][3] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21312/shard-tglb3/igt@kms_flip_til...@flip-changes-tiling-yf.html Known issues Here are the changes found in Patchwork_21312_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_create@create-massive: - shard-snb: NOTRUN -> [DMESG-WARN][4] ([i915#3002]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21312/shard-snb5/igt@gem_cre...@create-massive.html - shard-apl: NOTRUN -> [DMESG-WARN][5] ([i915#3002]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21312/shard-apl2/igt@gem_cre...@create-massive.html * igt@gem_ctx_persistence@legacy-engines-queued: - shard-snb: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#1099]) +4 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21312/shard-snb2/igt@gem_ctx_persiste...@legacy-engines-queued.html * igt@gem_eio@unwedge-stress: - shard-snb: NOTRUN -> [FAIL][7] ([i915#3354]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21312/shard-snb5/igt@gem_...@unwedge-stress.html * igt@gem_exec_fair@basic-none-rrul@rcs0: - shard-glk: [PASS][8] -> [FAIL][9] ([i915#2842]) +2 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10719/shard-glk7/igt@gem_exec_fair@basic-none-r...@rcs0.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21312/shard-glk4/igt@gem_exec_fair@basic-none-r...@rcs0.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-tglb: NOTRUN -> [FAIL][10] ([i915#2842]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21312/shard-tglb3/igt@gem_exec_fair@basic-pace-sh...@rcs0.html * igt@gem_exec_fair@basic-pace@vcs0: - shard-tglb: [PASS][11] -> [FAIL][12] ([i915#2842]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10719/shard-tglb6/igt@gem_exec_fair@basic-p...@vcs0.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21312/shard-tglb1/igt@gem_exec_fair@basic-p...@vcs0.html * igt@gem_exec_fair@basic-pace@vcs1: - shard-kbl: [PASS][13] -> [FAIL][14] ([i915#2842]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10719/shard-kbl7/igt@gem_exec_fair@basic-p...@vcs1.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21312/shard-kbl1/igt@gem_exec_fair@basic-p...@vcs1.html * igt@gem_pxp@reject-modify-context-protection-off-2: - shard-tglb: NOTRUN -> [SKIP][15] ([i915#4270]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21312/shard-tglb3/igt@gem_...@reject-modify-context-protection-off-2.html * igt@gem_userptr_blits@coherency-sync: - shard-tglb: NOTRUN -> [SKIP][16] ([fdo#110542]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21312/shard-tglb3/igt@gem_userptr_bl...@coherency-sync.html * igt@gem_userptr_blits@vma-merge: - shard-kbl: NOTRUN -> [FAIL][17] ([i915#3318]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21312/shard-kbl2/igt@gem_userptr_bl...@vma-merge.html * igt@gen7_exec_parse@oacontrol-tracking: - shard-tglb: NOTRUN -> [SKIP][18] ([fdo#109289]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21312/shard-tglb3/igt@gen7_exec_pa...@oacontrol-tracking.html * igt@i915_pm_dc@dc6-psr: - shard-iclb: [PASS][19] -> [FAIL][20] ([i915#454]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10719/shard-iclb6/igt@i915_pm...@dc6-psr.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21312/shard-iclb3/igt@i915_pm...@dc6-psr.html *
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/dp, drm/i915: Finish basic PWM support for VESA backlight helpers (rev9)
== Series Details == Series: drm/dp, drm/i915: Finish basic PWM support for VESA backlight helpers (rev9) URL : https://patchwork.freedesktop.org/series/95127/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10719_full -> Patchwork_21310_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_21310_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_21310_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_21310_full: ### IGT changes ### Possible regressions * igt@kms_flip_tiling@flip-changes-tiling-yf: - shard-tglb: NOTRUN -> [SKIP][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21310/shard-tglb8/igt@kms_flip_til...@flip-changes-tiling-yf.html * igt@kms_frontbuffer_tracking@fbc-suspend: - shard-kbl: [PASS][2] -> [INCOMPLETE][3] [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10719/shard-kbl1/igt@kms_frontbuffer_track...@fbc-suspend.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21310/shard-kbl2/igt@kms_frontbuffer_track...@fbc-suspend.html Known issues Here are the changes found in Patchwork_21310_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_create@create-massive: - shard-snb: NOTRUN -> [DMESG-WARN][4] ([i915#3002]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21310/shard-snb2/igt@gem_cre...@create-massive.html * igt@gem_ctx_isolation@preservation-s3@bcs0: - shard-apl: NOTRUN -> [DMESG-WARN][5] ([i915#180]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21310/shard-apl6/igt@gem_ctx_isolation@preservation...@bcs0.html * igt@gem_ctx_isolation@preservation-s3@vcs0: - shard-kbl: [PASS][6] -> [DMESG-WARN][7] ([i915#180]) +7 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10719/shard-kbl2/igt@gem_ctx_isolation@preservation...@vcs0.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21310/shard-kbl4/igt@gem_ctx_isolation@preservation...@vcs0.html * igt@gem_ctx_param@set-priority-not-supported: - shard-iclb: NOTRUN -> [SKIP][8] ([fdo#109314]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21310/shard-iclb1/igt@gem_ctx_pa...@set-priority-not-supported.html * igt@gem_ctx_persistence@legacy-engines-queued: - shard-snb: NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#1099]) +4 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21310/shard-snb6/igt@gem_ctx_persiste...@legacy-engines-queued.html * igt@gem_eio@unwedge-stress: - shard-snb: NOTRUN -> [FAIL][10] ([i915#3354]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21310/shard-snb2/igt@gem_...@unwedge-stress.html * igt@gem_exec_fair@basic-none-rrul@rcs0: - shard-glk: [PASS][11] -> [FAIL][12] ([i915#2842]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10719/shard-glk7/igt@gem_exec_fair@basic-none-r...@rcs0.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21310/shard-glk7/igt@gem_exec_fair@basic-none-r...@rcs0.html * igt@gem_exec_fair@basic-none-share@rcs0: - shard-iclb: [PASS][13] -> [FAIL][14] ([i915#2842]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10719/shard-iclb5/igt@gem_exec_fair@basic-none-sh...@rcs0.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21310/shard-iclb8/igt@gem_exec_fair@basic-none-sh...@rcs0.html * igt@gem_exec_fair@basic-none@vecs0: - shard-kbl: [PASS][15] -> [FAIL][16] ([i915#2842]) +3 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10719/shard-kbl6/igt@gem_exec_fair@basic-n...@vecs0.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21310/shard-kbl2/igt@gem_exec_fair@basic-n...@vecs0.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-tglb: NOTRUN -> [FAIL][17] ([i915#2842]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21310/shard-tglb8/igt@gem_exec_fair@basic-pace-sh...@rcs0.html * igt@gem_exec_fair@basic-pace@vcs1: - shard-kbl: [PASS][18] -> [SKIP][19] ([fdo#109271]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10719/shard-kbl7/igt@gem_exec_fair@basic-p...@vcs1.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21310/shard-kbl1/igt@gem_exec_fair@basic-p...@vcs1.html - shard-tglb: [PASS][20] -> [FAIL][21] ([i915#2842]) +1 similar issue [20]:
[Intel-gfx] linux-next: build failure after merge of the drm-misc tree
Hi all,
After merging the drm-misc tree, today's linux-next build (x86_64
allmodconfig) failed like this:
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c: In function
'gp100_vmm_fault_cancel':
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c:491:6: error: unused
variable 'inst' [-Werror=unused-variable]
491 | u32 inst, aper;
| ^~~~
cc1: all warnings being treated as errors
Caused by commit
404046cf4805 ("drm/nouveau/mmu/gp100-: drop unneeded assignment in the if
condition.")
I have used the drm-misc tree from next-20211011 for today.
--
Cheers,
Stephen Rothwell
pgp3qvYxBDGsl.pgp
Description: OpenPGP digital signature
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftests: Allow engine reset failure to do a GT reset in hangcheck selftest
== Series Details ==
Series: drm/i915/selftests: Allow engine reset failure to do a GT reset in
hangcheck selftest
URL : https://patchwork.freedesktop.org/series/95702/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10719 -> Patchwork_21313
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21313/index.html
Known issues
Here are the changes found in Patchwork_21313 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live@hangcheck:
- fi-snb-2600:[PASS][1] -> [INCOMPLETE][2] ([i915#3921])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10719/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21313/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
Possible fixes
* igt@i915_selftest@live@gt_heartbeat:
- fi-bdw-5557u: [DMESG-FAIL][3] ([i915#541]) -> [PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10719/fi-bdw-5557u/igt@i915_selftest@live@gt_heartbeat.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21313/fi-bdw-5557u/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@hangcheck:
- {fi-hsw-gt1}: [DMESG-WARN][5] ([i915#3303]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10719/fi-hsw-gt1/igt@i915_selftest@l...@hangcheck.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21313/fi-hsw-gt1/igt@i915_selftest@l...@hangcheck.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
[i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
[i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541
Participating hosts (38 -> 34)
--
Missing(4): fi-bsw-cyan fi-elk-e7500 fi-kbl-guc fi-bsw-n3050
Build changes
-
* Linux: CI_DRM_10719 -> Patchwork_21313
CI-20190529: 20190529
CI_DRM_10719: b138938ad4071c045a865977718019951186e322 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6242: 721fd85ee95225ed5df322f7182bdfa9b86a3e68 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_21313: bad5ebd3f38295f5c7848973d023033c59390e4c @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
bad5ebd3f382 drm/i915/selftests: Allow engine reset failure to do a GT reset in
hangcheck selftest
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21313/index.html
[Intel-gfx] [PATCH] drm/i915/selftests: Allow engine reset failure to do a GT reset in hangcheck selftest
The hangcheck selftest blocks per engine resets by setting magic bits in
the reset flags. This is incorrect for GuC submission because if the GuC
fails to reset an engine we would like to do a full GT reset. Do no set
these magic bits when using GuC submission.
Side note this lockless algorithm with magic bits to block resets really
should be ripped out.
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
index 7e2d99dd012d..90a03c60c80c 100644
--- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
+++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
@@ -734,7 +734,8 @@ static int __igt_reset_engine(struct intel_gt *gt, bool
active)
reset_engine_count = i915_reset_engine_count(global, engine);
st_engine_heartbeat_disable(engine);
- set_bit(I915_RESET_ENGINE + id, >reset.flags);
+ if (!using_guc)
+ set_bit(I915_RESET_ENGINE + id, >reset.flags);
count = 0;
do {
struct i915_request *rq = NULL;
@@ -824,7 +825,8 @@ static int __igt_reset_engine(struct intel_gt *gt, bool
active)
if (err)
break;
} while (time_before(jiffies, end_time));
- clear_bit(I915_RESET_ENGINE + id, >reset.flags);
+ if (!using_guc)
+ clear_bit(I915_RESET_ENGINE + id, >reset.flags);
st_engine_heartbeat_enable(engine);
pr_info("%s: Completed %lu %s resets\n",
engine->name, count, active ? "active" : "idle");
@@ -1042,7 +1044,8 @@ static int __igt_reset_engines(struct intel_gt *gt,
yield(); /* start all threads before we begin */
st_engine_heartbeat_disable_no_pm(engine);
- set_bit(I915_RESET_ENGINE + id, >reset.flags);
+ if (!using_guc)
+ set_bit(I915_RESET_ENGINE + id, >reset.flags);
do {
struct i915_request *rq = NULL;
struct intel_selftest_saved_policy saved;
@@ -1165,7 +1168,8 @@ static int __igt_reset_engines(struct intel_gt *gt,
if (err)
break;
} while (time_before(jiffies, end_time));
- clear_bit(I915_RESET_ENGINE + id, >reset.flags);
+ if (!using_guc)
+ clear_bit(I915_RESET_ENGINE + id, >reset.flags);
st_engine_heartbeat_enable_no_pm(engine);
pr_info("i915_reset_engine(%s:%s): %lu resets\n",
--
2.32.0
[Intel-gfx] ✗ Fi.CI.IGT: failure for Fixup header includes (rev3)
== Series Details == Series: Fixup header includes (rev3) URL : https://patchwork.freedesktop.org/series/95587/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10717_full -> Patchwork_21309_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_21309_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_21309_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_21309_full: ### CI changes ### Possible regressions * boot: - shard-skl: ([PASS][1], [PASS][2], [PASS][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23]) -> ([PASS][24], [PASS][25], [PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], [FAIL][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10717/shard-skl9/boot.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10717/shard-skl9/boot.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10717/shard-skl9/boot.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10717/shard-skl8/boot.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10717/shard-skl8/boot.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10717/shard-skl7/boot.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10717/shard-skl7/boot.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10717/shard-skl5/boot.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10717/shard-skl5/boot.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10717/shard-skl5/boot.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10717/shard-skl4/boot.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10717/shard-skl4/boot.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10717/shard-skl4/boot.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10717/shard-skl3/boot.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10717/shard-skl3/boot.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10717/shard-skl3/boot.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10717/shard-skl3/boot.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10717/shard-skl2/boot.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10717/shard-skl2/boot.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10717/shard-skl2/boot.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10717/shard-skl1/boot.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10717/shard-skl1/boot.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10717/shard-skl1/boot.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21309/shard-skl1/boot.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21309/shard-skl1/boot.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21309/shard-skl1/boot.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21309/shard-skl2/boot.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21309/shard-skl2/boot.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21309/shard-skl2/boot.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21309/shard-skl3/boot.html [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21309/shard-skl3/boot.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21309/shard-skl3/boot.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21309/shard-skl4/boot.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21309/shard-skl4/boot.html [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21309/shard-skl4/boot.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21309/shard-skl5/boot.html [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21309/shard-skl5/boot.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21309/shard-skl5/boot.html [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21309/shard-skl7/boot.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21309/shard-skl7/boot.html [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21309/shard-skl7/boot.html [42]:
Re: [Intel-gfx] [PATCH 20/26] drm/i915/guc: Implement no mid batch preemption for multi-lrc
On 10/4/2021 15:06, Matthew Brost wrote:
For some users of multi-lrc, e.g. split frame, it isn't safe to preempt
mid BB. To safely enable preemption at the BB boundary, a handshake
between to parent and child is needed. This is implemented via custom
between to parent -> between parent
emit_bb_start & emit_fini_breadcrumb functions and enabled via by
via by -> by
I'm also not seeing any mention of the forced re-group behavioural
change in either the comments or commit description.
default if a context is configured by set parallel extension.
v2:
(John Harrison)
- Fix a few comments wording
- Add struture for parent page layout
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/intel_context.c | 2 +-
drivers/gpu/drm/i915/gt/intel_context_types.h | 2 +
drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 2 +-
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 330 +-
4 files changed, 324 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_context.c
b/drivers/gpu/drm/i915/gt/intel_context.c
index 3b340eb59ada..ee84259959d0 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.c
+++ b/drivers/gpu/drm/i915/gt/intel_context.c
@@ -569,7 +569,7 @@ void intel_context_bind_parent_child(struct intel_context
*parent,
GEM_BUG_ON(intel_context_is_child(child));
GEM_BUG_ON(intel_context_is_parent(child));
- parent->parallel.number_children++;
+ parent->parallel.child_index = parent->parallel.number_children++;
list_add_tail(>parallel.child_link,
>parallel.child_list);
child->parallel.parent = parent;
diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h
b/drivers/gpu/drm/i915/gt/intel_context_types.h
index 1d880303a7e4..95a5b94b4ece 100644
--- a/drivers/gpu/drm/i915/gt/intel_context_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_context_types.h
@@ -250,6 +250,8 @@ struct intel_context {
struct i915_request *last_rq;
/** @number_children: number of children if parent */
u8 number_children;
+ /** @child_index: index into child_list if child */
+ u8 child_index;
/** @guc: GuC specific members for parallel submission */
struct {
/** @wqi_head: head pointer in work queue */
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
index a00eeddc1449..663950d3badc 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
@@ -181,7 +181,7 @@ struct guc_process_desc {
u32 wq_status;
u32 engine_presence;
u32 priority;
- u32 reserved[30];
+ u32 reserved[36];
Not seeing the promised explanation of this bug fix.
} __packed;
#define CONTEXT_REGISTRATION_FLAG_KMD BIT(0)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 12ee8ca76249..f28e36aa77c2 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -11,6 +11,7 @@
#include "gt/intel_context.h"
#include "gt/intel_engine_pm.h"
#include "gt/intel_engine_heartbeat.h"
+#include "gt/intel_gpu_commands.h"
#include "gt/intel_gt.h"
#include "gt/intel_gt_irq.h"
#include "gt/intel_gt_pm.h"
@@ -368,10 +369,16 @@ static inline struct i915_priolist *to_priolist(struct
rb_node *rb)
/*
* When using multi-lrc submission an extra page in the context state is
- * reserved for the process descriptor and work queue.
+ * reserved for the process descriptor, work queue, and handshake between the
+ * parent + childlren contexts to insert safe preemption points between each
set
+ * of BBs.
*
* The layout of this page is below:
* 0 guc_process_desc
+ * + sizeof(struct guc_process_desc) child go
+ * + CACHELINE_BYTES child join[0]
+ * ...
+ * + CACHELINE_BYTES child join[n - 1]
* ...unused
* PAGE_SIZE / 2 work queue start
* ...work queue
@@ -379,7 +386,25 @@ static inline struct i915_priolist *to_priolist(struct
rb_node *rb)
*/
#define WQ_SIZE (PAGE_SIZE / 2)
#define WQ_OFFSET (PAGE_SIZE - WQ_SIZE)
-static u32 __get_process_desc_offset(struct intel_context *ce)
+
+struct parent_page {
+ struct guc_process_desc pdesc;
+
+ u32 child_go_memory;
+ u8 unused0[CACHELINE_BYTES - sizeof(u32)];
+
+ struct {
+ u32 child_join_memory;
+ u8 unused1[CACHELINE_BYTES - sizeof(u32)];
+ } join[MAX_ENGINE_INSTANCE + 1];
Could have a common structure for these. Call the u32 'semaphore_memory'
or something then just
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftests: Skip hangcheck selftest on DG1
== Series Details ==
Series: drm/i915/selftests: Skip hangcheck selftest on DG1
URL : https://patchwork.freedesktop.org/series/95693/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10719 -> Patchwork_21312
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21312/index.html
Known issues
Here are the changes found in Patchwork_21312 that come from known issues:
### IGT changes ###
Issues hit
* igt@kms_frontbuffer_tracking@basic:
- fi-cml-u2: [PASS][1] -> [DMESG-WARN][2] ([i915#4269])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10719/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21312/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html
Possible fixes
* igt@i915_selftest@live@gt_heartbeat:
- fi-bdw-5557u: [DMESG-FAIL][3] ([i915#541]) -> [PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10719/fi-bdw-5557u/igt@i915_selftest@live@gt_heartbeat.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21312/fi-bdw-5557u/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@hangcheck:
- {fi-hsw-gt1}: [DMESG-WARN][5] ([i915#3303]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10719/fi-hsw-gt1/igt@i915_selftest@l...@hangcheck.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21312/fi-hsw-gt1/igt@i915_selftest@l...@hangcheck.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#2373]: https://gitlab.freedesktop.org/drm/intel/issues/2373
[i915#2966]: https://gitlab.freedesktop.org/drm/intel/issues/2966
[i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
[i915#4269]: https://gitlab.freedesktop.org/drm/intel/issues/4269
[i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541
[i915#750]: https://gitlab.freedesktop.org/drm/intel/issues/750
Participating hosts (38 -> 34)
--
Missing(4): fi-bsw-cyan fi-elk-e7500 fi-kbl-guc fi-bsw-n3050
Build changes
-
* Linux: CI_DRM_10719 -> Patchwork_21312
CI-20190529: 20190529
CI_DRM_10719: b138938ad4071c045a865977718019951186e322 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6242: 721fd85ee95225ed5df322f7182bdfa9b86a3e68 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_21312: 5c5355acdfbda3879fe610428c1f74d810eff552 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
5c5355acdfbd drm/i915/selftests: Skip hangcheck selftest on DG1
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21312/index.html
[Intel-gfx] [PATCH 2/4] drm/ttm: do not set NULL to debugfs dentry
For debugfs directory, it is recommended to save the result
and pass over to next debugfs API for creating debugfs
files/directories. Error conditions are handled by debugfs APIs.
CC: Christian Koenig
CC: Huang Rui
CC: David Airlie
CC: Daniel Vetter
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/ttm/ttm_device.c | 6 +-
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/ttm/ttm_device.c b/drivers/gpu/drm/ttm/ttm_device.c
index be24bb6cefd0..225ae6b0b4c2 100644
--- a/drivers/gpu/drm/ttm/ttm_device.c
+++ b/drivers/gpu/drm/ttm/ttm_device.c
@@ -77,9 +77,6 @@ static int ttm_global_init(void)
si_meminfo();
ttm_debugfs_root = debugfs_create_dir("ttm", NULL);
- if (IS_ERR(ttm_debugfs_root)) {
- ttm_debugfs_root = NULL;
- }
/* Limit the number of pages in the pool to about 50% of the total
* system memory.
@@ -108,8 +105,7 @@ static int ttm_global_init(void)
debugfs_create_atomic_t("buffer_objects", 0444, ttm_debugfs_root,
>bo_count);
out:
- if (ret && ttm_debugfs_root)
- debugfs_remove(ttm_debugfs_root);
+ debugfs_remove(ttm_debugfs_root);
if (ret)
--ttm_glob_use_count;
mutex_unlock(_global_mutex);
--
2.32.0
[Intel-gfx] [PATCH 4/4] vgaswitcheroo: do not check for NULL debugfs dentry
Debugfs APIs returns encoded error on failure so use
debugfs_lookup() instead of checking for NULL.
CC: Lukas Wunner
CC: David Airlie
CC: Daniel Vetter
CC: Maarten Lankhorst
CC: Maxime Ripard
CC: Thomas Zimmermann
Signed-off-by: Nirmoy Das
---
drivers/gpu/vga/vga_switcheroo.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/vga/vga_switcheroo.c b/drivers/gpu/vga/vga_switcheroo.c
index 365e6ddbe90f..a331525f0b32 100644
--- a/drivers/gpu/vga/vga_switcheroo.c
+++ b/drivers/gpu/vga/vga_switcheroo.c
@@ -914,7 +914,7 @@ static void vga_switcheroo_debugfs_fini(struct vgasr_priv
*priv)
static void vga_switcheroo_debugfs_init(struct vgasr_priv *priv)
{
/* already initialised */
- if (priv->debugfs_root)
+ if (debugfs_lookup("vgaswitcheroo", NULL))
return;
priv->debugfs_root = debugfs_create_dir("vgaswitcheroo", NULL);
--
2.32.0
[Intel-gfx] [PATCH 3/4] drm/i915/gt: do not check for NULL debugfs dentry
Do not check for NULL value as drm.primary->debugfs_root
will either contain a valid pointer or an encoded error
instead of NULL.
CC: Jani Nikula
CC: Joonas Lahtinen
CC: Rodrigo Vivi
CC: David Airlie
CC: Daniel Vetter
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/i915/gt/debugfs_gt.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt.c
b/drivers/gpu/drm/i915/gt/debugfs_gt.c
index 591eb60785db..95ca1b3ad320 100644
--- a/drivers/gpu/drm/i915/gt/debugfs_gt.c
+++ b/drivers/gpu/drm/i915/gt/debugfs_gt.c
@@ -16,9 +16,6 @@ void debugfs_gt_register(struct intel_gt *gt)
{
struct dentry *root;
- if (!gt->i915->drm.primary->debugfs_root)
- return;
-
root = debugfs_create_dir("gt", gt->i915->drm.primary->debugfs_root);
if (IS_ERR(root))
return;
--
2.32.0
[Intel-gfx] [PATCH 1/4] dri: do not check for NULL debugfs dentry
Debugfs APIs returns encoded error on failure instead of NULL
and for drm primary/minor debugfs directories, we save the
returned value in the dentry pointer and pass it on to drm
drivers to further create debugfs files/directories. Error
conditions are handled by debugfs APIs, so no need to check
for NULL, as saved dentry pointers will either contain a
valid pointer or an error code.
CC: Maarten Lankhorst
CC: Maxime Ripard
CC: Thomas Zimmermann
CC: David Airlie
CC: Daniel Vetter
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/drm_debugfs.c | 9 -
1 file changed, 9 deletions(-)
diff --git a/drivers/gpu/drm/drm_debugfs.c b/drivers/gpu/drm/drm_debugfs.c
index b0a826489488..0073854a4383 100644
--- a/drivers/gpu/drm/drm_debugfs.c
+++ b/drivers/gpu/drm/drm_debugfs.c
@@ -272,9 +272,6 @@ static void drm_debugfs_remove_all_files(struct drm_minor
*minor)
void drm_debugfs_cleanup(struct drm_minor *minor)
{
- if (!minor->debugfs_root)
- return;
-
drm_debugfs_remove_all_files(minor);
debugfs_remove_recursive(minor->debugfs_root);
@@ -419,9 +416,6 @@ void drm_debugfs_connector_add(struct drm_connector
*connector)
struct drm_minor *minor = connector->dev->primary;
struct dentry *root;
- if (!minor->debugfs_root)
- return;
-
root = debugfs_create_dir(connector->name, minor->debugfs_root);
connector->debugfs_entry = root;
@@ -440,9 +434,6 @@ void drm_debugfs_connector_add(struct drm_connector
*connector)
void drm_debugfs_connector_remove(struct drm_connector *connector)
{
- if (!connector->debugfs_entry)
- return;
-
debugfs_remove_recursive(connector->debugfs_entry);
connector->debugfs_entry = NULL;
--
2.32.0
Re: [Intel-gfx] [PATCH 17/26] drm/i915/guc: Connect UAPI to GuC multi-lrc interface
On Mon, Oct 11, 2021 at 03:09:43PM -0700, John Harrison wrote:
> On 10/4/2021 15:06, Matthew Brost wrote:
> > Introduce 'set parallel submit' extension to connect UAPI to GuC
> > multi-lrc interface. Kernel doc in new uAPI should explain it all.
> >
> > IGT: https://patchwork.freedesktop.org/patch/447008/?series=93071=1
> > media UMD: https://github.com/intel/media-driver/pull/1252
> >
> > v2:
> > (Daniel Vetter)
> >- Add IGT link and placeholder for media UMD link
> > v3:
> > (Kernel test robot)
> >- Fix warning in unpin engines call
> > (John Harrison)
> >- Reword a bunch of the kernel doc
> >
> > Cc: Tvrtko Ursulin
> > Signed-off-by: Matthew Brost
> > ---
> > drivers/gpu/drm/i915/gem/i915_gem_context.c | 221 +-
> > .../gpu/drm/i915/gem/i915_gem_context_types.h | 6 +
> > drivers/gpu/drm/i915/gt/intel_context_types.h | 9 +-
> > drivers/gpu/drm/i915/gt/intel_engine.h| 12 +-
> > drivers/gpu/drm/i915/gt/intel_engine_cs.c | 6 +-
> > .../drm/i915/gt/intel_execlists_submission.c | 6 +-
> > drivers/gpu/drm/i915/gt/selftest_execlists.c | 12 +-
> > .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 114 -
> > include/uapi/drm/i915_drm.h | 131 +++
> > 9 files changed, 489 insertions(+), 28 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> > b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> > index 8c7ea6e56262..6290bc20ccb1 100644
> > --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> > +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> > @@ -522,9 +522,150 @@ set_proto_ctx_engines_bond(struct i915_user_extension
> > __user *base, void *data)
> > return 0;
> > }
> > +static int
> > +set_proto_ctx_engines_parallel_submit(struct i915_user_extension __user
> > *base,
> > + void *data)
> > +{
> > + struct i915_context_engines_parallel_submit __user *ext =
> > + container_of_user(base, typeof(*ext), base);
> > + const struct set_proto_ctx_engines *set = data;
> > + struct drm_i915_private *i915 = set->i915;
> > + u64 flags;
> > + int err = 0, n, i, j;
> > + u16 slot, width, num_siblings;
> > + struct intel_engine_cs **siblings = NULL;
> > + intel_engine_mask_t prev_mask;
> > +
> > + /* Disabling for now */
> > + return -ENODEV;
> > +
> > + /* FIXME: This is NIY for execlists */
> > + if (!(intel_uc_uses_guc_submission(>gt.uc)))
> > + return -ENODEV;
> > +
> > + if (get_user(slot, >engine_index))
> > + return -EFAULT;
> > +
> > + if (get_user(width, >width))
> > + return -EFAULT;
> > +
> > + if (get_user(num_siblings, >num_siblings))
> > + return -EFAULT;
> > +
> > + if (slot >= set->num_engines) {
> > + drm_dbg(>drm, "Invalid placement value, %d >= %d\n",
> > + slot, set->num_engines);
> > + return -EINVAL;
> > + }
> > +
> > + if (set->engines[slot].type != I915_GEM_ENGINE_TYPE_INVALID) {
> > + drm_dbg(>drm,
> > + "Invalid placement[%d], already occupied\n", slot);
> > + return -EINVAL;
> > + }
> > +
> > + if (get_user(flags, >flags))
> > + return -EFAULT;
> > +
> > + if (flags) {
> > + drm_dbg(>drm, "Unknown flags 0x%02llx", flags);
> > + return -EINVAL;
> > + }
> > +
> > + for (n = 0; n < ARRAY_SIZE(ext->mbz64); n++) {
> > + err = check_user_mbz(>mbz64[n]);
> > + if (err)
> > + return err;
> > + }
> > +
> > + if (width < 2) {
> > + drm_dbg(>drm, "Width (%d) < 2\n", width);
> > + return -EINVAL;
> > + }
> > +
> > + if (num_siblings < 1) {
> > + drm_dbg(>drm, "Number siblings (%d) < 1\n",
> > + num_siblings);
> > + return -EINVAL;
> > + }
> > +
> > + siblings = kmalloc_array(num_siblings * width,
> > +sizeof(*siblings),
> > +GFP_KERNEL);
> > + if (!siblings)
> > + return -ENOMEM;
> > +
> > + /* Create contexts / engines */
> > + for (i = 0; i < width; ++i) {
> > + intel_engine_mask_t current_mask = 0;
> > + struct i915_engine_class_instance prev_engine;
> > +
> > + for (j = 0; j < num_siblings; ++j) {
> > + struct i915_engine_class_instance ci;
> > +
> > + n = i * num_siblings + j;
> > + if (copy_from_user(, >engines[n], sizeof(ci))) {
> > + err = -EFAULT;
> > + goto out_err;
> > + }
> > +
> > + siblings[n] =
> > + intel_engine_lookup_user(i915, ci.engine_class,
> > +ci.engine_instance);
> > + if (!siblings[n]) {
> > + drm_dbg(>drm,
> > +
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915/dp: abstract intel_dp_lane_max_vswing_reached()
== Series Details == Series: series starting with [1/2] drm/i915/dp: abstract intel_dp_lane_max_vswing_reached() URL : https://patchwork.freedesktop.org/series/95689/ State : success == Summary == CI Bug Log - changes from CI_DRM_10717_full -> Patchwork_21308_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_21308_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_create@create-massive: - shard-snb: NOTRUN -> [DMESG-WARN][1] ([i915#3002]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21308/shard-snb5/igt@gem_cre...@create-massive.html * igt@gem_ctx_isolation@preservation-s3@vecs0: - shard-kbl: [PASS][2] -> [DMESG-WARN][3] ([i915#180]) +4 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10717/shard-kbl7/igt@gem_ctx_isolation@preservation...@vecs0.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21308/shard-kbl4/igt@gem_ctx_isolation@preservation...@vecs0.html * igt@gem_ctx_persistence@legacy-engines-queued: - shard-snb: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#1099]) +3 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21308/shard-snb7/igt@gem_ctx_persiste...@legacy-engines-queued.html * igt@gem_eio@unwedge-stress: - shard-snb: NOTRUN -> [FAIL][5] ([i915#3354]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21308/shard-snb5/igt@gem_...@unwedge-stress.html * igt@gem_exec_fair@basic-deadline: - shard-apl: NOTRUN -> [FAIL][6] ([i915#2846]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21308/shard-apl3/igt@gem_exec_f...@basic-deadline.html * igt@gem_exec_fair@basic-none-solo@rcs0: - shard-kbl: NOTRUN -> [FAIL][7] ([i915#2842]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21308/shard-kbl3/igt@gem_exec_fair@basic-none-s...@rcs0.html * igt@gem_exec_fair@basic-none@vcs0: - shard-kbl: [PASS][8] -> [FAIL][9] ([i915#2842]) +1 similar issue [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10717/shard-kbl3/igt@gem_exec_fair@basic-n...@vcs0.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21308/shard-kbl1/igt@gem_exec_fair@basic-n...@vcs0.html * igt@gem_exec_fair@basic-pace-solo@rcs0: - shard-tglb: NOTRUN -> [FAIL][10] ([i915#2842]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21308/shard-tglb6/igt@gem_exec_fair@basic-pace-s...@rcs0.html * igt@gem_exec_fair@basic-pace@bcs0: - shard-tglb: [PASS][11] -> [FAIL][12] ([i915#2842]) +2 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10717/shard-tglb1/igt@gem_exec_fair@basic-p...@bcs0.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21308/shard-tglb6/igt@gem_exec_fair@basic-p...@bcs0.html * igt@gem_exec_fair@basic-throttle@rcs0: - shard-glk: [PASS][13] -> [FAIL][14] ([i915#2842]) +2 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10717/shard-glk5/igt@gem_exec_fair@basic-throt...@rcs0.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21308/shard-glk1/igt@gem_exec_fair@basic-throt...@rcs0.html * igt@gem_userptr_blits@set-cache-level: - shard-skl: [PASS][15] -> [DMESG-WARN][16] ([i915#1982]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10717/shard-skl2/igt@gem_userptr_bl...@set-cache-level.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21308/shard-skl4/igt@gem_userptr_bl...@set-cache-level.html * igt@gem_userptr_blits@unsync-unmap-cycles: - shard-tglb: NOTRUN -> [SKIP][17] ([i915#3297]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21308/shard-tglb5/igt@gem_userptr_bl...@unsync-unmap-cycles.html * igt@gem_userptr_blits@vma-merge: - shard-kbl: NOTRUN -> [FAIL][18] ([i915#3318]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21308/shard-kbl6/igt@gem_userptr_bl...@vma-merge.html * igt@gen9_exec_parse@basic-rejected: - shard-tglb: NOTRUN -> [SKIP][19] ([i915#2856]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21308/shard-tglb6/igt@gen9_exec_pa...@basic-rejected.html * igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp: - shard-apl: NOTRUN -> [SKIP][20] ([fdo#109271] / [i915#1937]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21308/shard-apl2/igt@i915_pm_lpsp@kms-l...@kms-lpsp-dp.html * igt@kms_async_flips@crc: - shard-skl: NOTRUN -> [FAIL][21] ([i915#4272]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21308/shard-skl1/igt@kms_async_fl...@crc.html * igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip: - shard-kbl: NOTRUN -> [SKIP][22] ([fdo#109271] /
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/4] dri: do not check for NULL debugfs dentry
== Series Details == Series: series starting with [1/4] dri: do not check for NULL debugfs dentry URL : https://patchwork.freedesktop.org/series/95691/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10719 -> Patchwork_21311 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_21311 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_21311, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21311/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_21311: ### IGT changes ### Possible regressions * igt@core_hotunplug@unbind-rebind: - fi-skl-6700k2: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10719/fi-skl-6700k2/igt@core_hotunp...@unbind-rebind.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21311/fi-skl-6700k2/igt@core_hotunp...@unbind-rebind.html - fi-rkl-guc: [PASS][3] -> [INCOMPLETE][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10719/fi-rkl-guc/igt@core_hotunp...@unbind-rebind.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21311/fi-rkl-guc/igt@core_hotunp...@unbind-rebind.html - fi-elk-e7500: [PASS][5] -> [INCOMPLETE][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10719/fi-elk-e7500/igt@core_hotunp...@unbind-rebind.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21311/fi-elk-e7500/igt@core_hotunp...@unbind-rebind.html - fi-ivb-3770:[PASS][7] -> [INCOMPLETE][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10719/fi-ivb-3770/igt@core_hotunp...@unbind-rebind.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21311/fi-ivb-3770/igt@core_hotunp...@unbind-rebind.html - fi-ilk-650: [PASS][9] -> [INCOMPLETE][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10719/fi-ilk-650/igt@core_hotunp...@unbind-rebind.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21311/fi-ilk-650/igt@core_hotunp...@unbind-rebind.html - fi-bsw-n3050: [PASS][11] -> [INCOMPLETE][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10719/fi-bsw-n3050/igt@core_hotunp...@unbind-rebind.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21311/fi-bsw-n3050/igt@core_hotunp...@unbind-rebind.html - fi-cfl-guc: [PASS][13] -> [INCOMPLETE][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10719/fi-cfl-guc/igt@core_hotunp...@unbind-rebind.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21311/fi-cfl-guc/igt@core_hotunp...@unbind-rebind.html - fi-skl-6600u: [PASS][15] -> [INCOMPLETE][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10719/fi-skl-6600u/igt@core_hotunp...@unbind-rebind.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21311/fi-skl-6600u/igt@core_hotunp...@unbind-rebind.html - fi-kbl-soraka: [PASS][17] -> [INCOMPLETE][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10719/fi-kbl-soraka/igt@core_hotunp...@unbind-rebind.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21311/fi-kbl-soraka/igt@core_hotunp...@unbind-rebind.html - fi-tgl-1115g4: [PASS][19] -> [INCOMPLETE][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10719/fi-tgl-1115g4/igt@core_hotunp...@unbind-rebind.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21311/fi-tgl-1115g4/igt@core_hotunp...@unbind-rebind.html - fi-bxt-dsi: [PASS][21] -> [INCOMPLETE][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10719/fi-bxt-dsi/igt@core_hotunp...@unbind-rebind.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21311/fi-bxt-dsi/igt@core_hotunp...@unbind-rebind.html - fi-kbl-r: [PASS][23] -> [INCOMPLETE][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10719/fi-kbl-r/igt@core_hotunp...@unbind-rebind.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21311/fi-kbl-r/igt@core_hotunp...@unbind-rebind.html - fi-cfl-8700k: [PASS][25] -> [INCOMPLETE][26] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10719/fi-cfl-8700k/igt@core_hotunp...@unbind-rebind.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21311/fi-cfl-8700k/igt@core_hotunp...@unbind-rebind.html - fi-rkl-11600: [PASS][27] -> [INCOMPLETE][28] [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10719/fi-rkl-11600/igt@core_hotunp...@unbind-rebind.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21311/fi-rkl-11600/igt@core_hotunp...@unbind-rebind.html - fi-kbl-7500u:
Re: [Intel-gfx] [PATCH 24/26] drm/i915: Update I915_GEM_BUSY IOCTL to understand composite fences
On 10/4/2021 3:06 PM, Matthew Brost wrote:
Parallel submission create composite fences (dma_fence_array) for excl /
shared slots in objects. The I915_GEM_BUSY IOCTL checks these slots to
determine the busyness of the object. Prior to patch it only check if
the fence in the slot was a i915_request. Update the check to understand
composite fences and correctly report the busyness.
Signed-off-by: Matthew Brost
Reviewed-by: Daniele Ceraolo Spurio
Daniele
---
drivers/gpu/drm/i915/gem/i915_gem_busy.c | 60 +++
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 5 +-
drivers/gpu/drm/i915/i915_request.h | 6 ++
3 files changed, 58 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_busy.c
b/drivers/gpu/drm/i915/gem/i915_gem_busy.c
index 6234e17259c1..b89d173c62eb 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_busy.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_busy.c
@@ -4,6 +4,8 @@
* Copyright © 2014-2016 Intel Corporation
*/
+#include
+
#include "gt/intel_engine.h"
#include "i915_gem_ioctls.h"
@@ -36,7 +38,7 @@ static __always_inline u32 __busy_write_id(u16 id)
}
static __always_inline unsigned int
-__busy_set_if_active(const struct dma_fence *fence, u32 (*flag)(u16 id))
+__busy_set_if_active(struct dma_fence *fence, u32 (*flag)(u16 id))
{
const struct i915_request *rq;
@@ -46,29 +48,63 @@ __busy_set_if_active(const struct dma_fence *fence, u32 (*flag)(u16 id))
* to eventually flush us, but to minimise latency just ask the
* hardware.
*
-* Note we only report on the status of native fences.
+* Note we only report on the status of native fences and we currently
+* have two native fences:
+*
+* 1. A composite fence (dma_fence_array) constructed of i915 requests
+* created during a parallel submission. In this case we deconstruct the
+* composite fence into individual i915 requests and check the status of
+* each request.
+*
+* 2. A single i915 request.
*/
- if (!dma_fence_is_i915(fence))
+ if (dma_fence_is_array(fence)) {
+ struct dma_fence_array *array = to_dma_fence_array(fence);
+ struct dma_fence **child = array->fences;
+ unsigned int nchild = array->num_fences;
+
+ do {
+ struct dma_fence *current_fence = *child++;
+
+ /* Not an i915 fence, can't be busy per above */
+ if (!dma_fence_is_i915(current_fence) ||
+ !test_bit(I915_FENCE_FLAG_COMPOSITE,
+ _fence->flags)) {
+ return 0;
+ }
+
+ rq = to_request(current_fence);
+ if (!i915_request_completed(rq)) {
+ BUILD_BUG_ON(!typecheck(u16,
+
rq->engine->uabi_class));
+ return flag(rq->engine->uabi_class);
+ }
+ } while (--nchild);
+
+ /* All requests in array complete, not busy */
return 0;
+ } else {
+ if (!dma_fence_is_i915(fence))
+ return 0;
- /* opencode to_request() in order to avoid const warnings */
- rq = container_of(fence, const struct i915_request, fence);
- if (i915_request_completed(rq))
- return 0;
+ rq = to_request(fence);
+ if (i915_request_completed(rq))
+ return 0;
- /* Beware type-expansion follies! */
- BUILD_BUG_ON(!typecheck(u16, rq->engine->uabi_class));
- return flag(rq->engine->uabi_class);
+ /* Beware type-expansion follies! */
+ BUILD_BUG_ON(!typecheck(u16, rq->engine->uabi_class));
+ return flag(rq->engine->uabi_class);
+ }
}
static __always_inline unsigned int
-busy_check_reader(const struct dma_fence *fence)
+busy_check_reader(struct dma_fence *fence)
{
return __busy_set_if_active(fence, __busy_read_flag);
}
static __always_inline unsigned int
-busy_check_writer(const struct dma_fence *fence)
+busy_check_writer(struct dma_fence *fence)
{
if (!fence)
return 0;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 5c7fb6f68bbb..16276f406fd6 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -2988,8 +2988,11 @@ eb_composite_fence_create(struct i915_execbuffer *eb,
int out_fence_fd)
if (!fences)
return ERR_PTR(-ENOMEM);
- for_each_batch_create_order(eb, i)
+ for_each_batch_create_order(eb, i) {
fences[i] = >requests[i]->fence;
+
Re: [Intel-gfx] [PATCH 17/26] drm/i915/guc: Connect UAPI to GuC multi-lrc interface
On 10/4/2021 15:06, Matthew Brost wrote:
Introduce 'set parallel submit' extension to connect UAPI to GuC
multi-lrc interface. Kernel doc in new uAPI should explain it all.
IGT: https://patchwork.freedesktop.org/patch/447008/?series=93071=1
media UMD: https://github.com/intel/media-driver/pull/1252
v2:
(Daniel Vetter)
- Add IGT link and placeholder for media UMD link
v3:
(Kernel test robot)
- Fix warning in unpin engines call
(John Harrison)
- Reword a bunch of the kernel doc
Cc: Tvrtko Ursulin
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 221 +-
.../gpu/drm/i915/gem/i915_gem_context_types.h | 6 +
drivers/gpu/drm/i915/gt/intel_context_types.h | 9 +-
drivers/gpu/drm/i915/gt/intel_engine.h| 12 +-
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 6 +-
.../drm/i915/gt/intel_execlists_submission.c | 6 +-
drivers/gpu/drm/i915/gt/selftest_execlists.c | 12 +-
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 114 -
include/uapi/drm/i915_drm.h | 131 +++
9 files changed, 489 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 8c7ea6e56262..6290bc20ccb1 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -522,9 +522,150 @@ set_proto_ctx_engines_bond(struct i915_user_extension
__user *base, void *data)
return 0;
}
+static int
+set_proto_ctx_engines_parallel_submit(struct i915_user_extension __user *base,
+ void *data)
+{
+ struct i915_context_engines_parallel_submit __user *ext =
+ container_of_user(base, typeof(*ext), base);
+ const struct set_proto_ctx_engines *set = data;
+ struct drm_i915_private *i915 = set->i915;
+ u64 flags;
+ int err = 0, n, i, j;
+ u16 slot, width, num_siblings;
+ struct intel_engine_cs **siblings = NULL;
+ intel_engine_mask_t prev_mask;
+
+ /* Disabling for now */
+ return -ENODEV;
+
+ /* FIXME: This is NIY for execlists */
+ if (!(intel_uc_uses_guc_submission(>gt.uc)))
+ return -ENODEV;
+
+ if (get_user(slot, >engine_index))
+ return -EFAULT;
+
+ if (get_user(width, >width))
+ return -EFAULT;
+
+ if (get_user(num_siblings, >num_siblings))
+ return -EFAULT;
+
+ if (slot >= set->num_engines) {
+ drm_dbg(>drm, "Invalid placement value, %d >= %d\n",
+ slot, set->num_engines);
+ return -EINVAL;
+ }
+
+ if (set->engines[slot].type != I915_GEM_ENGINE_TYPE_INVALID) {
+ drm_dbg(>drm,
+ "Invalid placement[%d], already occupied\n", slot);
+ return -EINVAL;
+ }
+
+ if (get_user(flags, >flags))
+ return -EFAULT;
+
+ if (flags) {
+ drm_dbg(>drm, "Unknown flags 0x%02llx", flags);
+ return -EINVAL;
+ }
+
+ for (n = 0; n < ARRAY_SIZE(ext->mbz64); n++) {
+ err = check_user_mbz(>mbz64[n]);
+ if (err)
+ return err;
+ }
+
+ if (width < 2) {
+ drm_dbg(>drm, "Width (%d) < 2\n", width);
+ return -EINVAL;
+ }
+
+ if (num_siblings < 1) {
+ drm_dbg(>drm, "Number siblings (%d) < 1\n",
+ num_siblings);
+ return -EINVAL;
+ }
+
+ siblings = kmalloc_array(num_siblings * width,
+sizeof(*siblings),
+GFP_KERNEL);
+ if (!siblings)
+ return -ENOMEM;
+
+ /* Create contexts / engines */
+ for (i = 0; i < width; ++i) {
+ intel_engine_mask_t current_mask = 0;
+ struct i915_engine_class_instance prev_engine;
+
+ for (j = 0; j < num_siblings; ++j) {
+ struct i915_engine_class_instance ci;
+
+ n = i * num_siblings + j;
+ if (copy_from_user(, >engines[n], sizeof(ci))) {
+ err = -EFAULT;
+ goto out_err;
+ }
+
+ siblings[n] =
+ intel_engine_lookup_user(i915, ci.engine_class,
+ci.engine_instance);
+ if (!siblings[n]) {
+ drm_dbg(>drm,
+ "Invalid sibling[%d]: { class:%d, inst:%d
}\n",
+ n, ci.engine_class, ci.engine_instance);
+ err = -EINVAL;
+ goto out_err;
+ }
+
+ if (n) {
+
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/4] dri: do not check for NULL debugfs dentry
== Series Details == Series: series starting with [1/4] dri: do not check for NULL debugfs dentry URL : https://patchwork.freedesktop.org/series/95691/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/ttm/ttm_device.c:138:5: warning: context imbalance in 'ttm_device_swapout' - wrong count at exit
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/dp, drm/i915: Finish basic PWM support for VESA backlight helpers (rev9)
== Series Details ==
Series: drm/dp, drm/i915: Finish basic PWM support for VESA backlight helpers
(rev9)
URL : https://patchwork.freedesktop.org/series/95127/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10719 -> Patchwork_21310
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21310/index.html
Known issues
Here are the changes found in Patchwork_21310 that come from known issues:
### IGT changes ###
Issues hit
* igt@kms_flip@basic-flip-vs-modeset@c-dp1:
- fi-cfl-8109u: [PASS][1] -> [FAIL][2] ([i915#4165])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10719/fi-cfl-8109u/igt@kms_flip@basic-flip-vs-mode...@c-dp1.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21310/fi-cfl-8109u/igt@kms_flip@basic-flip-vs-mode...@c-dp1.html
* igt@kms_frontbuffer_tracking@basic:
- fi-cml-u2: [PASS][3] -> [DMESG-WARN][4] ([i915#4269])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10719/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21310/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html
- fi-cfl-8109u: [PASS][5] -> [FAIL][6] ([i915#2546])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10719/fi-cfl-8109u/igt@kms_frontbuffer_track...@basic.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21310/fi-cfl-8109u/igt@kms_frontbuffer_track...@basic.html
Possible fixes
* igt@i915_selftest@live@gt_heartbeat:
- fi-bdw-5557u: [DMESG-FAIL][7] ([i915#541]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10719/fi-bdw-5557u/igt@i915_selftest@live@gt_heartbeat.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21310/fi-bdw-5557u/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@hangcheck:
- {fi-hsw-gt1}: [DMESG-WARN][9] ([i915#3303]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10719/fi-hsw-gt1/igt@i915_selftest@l...@hangcheck.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21310/fi-hsw-gt1/igt@i915_selftest@l...@hangcheck.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#2546]: https://gitlab.freedesktop.org/drm/intel/issues/2546
[i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
[i915#4165]: https://gitlab.freedesktop.org/drm/intel/issues/4165
[i915#4269]: https://gitlab.freedesktop.org/drm/intel/issues/4269
[i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541
Participating hosts (38 -> 36)
--
Missing(2): fi-bsw-cyan fi-kbl-guc
Build changes
-
* Linux: CI_DRM_10719 -> Patchwork_21310
CI-20190529: 20190529
CI_DRM_10719: b138938ad4071c045a865977718019951186e322 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6242: 721fd85ee95225ed5df322f7182bdfa9b86a3e68 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_21310: f2751a8b6787e59aa3395f5130379c3cf3e328bf @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
f2751a8b6787 drm/i915: Clarify probing order in
intel_dp_aux_init_backlight_funcs()
efe191cffc6d drm/dp, drm/i915: Add support for VESA backlights using PWM for
brightness control
6ec021b316be drm/dp: Disable unsupported features in
DP_EDP_BACKLIGHT_MODE_SET_REGISTER
1401f26cc795 drm/nouveau/kms/nv50-: Explicitly check DPCD backlights for aux
enable/brightness
6297c337b4ea drm/i915: Add support for panels with VESA backlights with PWM
enable/disable
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21310/index.html
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/dp, drm/i915: Finish basic PWM support for VESA backlight helpers (rev9)
== Series Details == Series: drm/dp, drm/i915: Finish basic PWM support for VESA backlight helpers (rev9) URL : https://patchwork.freedesktop.org/series/95127/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be
Re: [Intel-gfx] [PATCH v3] drm/i915/display: Wait PSR2 get out of deep sleep to update pipe
On Thu, 2021-10-07 at 12:31 +0300, Gwan-gyeong Mun wrote:
>
> On 10/6/21 11:04 PM, Souza, Jose wrote:
> > On Wed, 2021-10-06 at 11:50 +0300, Gwan-gyeong Mun wrote:
> > >
> > > On 10/6/21 2:18 AM, José Roberto de Souza wrote:
> > > > Alderlake-P was getting 'max time under evasion' messages when PSR2
> > > > is enabled, this is due PIPE_SCANLINE/PIPEDSL returning 0 over a
> > > > period of time longer than VBLANK_EVASION_TIME_US.
> > > >
> > > > For PSR1 we had the same issue so intel_psr_wait_for_idle() was
> > > > implemented to wait for PSR1 to get into idle state but nothing was
> > > > done for PSR2.
> > > >
> > > > For PSR2 we can't only wait for idle state as PSR2 tends to keep
> > > > into sleep state(ready to send selective updates).
> > > > Waiting for any state below deep sleep proved to be effective in
> > > > avoiding the evasion messages and also not wasted a lot of time.
> > > >
> > > > v2:
> > > > - dropping the additional wait_for loops, only the _wait_for_atomic()
> > > > is necessary
> > > > - waiting for states below EDP_PSR2_STATUS_STATE_DEEP_SLEEP
> > > >
> > > > v3:
> > > > - dropping intel_wait_for_condition_atomic() function
> > > >
> > > > Cc: Ville Syrjälä
> > > > Cc: Gwan-gyeong Mun
> > > > Signed-off-by: José Roberto de Souza
> > > > ---
> > > >.../drm/i915/display/intel_display_debugfs.c | 3 +-
> > > >drivers/gpu/drm/i915/display/intel_psr.c | 52
> > > > +++
> > > >drivers/gpu/drm/i915/i915_reg.h | 10 ++--
> > > >3 files changed, 36 insertions(+), 29 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > > > b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > > > index 309d74fd86ce1..d7dd3a57c6170 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > > > @@ -303,8 +303,7 @@ psr_source_status(struct intel_dp *intel_dp, struct
> > > > seq_file *m)
> > > >};
> > > >val = intel_de_read(dev_priv,
> > > >EDP_PSR2_STATUS(intel_dp->psr.transcoder));
> > > > -status_val = (val & EDP_PSR2_STATUS_STATE_MASK) >>
> > > > - EDP_PSR2_STATUS_STATE_SHIFT;
> > > > +status_val = REG_FIELD_GET(EDP_PSR2_STATUS_STATE_MASK, val);
> > > >if (status_val < ARRAY_SIZE(live_status))
> > > >status = live_status[status_val];
> > > >} else {
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > > > b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > index 7a205fd5023bb..ade514fc0a24d 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > @@ -1809,15 +1809,21 @@ void intel_psr_post_plane_update(const struct
> > > > intel_atomic_state *state)
> > > >_intel_psr_post_plane_update(state, crtc_state);
> > > >}
> > > >
> > > > -/**
> > > > - * psr_wait_for_idle - wait for PSR1 to idle
> > > > - * @intel_dp: Intel DP
> > > > - * @out_value: PSR status in case of failure
> > > > - *
> > > > - * Returns: 0 on success or -ETIMEOUT if PSR status does not idle.
> > > > - *
> > > > - */
> > > > -static int psr_wait_for_idle(struct intel_dp *intel_dp, u32 *out_value)
> > > > +static int _psr2_ready_for_pipe_update_locked(struct intel_dp
> > > > *intel_dp)
> > > > +{
> > > > +struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > > > +
> > > > +/*
> > > > + * Any state lower than EDP_PSR2_STATUS_STATE_DEEP_SLEEP is enough.
> > > > + * As all higher states has bit 4 of PSR2 state set we can just wait
> > > > for
> > > > + * EDP_PSR2_STATUS_STATE_DEEP_SLEEP to be cleared.
> > > > + */
> > > > +return intel_de_wait_for_clear(dev_priv,
> > > > + EDP_PSR2_STATUS(intel_dp->psr.transcoder),
> > > > + EDP_PSR2_STATUS_STATE_DEEP_SLEEP, 50);
> > > Under the DEEP_SLEEP state, there are IDLE, CAPTURE, CPTURE_FS, SLEEP,
> > > BUFON_FW, ML_UP, SU_STANDBY, etc. In this case, whether the evasion
> > > messages are completely tested in the state that changes quickly I think
> > > the test period is a little insufficient.
> >
> > What is your suggestion of test for this?
> >
> > I left my Alderlake-P running overnight(more than 12 hours) with a News
> > website open.
> > This website reloads the page at every 5 minutes, so it entered and exited
> > DC5/6 states several times without any evasion messages.
> >
> > > I think it may be necessary to test a little more or to have
> > > confirmation from the HW person in charge.
> >
> > I can file an issue for this but it will probably several weeks to get an
> > answer.
> >
> Yes, I am not disparaging what you tested.
> However, since the current code confirms that only the 31st bit of the
> PSR2_STATUS register is changed to 0 operationally,
> it does not guarantee that the tested use cases have been tested for
> IDLE, CAPTURE, CPTURE_FS, SLEEP, BUFON_FW, ML_UP, SU_STANDBY, and
> FAST_SLEEP states.
>
> I can't think of a way to test
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/guc: Inject probe errors for MMIO send, CT send
== Series Details == Series: drm/i915/guc: Inject probe errors for MMIO send, CT send URL : https://patchwork.freedesktop.org/series/95683/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10716_full -> Patchwork_21305_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_21305_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_21305_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_21305_full: ### IGT changes ### Possible regressions * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90: - shard-tglb: NOTRUN -> [SKIP][1] +3 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21305/shard-tglb3/igt@kms_rotation_...@primary-yf-tiled-reflect-x-90.html Known issues Here are the changes found in Patchwork_21305_full that come from known issues: ### IGT changes ### Issues hit * igt@feature_discovery@display-2x: - shard-tglb: NOTRUN -> [SKIP][2] ([i915#1839]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21305/shard-tglb3/igt@feature_discov...@display-2x.html * igt@gem_ctx_persistence@process: - shard-snb: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#1099]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21305/shard-snb7/igt@gem_ctx_persiste...@process.html * igt@gem_ctx_sseu@invalid-args: - shard-tglb: NOTRUN -> [SKIP][4] ([i915#280]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21305/shard-tglb3/igt@gem_ctx_s...@invalid-args.html * igt@gem_exec_fair@basic-none-rrul@rcs0: - shard-tglb: NOTRUN -> [FAIL][5] ([i915#2842]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21305/shard-tglb3/igt@gem_exec_fair@basic-none-r...@rcs0.html * igt@gem_exec_fair@basic-none@vcs1: - shard-iclb: NOTRUN -> [FAIL][6] ([i915#2842]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21305/shard-iclb2/igt@gem_exec_fair@basic-n...@vcs1.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-glk: [PASS][7] -> [FAIL][8] ([i915#2842]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10716/shard-glk6/igt@gem_exec_fair@basic-pace-sh...@rcs0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21305/shard-glk8/igt@gem_exec_fair@basic-pace-sh...@rcs0.html * igt@gem_exec_fair@basic-pace@rcs0: - shard-tglb: [PASS][9] -> [FAIL][10] ([i915#2842]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10716/shard-tglb7/igt@gem_exec_fair@basic-p...@rcs0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21305/shard-tglb6/igt@gem_exec_fair@basic-p...@rcs0.html * igt@gem_exec_fair@basic-pace@vecs0: - shard-kbl: NOTRUN -> [FAIL][11] ([i915#2842]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21305/shard-kbl1/igt@gem_exec_fair@basic-p...@vecs0.html * igt@gem_pread@exhaustion: - shard-glk: NOTRUN -> [WARN][12] ([i915#2658]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21305/shard-glk2/igt@gem_pr...@exhaustion.html - shard-snb: NOTRUN -> [WARN][13] ([i915#2658]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21305/shard-snb2/igt@gem_pr...@exhaustion.html * igt@gem_pwrite@basic-exhaustion: - shard-tglb: NOTRUN -> [WARN][14] ([i915#2658]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21305/shard-tglb3/igt@gem_pwr...@basic-exhaustion.html * igt@gem_pxp@protected-encrypted-src-copy-not-readible: - shard-tglb: NOTRUN -> [SKIP][15] ([i915#4270]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21305/shard-tglb2/igt@gem_...@protected-encrypted-src-copy-not-readible.html * igt@gem_userptr_blits@input-checking: - shard-apl: NOTRUN -> [DMESG-WARN][16] ([i915#3002]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21305/shard-apl6/igt@gem_userptr_bl...@input-checking.html - shard-kbl: NOTRUN -> [DMESG-WARN][17] ([i915#3002]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21305/shard-kbl1/igt@gem_userptr_bl...@input-checking.html * igt@gen3_render_mixed_blits: - shard-tglb: NOTRUN -> [SKIP][18] ([fdo#109289]) +1 similar issue [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21305/shard-tglb3/igt@gen3_render_mixed_blits.html * igt@gen9_exec_parse@allowed-single: - shard-skl: [PASS][19] -> [DMESG-WARN][20] ([i915#1436] / [i915#716]) [19]:
Re: [Intel-gfx] [PATCH 4/4] vgaswitcheroo: do not check for NULL debugfs dentry
On Mon, Oct 11, 2021 at 09:06:07PM +0200, Nirmoy Das wrote:
> Debugfs APIs returns encoded error on failure so use
> debugfs_lookup() instead of checking for NULL.
[...]
> --- a/drivers/gpu/vga/vga_switcheroo.c
> +++ b/drivers/gpu/vga/vga_switcheroo.c
> @@ -914,7 +914,7 @@ static void vga_switcheroo_debugfs_fini(struct vgasr_priv
> *priv)
> static void vga_switcheroo_debugfs_init(struct vgasr_priv *priv)
> {
> /* already initialised */
> - if (priv->debugfs_root)
> + if (debugfs_lookup("vgaswitcheroo", NULL))
> return;
>
> priv->debugfs_root = debugfs_create_dir("vgaswitcheroo", NULL);
If debugfs_create_dir() returns an error code, it does make sense to
retry the call when another vga_switcheroo client registers later.
I like that.
However I'd prefer simply changing this to explicitly check for NULL, i.e.:
- if (priv->debugfs_root)
+ if (priv->debugfs_root == NULL)
It's just as clear as calling debugfs_lookup() and it has way less
overhead. Granted, this isn't a hot path, but it's called on boot,
and the less code we execute, the faster the machine boots.
Thanks,
Lukas
[Intel-gfx] ✓ Fi.CI.BAT: success for Fixup header includes (rev3)
== Series Details == Series: Fixup header includes (rev3) URL : https://patchwork.freedesktop.org/series/95587/ State : success == Summary == CI Bug Log - changes from CI_DRM_10717 -> Patchwork_21309 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21309/index.html Known issues Here are the changes found in Patchwork_21309 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@cs-gfx: - fi-kbl-soraka: NOTRUN -> [SKIP][1] ([fdo#109271]) +11 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21309/fi-kbl-soraka/igt@amdgpu/amd_ba...@cs-gfx.html * igt@amdgpu/amd_basic@query-info: - fi-tgl-1115g4: NOTRUN -> [SKIP][2] ([fdo#109315]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21309/fi-tgl-1115g4/igt@amdgpu/amd_ba...@query-info.html * igt@amdgpu/amd_cs_nop@nop-gfx0: - fi-tgl-1115g4: NOTRUN -> [SKIP][3] ([fdo#109315] / [i915#2575]) +16 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21309/fi-tgl-1115g4/igt@amdgpu/amd_cs_...@nop-gfx0.html * igt@amdgpu/amd_cs_nop@sync-fork-compute0: - fi-snb-2600:NOTRUN -> [SKIP][4] ([fdo#109271]) +17 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21309/fi-snb-2600/igt@amdgpu/amd_cs_...@sync-fork-compute0.html * igt@gem_exec_suspend@basic-s0: - fi-tgl-1115g4: NOTRUN -> [FAIL][5] ([i915#1888]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21309/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s0.html * igt@gem_huc_copy@huc-copy: - fi-kbl-soraka: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#2190]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21309/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html - fi-tgl-1115g4: NOTRUN -> [SKIP][7] ([i915#2190]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21309/fi-tgl-1115g4/igt@gem_huc_c...@huc-copy.html * igt@i915_pm_backlight@basic-brightness: - fi-tgl-1115g4: NOTRUN -> [SKIP][8] ([i915#1155]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21309/fi-tgl-1115g4/igt@i915_pm_backli...@basic-brightness.html * igt@i915_selftest@live@gt_heartbeat: - fi-bdw-5557u: [PASS][9] -> [DMESG-FAIL][10] ([i915#541]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10717/fi-bdw-5557u/igt@i915_selftest@live@gt_heartbeat.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21309/fi-bdw-5557u/igt@i915_selftest@live@gt_heartbeat.html * igt@i915_selftest@live@gt_pm: - fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][11] ([i915#1886] / [i915#2291]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21309/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-tgl-1115g4: NOTRUN -> [SKIP][12] ([fdo#111827]) +8 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21309/fi-tgl-1115g4/igt@kms_chamel...@common-hpd-after-suspend.html - fi-kbl-soraka: NOTRUN -> [SKIP][13] ([fdo#109271] / [fdo#111827]) +8 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21309/fi-kbl-soraka/igt@kms_chamel...@common-hpd-after-suspend.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-tgl-1115g4: NOTRUN -> [SKIP][14] ([i915#4103]) +1 similar issue [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21309/fi-tgl-1115g4/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html * igt@kms_force_connector_basic@force-load-detect: - fi-tgl-1115g4: NOTRUN -> [SKIP][15] ([fdo#109285]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21309/fi-tgl-1115g4/igt@kms_force_connector_ba...@force-load-detect.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d: - fi-kbl-soraka: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#533]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21309/fi-kbl-soraka/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: - fi-skl-6600u: [PASS][17] -> [INCOMPLETE][18] ([i915#198]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10717/fi-skl-6600u/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21309/fi-skl-6600u/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html * igt@kms_psr@primary_mmap_gtt: - fi-tgl-1115g4: NOTRUN -> [SKIP][19] ([i915#1072]) +3 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21309/fi-tgl-1115g4/igt@kms_psr@primary_mmap_gtt.html * igt@prime_vgem@basic-userptr: - fi-tgl-1115g4: NOTRUN -> [SKIP][20] ([i915#3301]) [20]:
Re: [Intel-gfx] [PATCH 2/2] drm/i915/pmu: Connect engine busyness stats from GuC to pmu
On Mon, Oct 11, 2021 at 12:41:19PM +0100, Tvrtko Ursulin wrote:
On 07/10/2021 23:55, Umesh Nerlige Ramappa wrote:
With GuC handling scheduling, i915 is not aware of the time that a
context is scheduled in and out of the engine. Since i915 pmu relies on
this info to provide engine busyness to the user, GuC shares this info
with i915 for all engines using shared memory. For each engine, this
info contains:
- total busyness: total time that the context was running (total)
- id: id of the running context (id)
- start timestamp: timestamp when the context started running (start)
At the time (now) of sampling the engine busyness, if the id is valid
(!= ~0), and start is non-zero, then the context is considered to be
active and the engine busyness is calculated using the below equation
engine busyness = total + (now - start)
All times are obtained from the gt clock base. For inactive contexts,
engine busyness is just equal to the total.
The start and total values provided by GuC are 32 bits and wrap around
in a few minutes. Since perf pmu provides busyness as 64 bit
monotonically increasing values, there is a need for this implementation
to account for overflows and extend the time to 64 bits before returning
busyness to the user. In order to do that, a worker runs periodically at
frequency = 1/8th the time it takes for the timestamp to wrap. As an
example, that would be once in 27 seconds for a gt clock frequency of
19.2 MHz.
Note:
There might be an overaccounting of busyness due to the fact that GuC
may be updating the total and start values while kmd is reading them.
(i.e kmd may read the updated total and the stale start). In such a
case, user may see higher busyness value followed by smaller ones which
would eventually catch up to the higher value.
v2: (Tvrtko)
- Include details in commit message
- Move intel engine busyness function into execlist code
- Use union inside engine->stats
- Use natural type for ping delay jiffies
- Drop active_work condition checks
- Use for_each_engine if iterating all engines
- Drop seq locking, use spinlock at guc level to update engine stats
- Document worker specific details
v3: (Tvrtko/Umesh)
- Demarcate guc and execlist stat objects with comments
- Document known over-accounting issue in commit
- Provide a consistent view of guc state
- Add hooks to gt park/unpark for guc busyness
- Stop/start worker in gt park/unpark path
- Drop inline
- Move spinlock and worker inits to guc initialization
- Drop helpers that are called only once
v4: (Tvrtko/Matt/Umesh)
- Drop addressed opens from commit message
- Get runtime pm in ping, remove from the park path
- Use cancel_delayed_work_sync in disable_submission path
- Update stats during reset prepare
- Skip ping if reset in progress
- Explicitly name execlists and guc stats objects
- Since disable_submission is called from many places, move resetting
stats to intel_guc_submission_reset_prepare
Signed-off-by: John Harrison
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 28 +--
drivers/gpu/drm/i915/gt/intel_engine_types.h | 33 ++-
.../drm/i915/gt/intel_execlists_submission.c | 34 +++
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 2 +
.../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h | 1 +
drivers/gpu/drm/i915/gt/uc/intel_guc.h| 26 ++
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c| 21 ++
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.h| 5 +
drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 13 +
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 238 ++
.../gpu/drm/i915/gt/uc/intel_guc_submission.h | 2 +
drivers/gpu/drm/i915/i915_reg.h | 2 +
12 files changed, 377 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 38436f4b5706..6b783fdcba2a 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1873,23 +1873,6 @@ void intel_engine_dump(struct intel_engine_cs *engine,
intel_engine_print_breadcrumbs(engine, m);
}
-static ktime_t __intel_engine_get_busy_time(struct intel_engine_cs *engine,
- ktime_t *now)
-{
- struct intel_engine_execlists_stats *stats = >stats.execlists;
- ktime_t total = stats->total;
-
- /*
-* If the engine is executing something at the moment
-* add it to the total.
-*/
- *now = ktime_get();
- if (READ_ONCE(stats->active))
- total = ktime_add(total, ktime_sub(*now, stats->start));
-
- return total;
-}
-
/**
* intel_engine_get_busy_time() - Return current accumulated engine busyness
* @engine: engine to report on
@@ -1899,16 +1882,7 @@ static ktime_t __intel_engine_get_busy_time(struct
intel_engine_cs *engine,
*/
ktime_t intel_engine_get_busy_time(struct intel_engine_cs *engine, ktime_t
*now)
{
- struct
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Fixup header includes (rev3)
== Series Details == Series: Fixup header includes (rev3) URL : https://patchwork.freedesktop.org/series/95587/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_reset.c:1392:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/i915_perf.c:1442:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1496:15: warning: memset with byte count of 16777216 +./include/asm-generic/bitops/find.h:112:45: warning: shift count is negative (-262080) +./include/asm-generic/bitops/find.h:32:31: warning: shift count is negative (-262080) +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v8,1/8] drm/i915/gem: Break out some shmem backend utils
== Series Details == Series: series starting with [v8,1/8] drm/i915/gem: Break out some shmem backend utils URL : https://patchwork.freedesktop.org/series/95677/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10716_full -> Patchwork_21304_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_21304_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_21304_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_21304_full: ### IGT changes ### Possible regressions * igt@kms_frontbuffer_tracking@fbc-suspend: - shard-kbl: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10716/shard-kbl1/igt@kms_frontbuffer_track...@fbc-suspend.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21304/shard-kbl4/igt@kms_frontbuffer_track...@fbc-suspend.html * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90: - shard-tglb: NOTRUN -> [SKIP][3] +3 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21304/shard-tglb2/igt@kms_rotation_...@primary-yf-tiled-reflect-x-90.html Known issues Here are the changes found in Patchwork_21304_full that come from known issues: ### IGT changes ### Issues hit * igt@feature_discovery@display-2x: - shard-tglb: NOTRUN -> [SKIP][4] ([i915#1839]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21304/shard-tglb2/igt@feature_discov...@display-2x.html * igt@gem_ctx_sseu@invalid-args: - shard-tglb: NOTRUN -> [SKIP][5] ([i915#280]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21304/shard-tglb2/igt@gem_ctx_s...@invalid-args.html * igt@gem_eio@unwedge-stress: - shard-skl: [PASS][6] -> [TIMEOUT][7] ([i915#2369] / [i915#3063]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10716/shard-skl7/igt@gem_...@unwedge-stress.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21304/shard-skl2/igt@gem_...@unwedge-stress.html * igt@gem_exec_fair@basic-none-rrul@rcs0: - shard-tglb: NOTRUN -> [FAIL][8] ([i915#2842]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21304/shard-tglb6/igt@gem_exec_fair@basic-none-r...@rcs0.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-tglb: [PASS][9] -> [FAIL][10] ([i915#2842]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10716/shard-tglb6/igt@gem_exec_fair@basic-pace-sh...@rcs0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21304/shard-tglb8/igt@gem_exec_fair@basic-pace-sh...@rcs0.html - shard-glk: [PASS][11] -> [FAIL][12] ([i915#2842]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10716/shard-glk6/igt@gem_exec_fair@basic-pace-sh...@rcs0.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21304/shard-glk3/igt@gem_exec_fair@basic-pace-sh...@rcs0.html * igt@gem_exec_fair@basic-pace@rcs0: - shard-kbl: NOTRUN -> [FAIL][13] ([i915#2842]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21304/shard-kbl3/igt@gem_exec_fair@basic-p...@rcs0.html * igt@gem_pread@exhaustion: - shard-glk: NOTRUN -> [WARN][14] ([i915#2658]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21304/shard-glk5/igt@gem_pr...@exhaustion.html * igt@gem_pwrite@basic-exhaustion: - shard-tglb: NOTRUN -> [WARN][15] ([i915#2658]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21304/shard-tglb2/igt@gem_pwr...@basic-exhaustion.html * igt@gem_pxp@protected-encrypted-src-copy-not-readible: - shard-tglb: NOTRUN -> [SKIP][16] ([i915#4270]) +1 similar issue [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21304/shard-tglb3/igt@gem_...@protected-encrypted-src-copy-not-readible.html * igt@gem_userptr_blits@input-checking: - shard-apl: NOTRUN -> [DMESG-WARN][17] ([i915#3002]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21304/shard-apl2/igt@gem_userptr_bl...@input-checking.html - shard-kbl: NOTRUN -> [DMESG-WARN][18] ([i915#3002]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21304/shard-kbl3/igt@gem_userptr_bl...@input-checking.html * igt@gem_userptr_blits@vma-merge: - shard-apl: NOTRUN -> [FAIL][19] ([i915#3318]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21304/shard-apl8/igt@gem_userptr_bl...@vma-merge.html * igt@gem_workarounds@suspend-resume-context: - shard-tglb: [PASS][20] -> [INCOMPLETE][21] ([i915#456]) [20]:
[Intel-gfx] [PATCH] drm/i915/selftests: Skip hangcheck selftest on DG1
The hangcheck selftest blows on DG1 CI and aborts the BAT run. Investigation is underway to root cause the failure but in the meantime disable to this test on DG1 to unblock CI. Signed-off-by: Matthew Brost --- drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 8 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c index 7e2d99dd012d..e2115afbd073 100644 --- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c +++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c @@ -2018,6 +2018,14 @@ int intel_hangcheck_live_selftests(struct drm_i915_private *i915) intel_wakeref_t wakeref; int err; + /* +* FIXME: This test is blowing up in CI on DG1 due to engine resets +* sporadically timing out. Investigation to root cause this under way. +* In the meantime skip this test to unblock CI. +*/ + if (IS_DG1(i915)) + return 0; + if (!intel_has_gpu_reset(gt)) return 0; -- 2.32.0
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/dp: abstract intel_dp_lane_max_vswing_reached()
== Series Details == Series: series starting with [1/2] drm/i915/dp: abstract intel_dp_lane_max_vswing_reached() URL : https://patchwork.freedesktop.org/series/95689/ State : success == Summary == CI Bug Log - changes from CI_DRM_10717 -> Patchwork_21308 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21308/index.html Known issues Here are the changes found in Patchwork_21308 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@cs-gfx: - fi-kbl-soraka: NOTRUN -> [SKIP][1] ([fdo#109271]) +15 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21308/fi-kbl-soraka/igt@amdgpu/amd_ba...@cs-gfx.html * igt@amdgpu/amd_basic@query-info: - fi-tgl-1115g4: NOTRUN -> [SKIP][2] ([fdo#109315]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21308/fi-tgl-1115g4/igt@amdgpu/amd_ba...@query-info.html * igt@amdgpu/amd_cs_nop@nop-gfx0: - fi-tgl-1115g4: NOTRUN -> [SKIP][3] ([fdo#109315] / [i915#2575]) +16 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21308/fi-tgl-1115g4/igt@amdgpu/amd_cs_...@nop-gfx0.html * igt@debugfs_test@read_all_entries: - fi-kbl-soraka: [PASS][4] -> [DMESG-WARN][5] ([i915#1982] / [i915#262]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10717/fi-kbl-soraka/igt@debugfs_test@read_all_entries.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21308/fi-kbl-soraka/igt@debugfs_test@read_all_entries.html * igt@gem_huc_copy@huc-copy: - fi-kbl-soraka: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#2190]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21308/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html - fi-tgl-1115g4: NOTRUN -> [SKIP][7] ([i915#2190]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21308/fi-tgl-1115g4/igt@gem_huc_c...@huc-copy.html * igt@i915_pm_backlight@basic-brightness: - fi-tgl-1115g4: NOTRUN -> [SKIP][8] ([i915#1155]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21308/fi-tgl-1115g4/igt@i915_pm_backli...@basic-brightness.html * igt@i915_pm_rpm@basic-pci-d3-state: - fi-skl-6600u: [PASS][9] -> [FAIL][10] ([i915#3239]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10717/fi-skl-6600u/igt@i915_pm_...@basic-pci-d3-state.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21308/fi-skl-6600u/igt@i915_pm_...@basic-pci-d3-state.html * igt@i915_selftest@live@execlists: - fi-bsw-nick:[PASS][11] -> [INCOMPLETE][12] ([i915#2940]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10717/fi-bsw-nick/igt@i915_selftest@l...@execlists.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21308/fi-bsw-nick/igt@i915_selftest@l...@execlists.html * igt@i915_selftest@live@gt_pm: - fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][13] ([i915#1886] / [i915#2291]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21308/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-tgl-1115g4: NOTRUN -> [SKIP][14] ([fdo#111827]) +8 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21308/fi-tgl-1115g4/igt@kms_chamel...@common-hpd-after-suspend.html - fi-kbl-soraka: NOTRUN -> [SKIP][15] ([fdo#109271] / [fdo#111827]) +8 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21308/fi-kbl-soraka/igt@kms_chamel...@common-hpd-after-suspend.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-tgl-1115g4: NOTRUN -> [SKIP][16] ([i915#4103]) +1 similar issue [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21308/fi-tgl-1115g4/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html * igt@kms_force_connector_basic@force-load-detect: - fi-tgl-1115g4: NOTRUN -> [SKIP][17] ([fdo#109285]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21308/fi-tgl-1115g4/igt@kms_force_connector_ba...@force-load-detect.html * igt@kms_frontbuffer_tracking@basic: - fi-cml-u2: [PASS][18] -> [DMESG-WARN][19] ([i915#4269]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10717/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21308/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d: - fi-kbl-soraka: NOTRUN -> [SKIP][20] ([fdo#109271] / [i915#533]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21308/fi-kbl-soraka/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html * igt@kms_psr@primary_mmap_gtt: - fi-tgl-1115g4: NOTRUN -> [SKIP][21] ([i915#1072]) +3 similar issues [21]:
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/dp: abstract intel_dp_lane_max_vswing_reached()
== Series Details ==
Series: series starting with [1/2] drm/i915/dp: abstract
intel_dp_lane_max_vswing_reached()
URL : https://patchwork.freedesktop.org/series/95689/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
89b690d2e4c1 drm/i915/dp: abstract intel_dp_lane_max_vswing_reached()
a5f36be2f5c0 drm/i915/dg2: update link training for 128b/132b
-:53: WARNING:UNNECESSARY_ELSE: else is not generally useful after a break or
return
#53: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:1349:
+ return train_set & DP_TX_FFE_PRESET_VALUE_MASK;
+ } else {
-:85: CHECK:LINE_SPACING: Please don't use multiple blank lines
#85: FILE: drivers/gpu/drm/i915/display/intel_dp_link_training.c:307:
+
-:142: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in
parentheses
#142: FILE: drivers/gpu/drm/i915/display/intel_dp_link_training.c:396:
+#define TRAIN_REQ_TX_FFE_ARGS(link_status) \
+ _TRAIN_REQ_TX_FFE_ARGS(link_status, 0), \
+ _TRAIN_REQ_TX_FFE_ARGS(link_status, 1), \
+ _TRAIN_REQ_TX_FFE_ARGS(link_status, 2), \
+ _TRAIN_REQ_TX_FFE_ARGS(link_status, 3)
-:142: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'link_status' - possible
side-effects?
#142: FILE: drivers/gpu/drm/i915/display/intel_dp_link_training.c:396:
+#define TRAIN_REQ_TX_FFE_ARGS(link_status) \
+ _TRAIN_REQ_TX_FFE_ARGS(link_status, 0), \
+ _TRAIN_REQ_TX_FFE_ARGS(link_status, 1), \
+ _TRAIN_REQ_TX_FFE_ARGS(link_status, 2), \
+ _TRAIN_REQ_TX_FFE_ARGS(link_status, 3)
-:188: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in
parentheses
#188: FILE: drivers/gpu/drm/i915/display/intel_dp_link_training.c:521:
+#define TRAIN_SET_TX_FFE_ARGS(train_set) \
+ _TRAIN_SET_TX_FFE_ARGS((train_set)[0]), \
+ _TRAIN_SET_TX_FFE_ARGS((train_set)[1]), \
+ _TRAIN_SET_TX_FFE_ARGS((train_set)[2]), \
+ _TRAIN_SET_TX_FFE_ARGS((train_set)[3])
-:188: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'train_set' - possible
side-effects?
#188: FILE: drivers/gpu/drm/i915/display/intel_dp_link_training.c:521:
+#define TRAIN_SET_TX_FFE_ARGS(train_set) \
+ _TRAIN_SET_TX_FFE_ARGS((train_set)[0]), \
+ _TRAIN_SET_TX_FFE_ARGS((train_set)[1]), \
+ _TRAIN_SET_TX_FFE_ARGS((train_set)[2]), \
+ _TRAIN_SET_TX_FFE_ARGS((train_set)[3])
total: 2 errors, 1 warnings, 3 checks, 251 lines checked
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/selftests: Increase timeout in requests perf selftest
== Series Details == Series: drm/i915/selftests: Increase timeout in requests perf selftest URL : https://patchwork.freedesktop.org/series/95688/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10717 -> Patchwork_21307 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_21307 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_21307, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21307/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_21307: ### IGT changes ### Possible regressions * igt@i915_selftest@live@gem: - fi-pnv-d510:[PASS][1] -> [DMESG-FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10717/fi-pnv-d510/igt@i915_selftest@l...@gem.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21307/fi-pnv-d510/igt@i915_selftest@l...@gem.html Known issues Here are the changes found in Patchwork_21307 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_cs_nop@sync-fork-compute0: - fi-snb-2600:NOTRUN -> [SKIP][3] ([fdo#109271]) +17 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21307/fi-snb-2600/igt@amdgpu/amd_cs_...@sync-fork-compute0.html * igt@runner@aborted: - fi-pnv-d510:NOTRUN -> [FAIL][4] ([fdo#109271] / [i915#2403]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21307/fi-pnv-d510/igt@run...@aborted.html Possible fixes * igt@i915_selftest@live@hangcheck: - fi-snb-2600:[INCOMPLETE][5] ([i915#3921]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10717/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21307/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#2403]: https://gitlab.freedesktop.org/drm/intel/issues/2403 [i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921 Participating hosts (37 -> 19) -- Missing(18): fi-kbl-soraka fi-cml-u2 fi-kbl-7567u fi-bxt-dsi fi-bdw-5557u fi-jsl-1 fi-bsw-n3050 fi-glk-dsi fi-icl-u2 fi-bsw-cyan fi-kbl-7500u fi-cfl-8109u fi-skl-6700k2 fi-ehl-2 fi-bsw-kefka fi-bsw-nick fi-skl-6600u fi-kbl-r Build changes - * Linux: CI_DRM_10717 -> Patchwork_21307 CI-20190529: 20190529 CI_DRM_10717: 81e199c3565fe949631d8d08343bd89632a8ec0c @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6242: 721fd85ee95225ed5df322f7182bdfa9b86a3e68 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_21307: 5a3113b7da092778de3dbfe25fcb183fdf558b8f @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 5a3113b7da09 drm/i915/selftests: Increase timeout in requests perf selftest == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21307/index.html
Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/dp, drm/i915: Finish basic PWM support for VESA backlight helpers (rev8)
ok - CI on this failed like, multiple times last week - each time with something slightly different and pretty clearly not related, so I'm going to give this one last shot at retesting now that some time has passed - otherwise I'll just file some bugs. On Sat, 2021-10-09 at 01:58 +, Patchwork wrote: > Patch Details > Series:drm/dp, drm/i915: Finish basic PWM support for VESA backlight helpers > (rev8)URL:https://patchwork.freedesktop.org/series/95127/State:failure > Details:https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21296/index.html > CI Bug Log - changes from CI_DRM_10700_full -> > Patchwork_21296_fullSummaryFAILURE > Serious unknown changes coming with Patchwork_21296_full absolutely need to > be > verified manually. > If you think the reported changes have nothing to do with the changes > introduced in Patchwork_21296_full, please notify your bug team to allow > them > to document this new failure mode, which will reduce false positives in CI. > Possible new issuesHere are the unknown changes that may have been introduced > in > Patchwork_21296_full: > IGT changesPossible regressions * igt@i915_pm_dc@dc9-dpms:shard-tglb: NOTRUN > -> SKIPshard-iclb: NOTRUN -> >SKIP > * igt@i915_suspend@debugfs-reader:shard-kbl: PASS -> INCOMPLETE > Known issuesHere are the changes found in Patchwork_21296_full that come from > known > issues: > IGT changesIssues hit * igt@gem_ctx_isolation@preservation-s3@rcs0:shard-apl: > NOTRUN -> DMESG-WARN >([i915#180]) +1 similar issue > * igt@gem_ctx_persistence@legacy-engines-queued:shard-snb: NOTRUN -> SKIP >([fdo#109271] / [i915#1099]) +1 similar issue > * igt@gem_eio@unwedge-stress:shard-tglb: PASS -> TIMEOUT ([i915#2369] / >[i915#3063] / [i915#3648]) > * igt@gem_exec_fair@basic-deadline:shard-apl: NOTRUN -> FAIL ([i915#2846]) > * igt@gem_exec_fair@basic-none-share@rcs0:shard-kbl: PASS -> SKIP >([fdo#109271]) > * igt@gem_exec_fair@basic-none-solo@rcs0:shard-kbl: NOTRUN -> FAIL >([i915#2842]) > * igt@gem_exec_fair@basic-none@rcs0:shard-kbl: PASS -> FAIL ([i915#2842]) +1 >similar issue > * igt@gem_exec_fair@basic-pace-solo@rcs0:shard-iclb: NOTRUN -> FAIL >([i915#2842]) +2 similar issues > * igt@gem_exec_fair@basic-throttle@rcs0:shard-glk: NOTRUN -> FAIL >([i915#2842]) > * igt@gem_huc_copy@huc-copy:shard-apl: NOTRUN -> SKIP ([fdo#109271] / >[i915#2190]) > * igt@gem_pwrite@basic-exhaustion:shard-glk: NOTRUN -> WARN ([i915#2658]) > * igt@gem_pxp@reject-modify-context-protection-off-2:shard-iclb: NOTRUN -> >SKIP ([i915#4270]) > * igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-y-tiled:shard-glk: NOTRUN -> >SKIP ([fdo#109271]) +36 similar issues > * igt@gem_userptr_blits@dmabuf-sync:shard-kbl: NOTRUN -> SKIP ([fdo#109271] / >[i915#3323]) > * igt@gen9_exec_parse@batch-invalid-length:shard-iclb: NOTRUN -> SKIP >([i915#2856]) > * igt@i915_pm_dc@dc6-psr:shard-iclb: PASS -> FAIL ([i915#454]) > * igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp:shard-apl: NOTRUN -> SKIP >([fdo#109271] / [i915#1937]) > * igt@kms_big_fb@x-tiled-32bpp-rotate-180:shard-glk: NOTRUN -> DMESG-WARN >([i915#118]) > * igt@kms_big_fb@x-tiled-64bpp-rotate-270:shard-iclb: NOTRUN -> SKIP >([fdo#110725] / [fdo#111614]) > * igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip:shard-kbl: >NOTRUN -> SKIP ([fdo#109271] / [i915#3777]) +1 similar issue > * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip:shard-apl: >NOTRUN -> SKIP ([fdo#109271] / [i915#3777]) +1 similar issue > * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip-async- >flip:shard-kbl: NOTRUN -> SKIP ([fdo#109271]) +144 similar issues > * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0:shard-apl: NOTRUN -> >SKIP ([fdo#109271]) +272 similar issues > * igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_mc_ccs:shard-apl: NOTRUN >-> SKIP ([fdo#109271] / [i915#3886]) +19 similar issues > * igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc:shard- >skl: NOTRUN -> SKIP ([fdo#109271] / [i915#3886]) +1 similar issue > * igt@kms_ccs@pipe-c-crc-primary-rotation-180-y_tiled_gen12_mc_ccs:shard-kbl: >NOTRUN -> SKIP ([fdo#109271] / [i915#3886]) +6 similar issues > * igt@kms_chamelium@hdmi-hpd-for-each-pipe:shard-kbl: NOTRUN -> SKIP >([fdo#109271] / [fdo#111827]) +9 similar issues > * igt@kms_chamelium@vga-hpd:shard-apl: NOTRUN -> SKIP ([fdo#109271] / >[fdo#111827]) +26 similar issues > * igt@kms_color_chamelium@pipe-a-ctm-blue-to-red:shard-snb: NOTRUN -> SKIP >([fdo#109271] / [fdo#111827]) +16 similar issues > * igt@kms_color_chamelium@pipe-b-ctm-0-5:shard-glk: NOTRUN -> SKIP >([fdo#109271] / [fdo#111827]) +2 similar issues > * igt@kms_color_chamelium@pipe-d-ctm-red-to-blue:shard-skl: NOTRUN -> SKIP >([fdo#109271] / [fdo#111827]) +5 similar issues > * igt@kms_content_protection@legacy:shard-kbl: NOTRUN -> TIMEOUT >([i915#1319]) > * igt@kms_content_protection@lic:shard-apl:
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/dg2: Enabling 64k page size and flat ccs
== Series Details == Series: drm/i915/dg2: Enabling 64k page size and flat ccs URL : https://patchwork.freedesktop.org/series/95686/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10717 -> Patchwork_21306 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_21306 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_21306, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21306/index.html Known issues Here are the changes found in Patchwork_21306 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_cs_nop@sync-fork-compute0: - fi-snb-2600:NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21306/fi-snb-2600/igt@amdgpu/amd_cs_...@sync-fork-compute0.html Possible fixes * igt@i915_selftest@live@hangcheck: - fi-snb-2600:[INCOMPLETE][2] ([i915#3921]) -> [PASS][3] [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10717/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21306/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921 Participating hosts (37 -> 8) -- ERROR: It appears as if the changes made in Patchwork_21306 prevented too many machines from booting. Missing(29): fi-kbl-soraka fi-rkl-11600 fi-rkl-guc fi-bdw-gvtdvm fi-icl-u2 fi-apl-guc fi-icl-y fi-skl-6600u fi-cml-u2 fi-bxt-dsi fi-bdw-5557u fi-bsw-n3050 fi-glk-dsi fi-kbl-7500u fi-bsw-nick fi-skl-6700k2 fi-kbl-r fi-kbl-7567u fi-tgl-dsi fi-skl-guc fi-cfl-8700k fi-ehl-2 fi-jsl-1 fi-bsw-cyan fi-cfl-guc fi-kbl-guc fi-cfl-8109u fi-kbl-8809g fi-bsw-kefka Build changes - * Linux: CI_DRM_10717 -> Patchwork_21306 CI-20190529: 20190529 CI_DRM_10717: 81e199c3565fe949631d8d08343bd89632a8ec0c @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6242: 721fd85ee95225ed5df322f7182bdfa9b86a3e68 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_21306: 2b517348c6fb5167aa7a9fbbe59a548daef475fb @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 2b517348c6fb Doc/gpu/rfc/i915: i915 DG2 uAPI 749ff0849c0e drm/i915/uapi: document behaviour for DG2 64K support fcae6b137d64 drm/i915/gt: Clear compress metadata for Gen12.5 >= platforms 4a8a8a8bebf2 drm/i915/lmem: Enable lmem for platforms with Flat CCS 79dc6a059d71 drm/i915/xehpsdv: Add has_flat_ccs to device info 7062763f0800 drm/i915/xehpsdv: implement memory coloring 147ff265df2f drm/i915/selftests: account for min_alignment in GTT selftests b4c9e5a8a623 drm/i915: Add vm min alignment support a1536f2e5783 drm/i915/xehpsdv: support 64K GTT pages 6f36d1ed51b4 drm/i915/gtt/xehpsdv: move scratch page to system memory ead605ff4376 drm/i915: enforce min page size for scratch b2c0a0a180c4 drm/i915/xehpsdv: enforce min GTT alignment 70d612d1a872 drm/i915/xehpsdv: set min page-size to 64K 5bf9ba0e1d7d drm/i915: Add has_64k_pages flag == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21306/index.html
[Intel-gfx] [PATCH 1/2] drm/i915/dp: abstract intel_dp_lane_max_vswing_reached()
Add per-lane abstraction for max vswing reached to make follow-up
cleaner, as this one reverses the conditions.
v2: both conditions need to be true, reverse (Ville)
Cc: Ville Syrjälä
Signed-off-by: Jani Nikula
---
.../drm/i915/display/intel_dp_link_training.c | 42 +++
1 file changed, 25 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 1a943ae38a6b..1d4bcb91cd3b 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -515,29 +515,37 @@ intel_dp_update_link_train(struct intel_dp *intel_dp,
return ret == crtc_state->lane_count;
}
+/*
+ * FIXME: The DP spec is very confusing here, also the Link CTS spec seems to
+ * have self contradicting tests around this area.
+ *
+ * In lieu of better ideas let's just stop when we've reached the max supported
+ * vswing with its max pre-emphasis, which is either 2+1 or 3+0 depending on
+ * whether vswing level 3 is supported or not.
+ */
+static bool intel_dp_lane_max_vswing_reached(u8 train_set_lane)
+{
+ u8 v = (train_set_lane & DP_TRAIN_VOLTAGE_SWING_MASK) >>
+ DP_TRAIN_VOLTAGE_SWING_SHIFT;
+ u8 p = (train_set_lane & DP_TRAIN_PRE_EMPHASIS_MASK) >>
+ DP_TRAIN_PRE_EMPHASIS_SHIFT;
+
+ if ((train_set_lane & DP_TRAIN_MAX_SWING_REACHED) == 0)
+ return false;
+
+ if (v + p != 3)
+ return false;
+
+ return true;
+}
+
static bool intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp,
const struct intel_crtc_state
*crtc_state)
{
int lane;
- /*
-* FIXME: The DP spec is very confusing here, also the Link CTS
-* spec seems to have self contradicting tests around this area.
-*
-* In lieu of better ideas let's just stop when we've reached the
-* max supported vswing with its max pre-emphasis, which is either
-* 2+1 or 3+0 depending on whether vswing level 3 is supported or not.
-*/
for (lane = 0; lane < crtc_state->lane_count; lane++) {
- u8 v = (intel_dp->train_set[lane] &
DP_TRAIN_VOLTAGE_SWING_MASK) >>
- DP_TRAIN_VOLTAGE_SWING_SHIFT;
- u8 p = (intel_dp->train_set[lane] & DP_TRAIN_PRE_EMPHASIS_MASK)
>>
- DP_TRAIN_PRE_EMPHASIS_SHIFT;
-
- if ((intel_dp->train_set[lane] & DP_TRAIN_MAX_SWING_REACHED) ==
0)
- return false;
-
- if (v + p != 3)
+ if
(!intel_dp_lane_max_vswing_reached(intel_dp->train_set[lane]))
return false;
}
--
2.30.2
[Intel-gfx] [PATCH 2/2] drm/i915/dg2: update link training for 128b/132b
The 128b/132b channel coding link training uses more straightforward TX
FFE preset values. Reuse voltage tries and max vswing for retry logic.
The delays for 128b/132b are still all wrong, but this is regardless a
step forward.
v2: Fix UHBR rate checks, use intel_dp_is_uhbr() helper
v3:
- Rebase
- Modify intel_dp_adjust_request_changed() and
intel_dp_link_max_vswing_reached() to take 128b/132b into
account. (Ville)
v4:
- Train request printing for TX FFE (Ville)
- Log 8b/10b vs. 128b/132b (Ville)
- Add helper for per-lane max vswing / tx ffe (Ville)
- Name functions with tx_ffe/vswing instead of 128b132b/8b10b
Cc: Ville Syrjälä
Reviewed-by: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_ddi.c | 18 ++-
.../drm/i915/display/intel_dp_link_training.c | 152 ++
2 files changed, 134 insertions(+), 36 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 3f7bbeb3e3cd..59428ce4f8c1 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1338,13 +1338,20 @@ static int translate_signal_level(struct intel_dp
*intel_dp,
return 0;
}
-static int intel_ddi_dp_level(struct intel_dp *intel_dp, int lane)
+static int intel_ddi_dp_level(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state,
+ int lane)
{
u8 train_set = intel_dp->train_set[lane];
- u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
- DP_TRAIN_PRE_EMPHASIS_MASK);
- return translate_signal_level(intel_dp, signal_levels);
+ if (intel_dp_is_uhbr(crtc_state)) {
+ return train_set & DP_TX_FFE_PRESET_VALUE_MASK;
+ } else {
+ u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
+ DP_TRAIN_PRE_EMPHASIS_MASK);
+
+ return translate_signal_level(intel_dp, signal_levels);
+ }
}
int intel_ddi_level(struct intel_encoder *encoder,
@@ -1362,7 +1369,8 @@ int intel_ddi_level(struct intel_encoder *encoder,
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
level = intel_ddi_hdmi_level(encoder, trans);
else
- level = intel_ddi_dp_level(enc_to_intel_dp(encoder), lane);
+ level = intel_ddi_dp_level(enc_to_intel_dp(encoder), crtc_state,
+ lane);
if (drm_WARN_ON_ONCE(>drm, level >= n_entries))
level = n_entries - 1;
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 1d4bcb91cd3b..fda9f15ea7e9 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -304,11 +304,33 @@ static bool has_per_lane_signal_levels(struct intel_dp
*intel_dp,
return !intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy);
}
-static u8 intel_dp_get_lane_adjust_train(struct intel_dp *intel_dp,
-const struct intel_crtc_state
*crtc_state,
-enum drm_dp_phy dp_phy,
-const u8
link_status[DP_LINK_STATUS_SIZE],
-int lane)
+
+/* 128b/132b */
+static u8 intel_dp_get_lane_adjust_tx_ffe_preset(struct intel_dp *intel_dp,
+const struct intel_crtc_state
*crtc_state,
+enum drm_dp_phy dp_phy,
+const u8
link_status[DP_LINK_STATUS_SIZE],
+int lane)
+{
+ u8 tx_ffe = 0;
+
+ if (has_per_lane_signal_levels(intel_dp, dp_phy)) {
+ lane = min(lane, crtc_state->lane_count - 1);
+ tx_ffe = drm_dp_get_adjust_tx_ffe_preset(link_status, lane);
+ } else {
+ for (lane = 0; lane < crtc_state->lane_count; lane++)
+ tx_ffe = max(tx_ffe,
drm_dp_get_adjust_tx_ffe_preset(link_status, lane));
+ }
+
+ return tx_ffe;
+}
+
+/* 8b/10b */
+static u8 intel_dp_get_lane_adjust_vswing_preemph(struct intel_dp *intel_dp,
+ const struct intel_crtc_state
*crtc_state,
+ enum drm_dp_phy dp_phy,
+ const u8
link_status[DP_LINK_STATUS_SIZE],
+ int lane)
{
u8 v = 0;
u8 p = 0;
@@ -340,6 +362,20 @@ static u8 intel_dp_get_lane_adjust_train(struct intel_dp
*intel_dp,
return v | p;
}
+static u8 intel_dp_get_lane_adjust_train(struct intel_dp *intel_dp,
+
Re: [Intel-gfx] [PATCH 2/4] drm/i915/huc: Use i915_probe_error to report early HuC failures
On Mon, Oct 11, 2021 at 08:51:04PM +0530, Thanneeru Srinivasulu wrote:
> Replace DRM_ERROR with i915_probe_error to report early HuC failures.
>
> Signed-off-by: Thanneeru Srinivasulu
Reviewed-by: Matthew Brost
> ---
> drivers/gpu/drm/i915/gt/uc/intel_huc.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
> b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
> index ff4b6869b80b..ff0f5b9130c9 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
> @@ -179,7 +179,7 @@ int intel_huc_auth(struct intel_huc *huc)
> ret = intel_guc_auth_huc(guc,
>intel_guc_ggtt_offset(guc, huc->rsa_data));
> if (ret) {
> - DRM_ERROR("HuC: GuC did not ack Auth request %d\n", ret);
> + i915_probe_error(gt->i915, "HuC: GuC did not ack Auth request
> %d\n", ret);
> goto fail;
> }
>
> @@ -190,7 +190,7 @@ int intel_huc_auth(struct intel_huc *huc)
> huc->status.value,
> 2, 50, NULL);
> if (ret) {
> - DRM_ERROR("HuC: Firmware not verified %d\n", ret);
> + i915_probe_error(gt->i915, "HuC: Firmware not verified %d\n",
> ret);
> goto fail;
> }
>
> --
> 2.25.1
>
Re: [Intel-gfx] [PATCH 1/4] drm/i915/huc: Use i915_probe_error to report early CTB failures
On Mon, Oct 11, 2021 at 08:51:03PM +0530, Thanneeru Srinivasulu wrote: > Replace DRM_ERROR with CT_PROBE_ERROR to report early CTB failures. > > Signed-off-by: Thanneeru Srinivasulu Reviewed-by: Matthew Brost > --- > drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c > b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c > index 0a3504bc0b61..83764db0fd6d 100644 > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c > @@ -191,8 +191,8 @@ static int ct_register_buffer(struct intel_guc_ct *ct, > u32 type, > err = guc_action_register_ct_buffer(ct_to_guc(ct), type, > desc_addr, buff_addr, size); > if (unlikely(err)) > - CT_ERROR(ct, "Failed to register %s buffer (%pe)\n", > - guc_ct_buffer_type_to_str(type), ERR_PTR(err)); > + CT_PROBE_ERROR(ct, "Failed to register %s buffer (%pe)\n", > +guc_ct_buffer_type_to_str(type), ERR_PTR(err)); > return err; > } > > -- > 2.25.1 >
Re: [Intel-gfx] [PATCH 3/4] drm/i915/guc: Inject probe errors for MMIO send
On Mon, Oct 11, 2021 at 08:51:05PM +0530, Thanneeru Srinivasulu wrote: > Injecting probe errors -ENXIO for MMIO send. > > Signed-off-by: Thanneeru Srinivasulu Reviewed-by: Matthew Brost > --- > drivers/gpu/drm/i915/gt/uc/intel_guc.c | 4 > 1 file changed, 4 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c > b/drivers/gpu/drm/i915/gt/uc/intel_guc.c > index 8f8182bf7c11..490d66712afc 100644 > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c > @@ -403,6 +403,10 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32 > *request, u32 len, > int i; > int ret; > > + ret = i915_inject_probe_error(i915, -ENXIO); > + if (ret) > + return ret; > + > GEM_BUG_ON(!len); > GEM_BUG_ON(len > guc->send_regs.count); > > -- > 2.25.1 >
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/dg2: Enabling 64k page size and flat ccs
== Series Details == Series: drm/i915/dg2: Enabling 64k page size and flat ccs URL : https://patchwork.freedesktop.org/series/95686/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_reset.c:1392:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/i915_perf.c:1442:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1496:15: warning: memset with byte count of 16777216 +./include/asm-generic/bitops/find.h:112:45: warning: shift count is negative (-262080) +./include/asm-generic/bitops/find.h:32:31: warning: shift count is negative (-262080) +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
Re: [Intel-gfx] [PATCH 4/4] drm/i915/guc: Inject probe errors for CT send
On Mon, Oct 11, 2021 at 08:51:06PM +0530, Thanneeru Srinivasulu wrote:
> Inject probe errors -ENXIO, -EBUSY for CT send.
>
> Signed-off-by: Thanneeru Srinivasulu
> ---
> drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 8
> 1 file changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> index 83764db0fd6d..8ffef3abd3da 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> @@ -765,6 +765,14 @@ int intel_guc_ct_send(struct intel_guc_ct *ct, const u32
> *action, u32 len,
> u32 status = ~0; /* undefined */
> int ret;
>
> + ret = i915_inject_probe_error(ct_to_i915(ct), -ENXIO);
> + if (ret)
> + return ret;
> +
I don't see where -ENXIO is returned during an error that we handle
unless I am missing something. If we don't return -ENXIO anywhere else I
don't think we need to inject this error.
Matt
> + ret = i915_inject_probe_error(ct_to_i915(ct), -EBUSY);
> + if (ret)
> + return ret;
> +
> if (unlikely(!ct->enabled)) {
> struct intel_guc *guc = ct_to_guc(ct);
> struct intel_uc *uc = container_of(guc, struct intel_uc, guc);
> --
> 2.25.1
>
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dg2: Enabling 64k page size and flat ccs
== Series Details == Series: drm/i915/dg2: Enabling 64k page size and flat ccs URL : https://patchwork.freedesktop.org/series/95686/ State : warning == Summary == $ dim checkpatch origin/drm-tip 5bf9ba0e1d7d drm/i915: Add has_64k_pages flag 70d612d1a872 drm/i915/xehpsdv: set min page-size to 64K b2c0a0a180c4 drm/i915/xehpsdv: enforce min GTT alignment ead605ff4376 drm/i915: enforce min page size for scratch 6f36d1ed51b4 drm/i915/gtt/xehpsdv: move scratch page to system memory a1536f2e5783 drm/i915/xehpsdv: support 64K GTT pages b4c9e5a8a623 drm/i915: Add vm min alignment support 147ff265df2f drm/i915/selftests: account for min_alignment in GTT selftests -:108: WARNING:DEEP_INDENTATION: Too many leading tabs - consider code refactoring #108: FILE: drivers/gpu/drm/i915/selftests/i915_gem_gtt.c:456: + if (offset < hole_start + aligned_size) -:120: WARNING:DEEP_INDENTATION: Too many leading tabs - consider code refactoring #120: FILE: drivers/gpu/drm/i915/selftests/i915_gem_gtt.c:480: + if (offset + aligned_size > hole_end) -:138: WARNING:DEEP_INDENTATION: Too many leading tabs - consider code refactoring #138: FILE: drivers/gpu/drm/i915/selftests/i915_gem_gtt.c:496: + if (offset < hole_start + aligned_size) -:150: WARNING:DEEP_INDENTATION: Too many leading tabs - consider code refactoring #150: FILE: drivers/gpu/drm/i915/selftests/i915_gem_gtt.c:519: + if (offset + aligned_size > hole_end) -:168: WARNING:DEEP_INDENTATION: Too many leading tabs - consider code refactoring #168: FILE: drivers/gpu/drm/i915/selftests/i915_gem_gtt.c:535: + if (offset < hole_start + aligned_size) -:180: WARNING:DEEP_INDENTATION: Too many leading tabs - consider code refactoring #180: FILE: drivers/gpu/drm/i915/selftests/i915_gem_gtt.c:559: + if (offset + aligned_size > hole_end) -:198: WARNING:DEEP_INDENTATION: Too many leading tabs - consider code refactoring #198: FILE: drivers/gpu/drm/i915/selftests/i915_gem_gtt.c:575: + if (offset < hole_start + aligned_size) -:210: WARNING:DEEP_INDENTATION: Too many leading tabs - consider code refactoring #210: FILE: drivers/gpu/drm/i915/selftests/i915_gem_gtt.c:598: + if (offset + aligned_size > hole_end) total: 0 errors, 8 warnings, 0 checks, 297 lines checked 7062763f0800 drm/i915/xehpsdv: implement memory coloring 79dc6a059d71 drm/i915/xehpsdv: Add has_flat_ccs to device info 4a8a8a8bebf2 drm/i915/lmem: Enable lmem for platforms with Flat CCS fcae6b137d64 drm/i915/gt: Clear compress metadata for Gen12.5 >= platforms 749ff0849c0e drm/i915/uapi: document behaviour for DG2 64K support 2b517348c6fb Doc/gpu/rfc/i915: i915 DG2 uAPI -:14: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #14: new file mode 100644 -:19: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1 #19: FILE: Documentation/gpu/rfc/i915_dg2.rst:1: + total: 0 errors, 2 warnings, 0 checks, 56 lines checked
[Intel-gfx] [PATCH] drm/i915/selftests: Increase timeout in requests perf selftest
perf_parallel_engines is micro benchmark to test i915 request scheduling. The test creates a thread per physical engine and submits NOP requests and waits the requests to complete in a loop. In execlists mode this works perfectly fine as powerful CPU has enough cores to feed each engine and process the CSBs. With GuC submission the uC gets overwhelmed as all threads feed into a single CTB channel and the GuC gets bombarded with CSBs as contexts are immediately switched in and out on the engines due to the zero runtime of the requests. When the GuC is overwhelmed scheduling of contexts is unfair due to the nature of the GuC scheduling algorithm. This behavior is understood and deemed acceptable as this micro benchmark isn't close to real world use case. Increasing the timeout of wait period for requests to complete. This makes the test understand that is ok for contexts to get starved in this scenario. A future patch / cleanup may just delete these micro benchmark tests as they basically mean nothing. We care about real workloads not made up ones. Signed-off-by: Matthew Brost --- drivers/gpu/drm/i915/selftests/i915_request.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/selftests/i915_request.c b/drivers/gpu/drm/i915/selftests/i915_request.c index d67710d10615..6496671a113c 100644 --- a/drivers/gpu/drm/i915/selftests/i915_request.c +++ b/drivers/gpu/drm/i915/selftests/i915_request.c @@ -2805,7 +2805,7 @@ static int p_sync0(void *arg) i915_request_add(rq); err = 0; - if (i915_request_wait(rq, 0, HZ / 5) < 0) + if (i915_request_wait(rq, 0, HZ) < 0) err = -ETIME; i915_request_put(rq); if (err) @@ -2876,7 +2876,7 @@ static int p_sync1(void *arg) i915_request_add(rq); err = 0; - if (prev && i915_request_wait(prev, 0, HZ / 5) < 0) + if (prev && i915_request_wait(prev, 0, HZ) < 0) err = -ETIME; i915_request_put(prev); prev = rq; -- 2.32.0
Re: [Intel-gfx] [PATCH 14/14] Doc/gpu/rfc/i915: i915 DG2 uAPI
> -Original Message- > From: C, Ramalingam > Sent: Monday, October 11, 2021 9:12 AM > To: dri-devel ; intel-gfx g...@lists.freedesktop.org> > Cc: Daniel Vetter ; Auld, Matthew > ; Tang, CQ ; Hellstrom, > Thomas ; C, Ramalingam > ; Daniel Vetter > Subject: [PATCH 14/14] Doc/gpu/rfc/i915: i915 DG2 uAPI > > Details of the new features getting added as part of DG2 enabling and their > implicit impact on the uAPI. > > Signed-off-by: Ramalingam C > cc: Daniel Vetter > cc: Matthew Auld > --- > Documentation/gpu/rfc/i915_dg2.rst | 47 > ++ > Documentation/gpu/rfc/index.rst| 3 ++ > 2 files changed, 50 insertions(+) > create mode 100644 Documentation/gpu/rfc/i915_dg2.rst > > diff --git a/Documentation/gpu/rfc/i915_dg2.rst > b/Documentation/gpu/rfc/i915_dg2.rst > new file mode 100644 > index ..a83ca26cd758 > --- /dev/null > +++ b/Documentation/gpu/rfc/i915_dg2.rst > @@ -0,0 +1,47 @@ > + > +I915 DG2 RFC Section > + > + > +Upstream plan > += > +Plan to upstream the DG2 enabling is: > + > +* Merge basic HW enabling for DG2(Still without pciid) > +* Merge the 64k support for lmem > +* Merge the flat CCS enabling patches > +* Add the pciid for DG2 and enable the DG2 in CI > + > + > +64K page support for lmem > += > +On DG2 hw, local-memory supports minimum GTT page size of 64k only. 4k > is not supported anymore. > + > +DG2 hw dont support the 64k(lmem) and 4k(smem) pages in the same > ppgtt > +Page table. Refer the struct drm_i915_gem_create_ext for the implication > of handling the 64k page size. > + > +.. kernel-doc:: include/uapi/drm/i915_drm.h > +:functions: drm_i915_gem_create_ext > + > + > +flat CCS support for lmem > += > +Gen 12+ devices support 3D surfaces compression and compression > +formats. This is accomplished by an additional compression control state > (CCS) stored for each surface. General introduction, OK. > + > +Gen 12 devices(TGL and DG1) stores compression state in a separate region > of memory. > +It is managed by userspace and has an associated set of userspace > +managed page tables used by hardware for address translation. I don't know the purpose of this paragraph, do we need to mention TGL/DG1? This is "Gen 12", not "Gen 12+" in first paragraph. > + > +In Gen 12.5 devices(XEXPSDV and DG2) Flat CCS is introduced to replace > +the userspace managed AUX pagetable with the flat indexed region of > +device memory for storing the compression state Because this is DG2 document, do we need to mention XeHP SDV? > + > +GOP Driver steals a chunk of memory for the CCS surface corresponding > +to the entire range of local memory. The memory required for the CCS of > +the entire local memory is > +1/256 of the main local memory. The Gop driver will also program a > +secure register (XEHPSDV_FLAT_CCS_BASE_ADDR 0x4910) with this address > value. I think it is not necessary to say the CCS base register. This is internal detail. > + > +So the Total local memory available for driver allocation is Total lmem > +size - CCS data size Well, we need to minus the GTT, lmem stolen (DG2 only), and WOPCM. Maybe just say, total local memory available is smaller because of other reserved regions. > + > +Flat CCS data needs to be cleared when a lmem object is allocated. And > +CCS data can be copied in and out of CCS region through > XY_CTRL_SURF_COPY_BLT. OK. --CQ > diff --git a/Documentation/gpu/rfc/index.rst > b/Documentation/gpu/rfc/index.rst index 91e93a705230..afb320ed4028 > 100644 > --- a/Documentation/gpu/rfc/index.rst > +++ b/Documentation/gpu/rfc/index.rst > @@ -20,6 +20,9 @@ host such documentation: > > i915_gem_lmem.rst > > +.. toctree:: > +i915_dg2.rst > + > .. toctree:: > > i915_scheduler.rst > -- > 2.20.1
Re: [Intel-gfx] [PATCH] lib/stackdepot: allow optional init and stack_table allocation by kvmalloc()
On 10/7/21 13:01, Marco Elver wrote:
> On Thu, Oct 07, 2021 at 11:58AM +0200, Vlastimil Babka wrote:
> [...]
>> - Add a CONFIG_STACKDEPOT_ALWAYS_INIT flag to keep using the current
>> well-defined point of allocation as part of mem_init(). Make CONFIG_KASAN
>> select this flag.
>> - Other users have to call stack_depot_init() as part of their own init when
>> it's determined that stack depot will actually be used. This may depend on
>> both config and runtime conditions. Convert current users which are
>> page_owner and several in the DRM subsystem. Same will be done for SLUB
>> later.
>> - Because the init might now be called after the boot-time memblock
>> allocation
>> has given all memory to the buddy allocator, change stack_depot_init() to
>> allocate stack_table with kvmalloc() when memblock is no longer available.
>> Also handle allocation failure by disabling stackdepot (could have
>> theoretically happened even with memblock allocation previously), and don't
>> unnecessarily align the memblock allocation to its own size anymore.
> ...
>> Hi, I'd appreciate review of the DRM parts - namely that I've got correctly
>> that stack_depot_init() is called from the proper init functions and iff
>> stack_depot_save() is going to be used later. Thanks!
>
> For ease of review between stackdepot and DRM changes, I thought it'd be
> nice to split into 2 patches, but not sure it'll work, because you're
> changing the semantics of the normal STACKDEPOT.
Yeah, that's why it's a single patch. As the DRM parts are clearly separated
to their files, I think review should be fine.
> One option would be to flip it around, and instead have
> STACKDEPOT_LAZY_INIT, but that seems counter-intuitive if the majority
> of STACKDEPOT users are LAZY_INIT users.
Agree.
> On the other hand, the lazy initialization mode you're introducing
> requires an explicit stack_depot_init() call somewhere and isn't as
> straightforward as before.
>
> Not sure what is best. My intuition tells me STACKDEPOT_LAZY_INIT would
> be safer as it's a deliberate opt-in to the lazy initialization
> behaviour.
I think it should be fine with ALWAYS_INIT. There are not many stackdepot
users being added, and anyone developing a new one will very quickly find
out if they forget to call stack_depot_init()?
> Preferences?
>
> [...]
>> --- a/drivers/gpu/drm/drm_mm.c
>> +++ b/drivers/gpu/drm/drm_mm.c
>> @@ -980,6 +980,10 @@ void drm_mm_init(struct drm_mm *mm, u64 start, u64 size)
>> add_hole(>head_node);
>>
>> mm->scan_active = 0;
>> +
>> +#ifdef CONFIG_DRM_DEBUG_MM
>> +stack_depot_init();
>> +#endif
>
> DRM_DEBUG_MM implies STACKDEPOT. Not sure what is more readable to drm
> maintainers, but perhaps it'd be nicer to avoid the #ifdef here, and
> instead just keep the no-op version of stack_depot_init() in
> . I don't have a strong preference.
Hm, but in case STACKDEPOT is also selected by something else (e.g.
CONFIG_PAGE_OWNER) which uses lazy init but isn't enabled on boot, then
without #ifdef CONFIG_DRM_DEBUG_MM above, this code would call a
stack_depot_init() (that's not a no-op) even in case it's not going to be
using it, so not what we want to achieve.
But it could be changed to use IS_ENABLED() if that's preferred by DRM folks.
BTW it's possible that there won't be any DRM review because this failed to
apply:
https://patchwork.freedesktop.org/series/95549/
DRM folks, any hint how to indicate that the base was next-20211001?
>> @@ -30,13 +40,4 @@ int stack_depot_snprint(depot_stack_handle_t handle, char
>> *buf, size_t size,
>>
>> void stack_depot_print(depot_stack_handle_t stack);
>>
>> -#ifdef CONFIG_STACKDEPOT
>> -int stack_depot_init(void);
>> -#else
>> -static inline int stack_depot_init(void)
>> -{
>> -return 0;
>> -}
>> -#endif /* CONFIG_STACKDEPOT */
>> -
>
> Could we avoid the IS_ENABLED() in init/main.c by adding a wrapper here:
>
> +#ifdef CONFIG_STACKDEPOT_ALWAYS_INIT
> +static inline int stack_depot_early_init(void) { return
> stack_depot_init(); }
> +#else
> +static inline int stack_depot_early_init(void) { return 0; }
> +#endif /* CONFIG_STACKDEPOT_ALWAYS_INIT */
We could, but it's a wrapper made for only a single caller...
>> #endif
>> diff --git a/init/main.c b/init/main.c
>> index ee4d3e1b3eb9..b6a5833d98f5 100644
>> --- a/init/main.c
>> +++ b/init/main.c
>> @@ -844,7 +844,8 @@ static void __init mm_init(void)
>> init_mem_debugging_and_hardening();
>> kfence_alloc_pool();
>> report_meminit();
>> -stack_depot_init();
>> +if (IS_ENABLED(CONFIG_STACKDEPOT_ALWAYS_INIT))
>> +stack_depot_init();
>
> I'd push the decision of when to call this into via
> wrapper stack_depot_early_init().
No strong preferrences, if you think it's worth it.
>> mem_init();
>> mem_init_print_info();
>> /* page_owner must be initialized after buddy is ready */
>> diff --git a/lib/Kconfig b/lib/Kconfig
>> index
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/guc: Inject probe errors for MMIO send, CT send
== Series Details == Series: drm/i915/guc: Inject probe errors for MMIO send, CT send URL : https://patchwork.freedesktop.org/series/95683/ State : success == Summary == CI Bug Log - changes from CI_DRM_10716 -> Patchwork_21305 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21305/index.html Known issues Here are the changes found in Patchwork_21305 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@cs-sdma: - fi-cfl-8109u: NOTRUN -> [SKIP][1] ([fdo#109271]) +28 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21305/fi-cfl-8109u/igt@amdgpu/amd_ba...@cs-sdma.html - fi-kbl-7500u: NOTRUN -> [SKIP][2] ([fdo#109271]) +30 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21305/fi-kbl-7500u/igt@amdgpu/amd_ba...@cs-sdma.html * igt@amdgpu/amd_basic@memory-alloc: - fi-cml-u2: NOTRUN -> [SKIP][3] ([fdo#109315]) +17 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21305/fi-cml-u2/igt@amdgpu/amd_ba...@memory-alloc.html * igt@amdgpu/amd_basic@query-info: - fi-bsw-kefka: NOTRUN -> [SKIP][4] ([fdo#109271]) +32 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21305/fi-bsw-kefka/igt@amdgpu/amd_ba...@query-info.html - fi-tgl-1115g4: NOTRUN -> [SKIP][5] ([fdo#109315]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21305/fi-tgl-1115g4/igt@amdgpu/amd_ba...@query-info.html * igt@amdgpu/amd_cs_nop@nop-compute0: - fi-ilk-650: NOTRUN -> [SKIP][6] ([fdo#109271]) +35 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21305/fi-ilk-650/igt@amdgpu/amd_cs_...@nop-compute0.html * igt@amdgpu/amd_cs_nop@nop-gfx0: - fi-tgl-1115g4: NOTRUN -> [SKIP][7] ([fdo#109315] / [i915#2575]) +16 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21305/fi-tgl-1115g4/igt@amdgpu/amd_cs_...@nop-gfx0.html * igt@fbdev@write: - fi-bdw-gvtdvm: NOTRUN -> [SKIP][8] ([fdo#109271]) +5 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21305/fi-bdw-gvtdvm/igt@fb...@write.html * igt@gem_exec_fence@basic-busy@bcs0: - fi-kbl-soraka: NOTRUN -> [SKIP][9] ([fdo#109271]) +9 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21305/fi-kbl-soraka/igt@gem_exec_fence@basic-b...@bcs0.html - fi-cml-u2: NOTRUN -> [SKIP][10] ([i915#1208]) +1 similar issue [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21305/fi-cml-u2/igt@gem_exec_fence@basic-b...@bcs0.html * igt@gem_exec_suspend@basic-s0: - fi-bdw-gvtdvm: NOTRUN -> [INCOMPLETE][11] ([i915#146]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21305/fi-bdw-gvtdvm/igt@gem_exec_susp...@basic-s0.html * igt@gem_exec_suspend@basic-s3: - fi-bwr-2160:NOTRUN -> [SKIP][12] ([fdo#109271]) +60 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21305/fi-bwr-2160/igt@gem_exec_susp...@basic-s3.html - fi-tgl-1115g4: NOTRUN -> [FAIL][13] ([i915#1888]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21305/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s3.html * igt@gem_huc_copy@huc-copy: - fi-cml-u2: NOTRUN -> [SKIP][14] ([i915#2190]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21305/fi-cml-u2/igt@gem_huc_c...@huc-copy.html - fi-kbl-soraka: NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#2190]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21305/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html - fi-glk-dsi: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#2190]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21305/fi-glk-dsi/igt@gem_huc_c...@huc-copy.html - fi-kbl-7500u: NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#2190]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21305/fi-kbl-7500u/igt@gem_huc_c...@huc-copy.html - fi-tgl-1115g4: NOTRUN -> [SKIP][18] ([i915#2190]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21305/fi-tgl-1115g4/igt@gem_huc_c...@huc-copy.html - fi-cfl-8109u: NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#2190]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21305/fi-cfl-8109u/igt@gem_huc_c...@huc-copy.html * igt@i915_pm_backlight@basic-brightness: - fi-tgl-1115g4: NOTRUN -> [SKIP][20] ([i915#1155]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21305/fi-tgl-1115g4/igt@i915_pm_backli...@basic-brightness.html * igt@i915_selftest@live@gt_heartbeat: - fi-bsw-nick:[PASS][21] -> [DMESG-FAIL][22] ([i915#541]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10716/fi-bsw-nick/igt@i915_selftest@live@gt_heartbeat.html [22]:
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v8,1/8] drm/i915/gem: Break out some shmem backend utils
== Series Details == Series: series starting with [v8,1/8] drm/i915/gem: Break out some shmem backend utils URL : https://patchwork.freedesktop.org/series/95677/ State : success == Summary == CI Bug Log - changes from CI_DRM_10716 -> Patchwork_21304 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21304/index.html Known issues Here are the changes found in Patchwork_21304 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@cs-sdma: - fi-cfl-8109u: NOTRUN -> [SKIP][1] ([fdo#109271]) +28 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21304/fi-cfl-8109u/igt@amdgpu/amd_ba...@cs-sdma.html - fi-kbl-7500u: NOTRUN -> [SKIP][2] ([fdo#109271]) +30 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21304/fi-kbl-7500u/igt@amdgpu/amd_ba...@cs-sdma.html * igt@amdgpu/amd_basic@memory-alloc: - fi-cml-u2: NOTRUN -> [SKIP][3] ([fdo#109315]) +17 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21304/fi-cml-u2/igt@amdgpu/amd_ba...@memory-alloc.html * igt@amdgpu/amd_basic@query-info: - fi-bsw-kefka: NOTRUN -> [SKIP][4] ([fdo#109271]) +32 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21304/fi-bsw-kefka/igt@amdgpu/amd_ba...@query-info.html - fi-tgl-1115g4: NOTRUN -> [SKIP][5] ([fdo#109315]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21304/fi-tgl-1115g4/igt@amdgpu/amd_ba...@query-info.html * igt@amdgpu/amd_cs_nop@nop-compute0: - fi-ilk-650: NOTRUN -> [SKIP][6] ([fdo#109271]) +35 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21304/fi-ilk-650/igt@amdgpu/amd_cs_...@nop-compute0.html * igt@amdgpu/amd_cs_nop@nop-gfx0: - fi-tgl-1115g4: NOTRUN -> [SKIP][7] ([fdo#109315] / [i915#2575]) +16 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21304/fi-tgl-1115g4/igt@amdgpu/amd_cs_...@nop-gfx0.html * igt@fbdev@write: - fi-bdw-gvtdvm: NOTRUN -> [SKIP][8] ([fdo#109271]) +5 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21304/fi-bdw-gvtdvm/igt@fb...@write.html * igt@gem_exec_fence@basic-busy@bcs0: - fi-kbl-soraka: NOTRUN -> [SKIP][9] ([fdo#109271]) +2 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21304/fi-kbl-soraka/igt@gem_exec_fence@basic-b...@bcs0.html - fi-cml-u2: NOTRUN -> [SKIP][10] ([i915#1208]) +1 similar issue [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21304/fi-cml-u2/igt@gem_exec_fence@basic-b...@bcs0.html * igt@gem_exec_suspend@basic-s0: - fi-kbl-soraka: NOTRUN -> [INCOMPLETE][11] ([i915#4221]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21304/fi-kbl-soraka/igt@gem_exec_susp...@basic-s0.html - fi-bdw-gvtdvm: NOTRUN -> [INCOMPLETE][12] ([i915#146]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21304/fi-bdw-gvtdvm/igt@gem_exec_susp...@basic-s0.html - fi-tgl-1115g4: NOTRUN -> [FAIL][13] ([i915#1888]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21304/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s0.html * igt@gem_exec_suspend@basic-s3: - fi-bwr-2160:NOTRUN -> [SKIP][14] ([fdo#109271]) +60 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21304/fi-bwr-2160/igt@gem_exec_susp...@basic-s3.html * igt@gem_huc_copy@huc-copy: - fi-cml-u2: NOTRUN -> [SKIP][15] ([i915#2190]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21304/fi-cml-u2/igt@gem_huc_c...@huc-copy.html - fi-glk-dsi: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#2190]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21304/fi-glk-dsi/igt@gem_huc_c...@huc-copy.html - fi-kbl-7500u: NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#2190]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21304/fi-kbl-7500u/igt@gem_huc_c...@huc-copy.html - fi-tgl-1115g4: NOTRUN -> [SKIP][18] ([i915#2190]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21304/fi-tgl-1115g4/igt@gem_huc_c...@huc-copy.html - fi-cfl-8109u: NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#2190]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21304/fi-cfl-8109u/igt@gem_huc_c...@huc-copy.html * igt@i915_pm_backlight@basic-brightness: - fi-tgl-1115g4: NOTRUN -> [SKIP][20] ([i915#1155]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21304/fi-tgl-1115g4/igt@i915_pm_backli...@basic-brightness.html * igt@i915_selftest@live@requests: - fi-pnv-d510:[PASS][21] -> [DMESG-FAIL][22] ([i915#4140]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10716/fi-pnv-d510/igt@i915_selftest@l...@requests.html [22]:
[Intel-gfx] [PATCH 14/14] Doc/gpu/rfc/i915: i915 DG2 uAPI
Details of the new features getting added as part of DG2 enabling and their implicit impact on the uAPI. Signed-off-by: Ramalingam C cc: Daniel Vetter cc: Matthew Auld --- Documentation/gpu/rfc/i915_dg2.rst | 47 ++ Documentation/gpu/rfc/index.rst| 3 ++ 2 files changed, 50 insertions(+) create mode 100644 Documentation/gpu/rfc/i915_dg2.rst diff --git a/Documentation/gpu/rfc/i915_dg2.rst b/Documentation/gpu/rfc/i915_dg2.rst new file mode 100644 index ..a83ca26cd758 --- /dev/null +++ b/Documentation/gpu/rfc/i915_dg2.rst @@ -0,0 +1,47 @@ + +I915 DG2 RFC Section + + +Upstream plan += +Plan to upstream the DG2 enabling is: + +* Merge basic HW enabling for DG2(Still without pciid) +* Merge the 64k support for lmem +* Merge the flat CCS enabling patches +* Add the pciid for DG2 and enable the DG2 in CI + + +64K page support for lmem += +On DG2 hw, local-memory supports minimum GTT page size of 64k only. 4k is not supported anymore. + +DG2 hw dont support the 64k(lmem) and 4k(smem) pages in the same ppgtt Page table. Refer the +struct drm_i915_gem_create_ext for the implication of handling the 64k page size. + +.. kernel-doc:: include/uapi/drm/i915_drm.h +:functions: drm_i915_gem_create_ext + + +flat CCS support for lmem += +Gen 12+ devices support 3D surfaces compression and compression formats. This is +accomplished by an additional compression control state (CCS) stored for each surface. + +Gen 12 devices(TGL and DG1) stores compression state in a separate region of memory. +It is managed by userspace and has an associated set of userspace managed page tables +used by hardware for address translation. + +In Gen 12.5 devices(XEXPSDV and DG2) Flat CCS is introduced to replace the userspace +managed AUX pagetable with the flat indexed region of device memory for storing the +compression state + +GOP Driver steals a chunk of memory for the CCS surface corresponding to the entire +range of local memory. The memory required for the CCS of the entire local memory is +1/256 of the main local memory. The Gop driver will also program a secure register +(XEHPSDV_FLAT_CCS_BASE_ADDR 0x4910) with this address value. + +So the Total local memory available for driver allocation is Total lmem size - CCS data size + +Flat CCS data needs to be cleared when a lmem object is allocated. And CCS data can +be copied in and out of CCS region through XY_CTRL_SURF_COPY_BLT. diff --git a/Documentation/gpu/rfc/index.rst b/Documentation/gpu/rfc/index.rst index 91e93a705230..afb320ed4028 100644 --- a/Documentation/gpu/rfc/index.rst +++ b/Documentation/gpu/rfc/index.rst @@ -20,6 +20,9 @@ host such documentation: i915_gem_lmem.rst +.. toctree:: +i915_dg2.rst + .. toctree:: i915_scheduler.rst -- 2.20.1
[Intel-gfx] [PATCH 13/14] drm/i915/uapi: document behaviour for DG2 64K support
From: Matthew Auld
On discrete platforms like DG2, we need to support a minimum page size
of 64K when dealing with device local-memory. This is quite tricky for
various reasons, so try to document the new implicit uapi for this.
Signed-off-by: Matthew Auld
Signed-off-by: Ramalingam C
---
include/uapi/drm/i915_drm.h | 61 ++---
1 file changed, 56 insertions(+), 5 deletions(-)
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index aa2a7eccfb94..d62e8b7ed8b6 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -1118,10 +1118,16 @@ struct drm_i915_gem_exec_object2 {
/**
* When the EXEC_OBJECT_PINNED flag is specified this is populated by
* the user with the GTT offset at which this object will be pinned.
+*
* When the I915_EXEC_NO_RELOC flag is specified this must contain the
* presumed_offset of the object.
+*
* During execbuffer2 the kernel populates it with the value of the
* current GTT offset of the object, for future presumed_offset writes.
+*
+* See struct drm_i915_gem_create_ext for the rules when dealing with
+* alignment restrictions with I915_MEMORY_CLASS_DEVICE, on devices with
+* minimum page sizes, like DG2.
*/
__u64 offset;
@@ -3001,11 +3007,56 @@ struct drm_i915_gem_create_ext {
*
* The (page-aligned) allocated size for the object will be returned.
*
-* Note that for some devices we have might have further minimum
-* page-size restrictions(larger than 4K), like for device local-memory.
-* However in general the final size here should always reflect any
-* rounding up, if for example using the
I915_GEM_CREATE_EXT_MEMORY_REGIONS
-* extension to place the object in device local-memory.
+* On discrete platforms, starting from DG2, we have to contend with GTT
+* page size restrictions when dealing with I915_MEMORY_CLASS_DEVICE
+* objects. Specifically the hardware only supports 64K or larger GTT
+* page sizes for such memory. The kernel will already ensure that all
+* I915_MEMORY_CLASS_DEVICE memory is allocated using 64K or larger page
+* sizes underneath.
+*
+* Note that the returned size here will always reflect any required
+* rounding up done by the kernel, i.e 4K will now become 64K on devices
+* such as DG2. The GTT alignment will also need be at least 64K for
+* such objects.
+*
+* Note that due to how the hardware implements 64K GTT page support, we
+* have some further complications:
+*
+* 1.) The entire PDE(which covers a 2M virtual address range), must
+* contain only 64K PTEs, i.e mixing 4K and 64K PTEs in the same
+* PDE is forbidden by the hardware.
+*
+* 2.) We still need to support 4K PTEs for I915_MEMORY_CLASS_SYSTEM
+* objects.
+*
+* To handle the above the kernel implements a memory coloring scheme to
+* prevent userspace from mixing I915_MEMORY_CLASS_DEVICE and
+* I915_MEMORY_CLASS_SYSTEM objects in the same PDE. If the kernel is
+* ever unable to evict the required pages for the given PDE(different
+* color) when inserting the object into the GTT then it will simply
+* fail the request.
+*
+* Since userspace needs to manage the GTT address space themselves,
+* special care is needed to ensure this doesn't happen. The simplest
+* scheme is to simply align and round up all I915_MEMORY_CLASS_DEVICE
+* objects to 2M, which avoids any issues here. At the very least this
+* is likely needed for objects that can be placed in both
+* I915_MEMORY_CLASS_DEVICE and I915_MEMORY_CLASS_SYSTEM, to avoid
+* potential issues when the kernel needs to migrate the object behind
+* the scenes, since that might also involve evicting other objects.
+*
+* To summarise the GTT rules, on platforms like DG2:
+*
+* 1.) All objects that can be placed in I915_MEMORY_CLASS_DEVICE must
+* have 64K alignment. The kernel will reject this otherwise.
+*
+* 2.) All I915_MEMORY_CLASS_DEVICE objects must never be placed in
+* the same PDE with other I915_MEMORY_CLASS_SYSTEM objects. The
+* kernel will reject this otherwise.
+*
+* 3.) Objects that can be placed in both I915_MEMORY_CLASS_DEVICE and
+* I915_MEMORY_CLASS_SYSTEM should probably be aligned and padded out
+* to 2M.
*/
__u64 size;
/**
--
2.20.1
[Intel-gfx] [PATCH 12/14] drm/i915/gt: Clear compress metadata for Gen12.5 >= platforms
From: Ayaz A Siddiqui
Gen12.5+ devices support Flat CCS which reserved a portion of the device
memory to store compression metadata, during the clearing of device memory
buffer object we also need to clear the associated CCS buffer.
Flat CCS memory can not be directly accessed by S/W.
Address of CCS buffer associated main BO is automatically calculated
by device itself. KMD/UMD can only access this buffer indirectly using
XY_CTRL_SURF_COPY_BLT cmd via the address of device memory buffer.
Cc: CQ Tang
Signed-off-by: Ayaz A Siddiqui
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 14 +++
drivers/gpu/drm/i915/gt/intel_migrate.c | 120 ++-
2 files changed, 131 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
index f8253012d166..07bf5a1753bd 100644
--- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
+++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
@@ -203,6 +203,20 @@
#define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
#define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2)
+#define XY_CTRL_SURF_INSTR_SIZE5
+#define MI_FLUSH_DW_SIZE 3
+#define XY_CTRL_SURF_COPY_BLT ((2 << 29) | (0x48 << 22) | 3)
+#define SRC_ACCESS_TYPE_SHIFT21
+#define DST_ACCESS_TYPE_SHIFT20
+#define CCS_SIZE_SHIFT 8
+#define XY_CTRL_SURF_MOCS_SHIFT 25
+#define NUM_CCS_BYTES_PER_BLOCK 256
+#define NUM_CCS_BLKS_PER_XFER1024
+#define INDIRECT_ACCESS 0
+#define DIRECT_ACCESS1
+#define MI_FLUSH_LLC BIT(9)
+#define MI_FLUSH_CCS BIT(16)
+
#define COLOR_BLT_CMD (2 << 29 | 0x40 << 22 | (5 - 2))
#define XY_COLOR_BLT_CMD (2 << 29 | 0x50 << 22)
#define SRC_COPY_BLT_CMD (2 << 29 | 0x43 << 22)
diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c
b/drivers/gpu/drm/i915/gt/intel_migrate.c
index afb1cce9a352..0bed01750884 100644
--- a/drivers/gpu/drm/i915/gt/intel_migrate.c
+++ b/drivers/gpu/drm/i915/gt/intel_migrate.c
@@ -17,6 +17,7 @@ struct insert_pte_data {
};
#define CHUNK_SZ SZ_8M /* ~1ms at 8GiB/s preemption delay */
+#define GET_CCS_SIZE(i915, size) (HAS_FLAT_CCS(i915) ? (size) >> 8 : 0)
static bool engine_supports_migration(struct intel_engine_cs *engine)
{
@@ -490,15 +491,104 @@ intel_context_migrate_copy(struct intel_context *ce,
return err;
}
-static int emit_clear(struct i915_request *rq, int size, u32 value)
+static inline u32 *i915_flush_dw(u32 *cmd, u64 dst, u32 flags)
+{
+ /* Mask the 3 LSB to use the PPGTT address space */
+ *cmd++ = MI_FLUSH_DW | flags;
+ *cmd++ = lower_32_bits(dst);
+ *cmd++ = upper_32_bits(dst);
+
+ return cmd;
+}
+
+static u32 calc_ctrl_surf_instr_size(struct drm_i915_private *i915, int size)
+{
+ u32 num_cmds, num_blks, total_size;
+
+ if (!GET_CCS_SIZE(i915, size))
+ return 0;
+
+ /*
+* XY_CTRL_SURF_COPY_BLT transfers CCS in 256 byte
+* blocks. one XY_CTRL_SURF_COPY_BLT command can
+* trnasfer upto 1024 blocks.
+*/
+ num_blks = (GET_CCS_SIZE(i915, size) +
+ (NUM_CCS_BYTES_PER_BLOCK - 1)) >> 8;
+ num_cmds = (num_blks + (NUM_CCS_BLKS_PER_XFER - 1)) >> 10;
+ total_size = (XY_CTRL_SURF_INSTR_SIZE) * num_cmds;
+
+ /*
+* We need to add a flush before and after
+* XY_CTRL_SURF_COPY_BLT
+*/
+ total_size += 2 * MI_FLUSH_DW_SIZE;
+ return total_size;
+}
+
+static u32 *_i915_ctrl_surf_copy_blt(u32 *cmd, u64 src_addr, u64 dst_addr,
+u8 src_mem_access, u8 dst_mem_access,
+int src_mocs, int dst_mocs,
+u16 num_ccs_blocks)
+{
+ int i = num_ccs_blocks;
+
+ /*
+* The XY_CTRL_SURF_COPY_BLT instruction is used to copy the CCS
+* data in and out of the CCS region.
+*
+* We can copy at most 1024 blocks of 256 bytes using one
+* XY_CTRL_SURF_COPY_BLT instruction.
+*
+* In case we need to copy more than 1024 blocks, we need to add
+* another instruction to the same batch buffer.
+*
+* 1024 blocks of 256 bytes of CCS represent a total 256KB of CCS.
+*
+* 256 KB of CCS represents 256 * 256 KB = 64 MB of LMEM.
+*/
+ do {
+ /*
+* We use logical AND with 1023 since the size field
+* takes values which is in the range of 0 - 1023
+*/
+ *cmd++ = ((XY_CTRL_SURF_COPY_BLT) |
+ (src_mem_access << SRC_ACCESS_TYPE_SHIFT) |
+ (dst_mem_access << DST_ACCESS_TYPE_SHIFT) |
+ (((i - 1) & 1023) << CCS_SIZE_SHIFT));
[Intel-gfx] [PATCH 11/14] drm/i915/lmem: Enable lmem for platforms with Flat CCS
From: Abdiel Janulgue
A portion of device memory is reserved for Flat CCS so usable
device memory will be reduced by size of Flat CCS. Size of
Flat CCS is specified in “XEHPSDV_FLAT_CCS_BASE_ADDR”.
So to get effective device memory we need to subtract
total device memory by Flat CCS memory size.
Cc: Matthew Auld
Signed-off-by: Abdiel Janulgue
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/gt/intel_gt.c | 19 ++
drivers/gpu/drm/i915/gt/intel_gt.h | 1 +
drivers/gpu/drm/i915/gt/intel_region_lmem.c | 22 +++--
drivers/gpu/drm/i915/i915_reg.h | 3 +++
4 files changed, 43 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index 1cb1948ac959..fd82ebee8724 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -900,6 +900,25 @@ u32 intel_gt_read_register_fw(struct intel_gt *gt,
i915_reg_t reg)
return intel_uncore_read_fw(gt->uncore, reg);
}
+u32 intel_gt_read_register(struct intel_gt *gt, i915_reg_t reg)
+{
+ int type;
+ u8 sliceid, subsliceid;
+
+ for (type = 0; type < NUM_STEERING_TYPES; type++) {
+ if (intel_gt_reg_needs_read_steering(gt, reg, type)) {
+ intel_gt_get_valid_steering(gt, type, ,
+ );
+ return intel_uncore_read_with_mcr_steering(gt->uncore,
+ reg,
+ sliceid,
+ subsliceid);
+ }
+ }
+
+ return intel_uncore_read(gt->uncore, reg);
+}
+
void intel_gt_info_print(const struct intel_gt_info *info,
struct drm_printer *p)
{
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h
b/drivers/gpu/drm/i915/gt/intel_gt.h
index 74e771871a9b..24b78398a587 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt.h
@@ -84,6 +84,7 @@ static inline bool intel_gt_needs_read_steering(struct
intel_gt *gt,
}
u32 intel_gt_read_register_fw(struct intel_gt *gt, i915_reg_t reg);
+u32 intel_gt_read_register(struct intel_gt *gt, i915_reg_t reg);
void intel_gt_info_print(const struct intel_gt_info *info,
struct drm_printer *p);
diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
index 073d28d96669..d1f88beb26fe 100644
--- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
+++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
@@ -201,8 +201,26 @@ static struct intel_memory_region *setup_lmem(struct
intel_gt *gt)
if (!IS_DGFX(i915))
return ERR_PTR(-ENODEV);
- /* Stolen starts from GSMBASE on DG1 */
- lmem_size = intel_uncore_read64(uncore, GEN12_GSMBASE);
+ if (HAS_FLAT_CCS(i915)) {
+ u64 tile_stolen, flat_ccs_base_addr_reg, flat_ccs_base;
+
+ lmem_size = pci_resource_len(pdev, 2);
+ flat_ccs_base_addr_reg = intel_gt_read_register(gt,
XEHPSDV_FLAT_CCS_BASE_ADDR);
+ flat_ccs_base = (flat_ccs_base_addr_reg >>
XEHPSDV_CCS_BASE_SHIFT) * SZ_64K;
+ tile_stolen = lmem_size - flat_ccs_base;
+
+ /* If the FLAT_CCS_BASE_ADDR register is not populated, flag an
error */
+ if (tile_stolen == lmem_size)
+ DRM_ERROR("CCS_BASE_ADDR register did not have expected
value\n");
+
+ lmem_size -= tile_stolen;
+ } else {
+ /* Stolen starts from GSMBASE without CCS */
+ lmem_size = intel_uncore_read64(>uncore, GEN12_GSMBASE);
+ if (GEM_WARN_ON(lmem_size > pci_resource_len(pdev, 2)))
+ return ERR_PTR(-ENODEV);
+ }
+
io_start = pci_resource_start(pdev, 2);
if (GEM_WARN_ON(lmem_size > pci_resource_len(pdev, 2)))
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a897f4abea0c..5a14e0ca9d4f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -12480,6 +12480,9 @@ enum skl_power_gate {
#define GEN12_GSMBASE _MMIO(0x108100)
#define GEN12_DSMBASE _MMIO(0x1080C0)
+#define XEHPSDV_FLAT_CCS_BASE_ADDR _MMIO(0x4910)
+#define XEHPSDV_CCS_BASE_SHIFT 8
+
/* gamt regs */
#define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4)
#define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW 0x67F1427F /* max/min for
LRA1/2 */
--
2.20.1
[Intel-gfx] [PATCH 10/14] drm/i915/xehpsdv: Add has_flat_ccs to device info
From: CQ Tang
Gen12+ devices support 3D surface (buffer) compression and various
compression formats. This is accomplished by an additional compression
control state (CCS) stored for each surface.
Gen 12 devices(TGL family and DG1) stores compression states in a separate
region of memory. It is managed by user-space and has an associated set of
user-space managed page tables used by hardware for address translation.
In Gen12.5 devices(XEHPSDV, DG2, etc), there is a new feature introduced
i.e Flat CCS. It replaced AUX page tables with a flat indexed region of
device memory for storing compression states.
Cc: Joonas Lahtinen
Cc: Matthew Auld
Signed-off-by: CQ Tang
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_pci.c | 1 +
drivers/gpu/drm/i915/intel_device_info.h | 1 +
3 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a16fde38a252..57948e0ee48b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1721,6 +1721,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i))
#define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM)
+#define HAS_FLAT_CCS(dev_priv) (INTEL_INFO(dev_priv)->has_flat_ccs)
+
#define HAS_GT_UC(dev_priv)(INTEL_INFO(dev_priv)->has_gt_uc)
#define HAS_POOLED_EU(dev_priv)(INTEL_INFO(dev_priv)->has_pooled_eu)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 8ef484a23652..68367b505dc4 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -991,6 +991,7 @@ static const struct intel_device_info adl_p_info = {
XE_HP_PAGE_SIZES, \
.dma_mask_size = 46, \
.has_64bit_reloc = 1, \
+ .has_flat_ccs = 1, \
.has_global_mocs = 1, \
.has_gt_uc = 1, \
.has_llc = 1, \
diff --git a/drivers/gpu/drm/i915/intel_device_info.h
b/drivers/gpu/drm/i915/intel_device_info.h
index dd453b96af19..87ee1d86d2ac 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -126,6 +126,7 @@ enum intel_ppgtt_type {
func(has_64k_pages); \
func(gpu_reset_clobbers_display); \
func(has_reset_engine); \
+ func(has_flat_ccs); \
func(has_global_mocs); \
func(has_gt_uc); \
func(has_l3_dpf); \
--
2.20.1
[Intel-gfx] [PATCH 09/14] drm/i915/xehpsdv: implement memory coloring
From: Matthew Auld
The basic idea is that each 2M block(page-table) has a color, depending
on if the page-table is occupied by LMEM objects(64K) or SMEM
objects(4K), where our goal is to prevent mixing 64K and 4K GTT pages in
the page-table, which is not supported by the HW.
Signed-off-by: Matthew Auld
Signed-off-by: Stuart Summers
Signed-off-by: Ramalingam C
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
---
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 16 ++
drivers/gpu/drm/i915/gt/intel_gtt.h | 6
drivers/gpu/drm/i915/i915_gem_evict.c | 17 ++
drivers/gpu/drm/i915/i915_vma.c | 46 +++
4 files changed, 71 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
index fec0f20f1b93..666745adbe93 100644
--- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
@@ -464,6 +464,19 @@ gen8_ppgtt_insert_pte(struct i915_ppgtt *ppgtt,
return idx;
}
+static void xehpsdv_ppgtt_color_adjust(const struct drm_mm_node *node,
+ unsigned long color,
+ u64 *start,
+ u64 *end)
+{
+ if (i915_node_color_differs(node, color))
+ *start = round_up(*start, SZ_2M);
+
+ node = list_next_entry(node, node_list);
+ if (i915_node_color_differs(node, color))
+ *end = round_down(*end, SZ_2M);
+}
+
static void
xehpsdv_ppgtt_insert_huge(struct i915_vma *vma,
struct sgt_dma *iter,
@@ -901,6 +914,9 @@ struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt,
ppgtt->vm.alloc_scratch_dma = alloc_pt_dma;
}
+ if (HAS_64K_PAGES(gt->i915))
+ ppgtt->vm.mm.color_adjust = xehpsdv_ppgtt_color_adjust;
+
err = gen8_init_scratch(>vm);
if (err)
goto err_free;
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h
b/drivers/gpu/drm/i915/gt/intel_gtt.h
index 20101eef4c95..34696acde342 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
@@ -397,6 +397,12 @@ i915_vm_has_cache_coloring(struct i915_address_space *vm)
return i915_is_ggtt(vm) && vm->mm.color_adjust;
}
+static inline bool
+i915_vm_has_memory_coloring(struct i915_address_space *vm)
+{
+ return !i915_is_ggtt(vm) && vm->mm.color_adjust;
+}
+
static inline struct i915_ggtt *
i915_vm_to_ggtt(struct i915_address_space *vm)
{
diff --git a/drivers/gpu/drm/i915/i915_gem_evict.c
b/drivers/gpu/drm/i915/i915_gem_evict.c
index 2b73ddb11c66..006bf4924c24 100644
--- a/drivers/gpu/drm/i915/i915_gem_evict.c
+++ b/drivers/gpu/drm/i915/i915_gem_evict.c
@@ -292,6 +292,13 @@ int i915_gem_evict_for_node(struct i915_address_space *vm,
/* Always look at the page afterwards to avoid the end-of-GTT */
end += I915_GTT_PAGE_SIZE;
+ } else if (i915_vm_has_memory_coloring(vm)) {
+ /*
+* Expand the search the cover the page-table boundries, in
+* case we need to flip the color of the page-table(s).
+*/
+ start = round_down(start, SZ_2M);
+ end = round_up(end, SZ_2M);
}
GEM_BUG_ON(start >= end);
@@ -321,6 +328,16 @@ int i915_gem_evict_for_node(struct i915_address_space *vm,
if (node->color == target->color)
continue;
}
+ } else if (i915_vm_has_memory_coloring(vm)) {
+ if (node->start + node->size <= target->start) {
+ if (node->color == target->color)
+ continue;
+ }
+
+ if (node->start >= target->start + target->size) {
+ if (node->color == target->color)
+ continue;
+ }
}
if (i915_vma_is_pinned(vma)) {
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index 1ea1fa08efdf..2664d3ab49b9 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -585,6 +585,10 @@ bool i915_gem_valid_gtt_space(struct i915_vma *vma,
unsigned long color)
struct drm_mm_node *node = >node;
struct drm_mm_node *other;
+ /* Only valid to be called on an already inserted vma */
+ GEM_BUG_ON(!drm_mm_node_allocated(node));
+ GEM_BUG_ON(list_empty(>node_list));
+
/*
* On some machines we have to be careful when putting differing types
* of snoopable memory together to avoid the prefetcher crossing memory
@@ -592,22 +596,34 @@ bool i915_gem_valid_gtt_space(struct i915_vma *vma,
unsigned long color)
* these constraints apply and set the drm_mm.color_adjust
*
[Intel-gfx] [PATCH 08/14] drm/i915/selftests: account for min_alignment in GTT selftests
From: Matthew Auld
We need to support vm->min_alignment > 4K, depending
on the vm itself and the type of object we are inserting.
With this in mind update the GTT selftests to take this
into account.
Signed-off-by: Matthew Auld
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 96 ---
1 file changed, 63 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
index 46f4236039a9..fdb4bf88293b 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
@@ -237,6 +237,8 @@ static int lowlevel_hole(struct i915_address_space *vm,
u64 hole_start, u64 hole_end,
unsigned long end_time)
{
+ const unsigned int min_alignment =
+ i915_vm_min_alignment(vm, INTEL_MEMORY_SYSTEM);
I915_RND_STATE(seed_prng);
struct i915_vma *mock_vma;
unsigned int size;
@@ -250,9 +252,10 @@ static int lowlevel_hole(struct i915_address_space *vm,
I915_RND_SUBSTATE(prng, seed_prng);
struct drm_i915_gem_object *obj;
unsigned int *order, count, n;
- u64 hole_size;
+ u64 hole_size, aligned_size;
- hole_size = (hole_end - hole_start) >> size;
+ aligned_size = max_t(u32, ilog2(min_alignment), size);
+ hole_size = (hole_end - hole_start) >> aligned_size;
if (hole_size > KMALLOC_MAX_SIZE / sizeof(u32))
hole_size = KMALLOC_MAX_SIZE / sizeof(u32);
count = hole_size >> 1;
@@ -273,8 +276,8 @@ static int lowlevel_hole(struct i915_address_space *vm,
}
GEM_BUG_ON(!order);
- GEM_BUG_ON(count * BIT_ULL(size) > vm->total);
- GEM_BUG_ON(hole_start + count * BIT_ULL(size) > hole_end);
+ GEM_BUG_ON(count * BIT_ULL(aligned_size) > vm->total);
+ GEM_BUG_ON(hole_start + count * BIT_ULL(aligned_size) >
hole_end);
/* Ignore allocation failures (i.e. don't report them as
* a test failure) as we are purposefully allocating very
@@ -297,10 +300,10 @@ static int lowlevel_hole(struct i915_address_space *vm,
}
for (n = 0; n < count; n++) {
- u64 addr = hole_start + order[n] * BIT_ULL(size);
+ u64 addr = hole_start + order[n] *
BIT_ULL(aligned_size);
intel_wakeref_t wakeref;
- GEM_BUG_ON(addr + BIT_ULL(size) > vm->total);
+ GEM_BUG_ON(addr + BIT_ULL(aligned_size) > vm->total);
if (igt_timeout(end_time,
"%s timed out before %d/%d\n",
@@ -343,7 +346,7 @@ static int lowlevel_hole(struct i915_address_space *vm,
}
mock_vma->pages = obj->mm.pages;
- mock_vma->node.size = BIT_ULL(size);
+ mock_vma->node.size = BIT_ULL(aligned_size);
mock_vma->node.start = addr;
with_intel_runtime_pm(vm->gt->uncore->rpm, wakeref)
@@ -354,7 +357,7 @@ static int lowlevel_hole(struct i915_address_space *vm,
i915_random_reorder(order, count, );
for (n = 0; n < count; n++) {
- u64 addr = hole_start + order[n] * BIT_ULL(size);
+ u64 addr = hole_start + order[n] *
BIT_ULL(aligned_size);
intel_wakeref_t wakeref;
GEM_BUG_ON(addr + BIT_ULL(size) > vm->total);
@@ -398,8 +401,10 @@ static int fill_hole(struct i915_address_space *vm,
{
const u64 hole_size = hole_end - hole_start;
struct drm_i915_gem_object *obj;
+ const unsigned int min_alignment =
+ i915_vm_min_alignment(vm, INTEL_MEMORY_SYSTEM);
const unsigned long max_pages =
- min_t(u64, ULONG_MAX - 1, hole_size/2 >> PAGE_SHIFT);
+ min_t(u64, ULONG_MAX - 1, (hole_size / 2) >>
ilog2(min_alignment));
const unsigned long max_step = max(int_sqrt(max_pages), 2UL);
unsigned long npages, prime, flags;
struct i915_vma *vma;
@@ -440,14 +445,17 @@ static int fill_hole(struct i915_address_space *vm,
offset = p->offset;
list_for_each_entry(obj, , st_link) {
+ u64 aligned_size =
round_up(obj->base.size,
+
min_alignment);
+
vma = i915_vma_instance(obj, vm, NULL);
if (IS_ERR(vma))
continue;
[Intel-gfx] [PATCH 07/14] drm/i915: Add vm min alignment support
From: Bommu Krishnaiah
Replace the hard coded 4K alignment value with vm->min_alignment.
Cc: Wilson Chris P
Signed-off-by: Bommu Krishnaiah
Signed-off-by: Ramalingam C
---
.../i915/gem/selftests/i915_gem_client_blt.c | 23 ---
drivers/gpu/drm/i915/gt/intel_gtt.c | 9
drivers/gpu/drm/i915/gt/intel_gtt.h | 9
3 files changed, 33 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
index ecbcbb86ae1e..30c8d64df3b8 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
@@ -32,6 +32,7 @@ struct tiled_blits {
struct blit_buffer scratch;
struct i915_vma *batch;
u64 hole;
+ u64 align;
u32 width;
u32 height;
};
@@ -403,14 +404,21 @@ tiled_blits_create(struct intel_engine_cs *engine, struct
rnd_state *prng)
goto err_free;
}
- hole_size = 2 * PAGE_ALIGN(WIDTH * HEIGHT * 4);
+ t->align = I915_GTT_PAGE_SIZE_2M; /* XXX worst case, derive from vm! */
+ t->align = max(t->align,
+ i915_vm_min_alignment(t->ce->vm, INTEL_MEMORY_LOCAL));
+ t->align = max(t->align,
+ i915_vm_min_alignment(t->ce->vm, INTEL_MEMORY_SYSTEM));
+
+ hole_size = 2 * round_up(WIDTH * HEIGHT * 4, t->align);
hole_size *= 2; /* room to maneuver */
- hole_size += 2 * I915_GTT_MIN_ALIGNMENT;
+ hole_size += 2 * t->align; /* padding on either side */
mutex_lock(>ce->vm->mutex);
memset(, 0, sizeof(hole));
err = drm_mm_insert_node_in_range(>ce->vm->mm, ,
- hole_size, 0, I915_COLOR_UNEVICTABLE,
+ hole_size, t->align,
+ I915_COLOR_UNEVICTABLE,
0, U64_MAX,
DRM_MM_INSERT_BEST);
if (!err)
@@ -421,7 +429,7 @@ tiled_blits_create(struct intel_engine_cs *engine, struct
rnd_state *prng)
goto err_put;
}
- t->hole = hole.start + I915_GTT_MIN_ALIGNMENT;
+ t->hole = hole.start + t->align;
pr_info("Using hole at %llx\n", t->hole);
err = tiled_blits_create_buffers(t, WIDTH, HEIGHT, prng);
@@ -448,7 +456,7 @@ static void tiled_blits_destroy(struct tiled_blits *t)
static int tiled_blits_prepare(struct tiled_blits *t,
struct rnd_state *prng)
{
- u64 offset = PAGE_ALIGN(t->width * t->height * 4);
+ u64 offset = round_up(t->width * t->height * 4, t->align);
u32 *map;
int err;
int i;
@@ -479,8 +487,7 @@ static int tiled_blits_prepare(struct tiled_blits *t,
static int tiled_blits_bounce(struct tiled_blits *t, struct rnd_state *prng)
{
- u64 offset =
- round_up(t->width * t->height * 4, 2 * I915_GTT_MIN_ALIGNMENT);
+ u64 offset = round_up(t->width * t->height * 4, 2 * t->align);
int err;
/* We want to check position invariant tiling across GTT eviction */
@@ -493,7 +500,7 @@ static int tiled_blits_bounce(struct tiled_blits *t, struct
rnd_state *prng)
/* Reposition so that we overlap the old addresses, and slightly off */
err = tiled_blit(t,
->buffers[2], t->hole + I915_GTT_MIN_ALIGNMENT,
+>buffers[2], t->hole + t->align,
>buffers[1], t->hole + 3 * offset / 2);
if (err)
return err;
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c
b/drivers/gpu/drm/i915/gt/intel_gtt.c
index 56fbd37a6b54..4743921b7638 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
@@ -216,6 +216,15 @@ void i915_address_space_init(struct i915_address_space
*vm, int subclass)
GEM_BUG_ON(!vm->total);
drm_mm_init(>mm, 0, vm->total);
+
+ memset64(vm->min_alignment, I915_GTT_MIN_ALIGNMENT,
+ARRAY_SIZE(vm->min_alignment));
+
+ if (HAS_64K_PAGES(vm->i915)) {
+ vm->min_alignment[INTEL_MEMORY_LOCAL] = I915_GTT_PAGE_SIZE_64K;
+ vm->min_alignment[INTEL_MEMORY_STOLEN_LOCAL] =
I915_GTT_PAGE_SIZE_64K;
+ }
+
vm->mm.head_node.color = I915_COLOR_UNEVICTABLE;
INIT_LIST_HEAD(>bound_list);
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h
b/drivers/gpu/drm/i915/gt/intel_gtt.h
index 6d0233ffae17..20101eef4c95 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
@@ -28,6 +28,8 @@
#include "gt/intel_reset.h"
#include "i915_selftest.h"
#include "i915_vma_types.h"
+#include "i915_params.h"
+#include "intel_memory_region.h"
#define I915_GFP_ALLOW_FAIL (GFP_KERNEL | __GFP_RETRY_MAYFAIL | __GFP_NOWARN)
@@ -224,6 +226,7 @@ struct
[Intel-gfx] [PATCH 06/14] drm/i915/xehpsdv: support 64K GTT pages
From: Matthew Auld
XEHPSDV optimises 64K GTT pages for local-memory, since everything
should be allocated at 64K granularity. We say goodbye to sparse
entries, and instead get a compact 256B page-table for 64K pages,
which should be more cache friendly. 4K pages for local-memory
are no longer supported by the HW.
Signed-off-by: Matthew Auld
Signed-off-by: Stuart Summers
Signed-off-by: Ramalingam C
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
---
.../gpu/drm/i915/gem/selftests/huge_pages.c | 61 ++
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 106 +-
drivers/gpu/drm/i915/gt/intel_gtt.h | 3 +
drivers/gpu/drm/i915/gt/intel_ppgtt.c | 1 +
4 files changed, 168 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
index 41d0680f3bd7..9c2ffa4090f1 100644
--- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
@@ -1451,6 +1451,66 @@ static int igt_ppgtt_sanity_check(void *arg)
return err;
}
+static int igt_ppgtt_compact(void *arg)
+{
+ struct i915_gem_context *ctx = arg;
+ struct drm_i915_private *i915 = ctx->i915;
+ struct drm_i915_gem_object *obj;
+ int err;
+
+ /*
+* Simple test to catch issues with compact 64K pages -- since the pt is
+* compacted to 256B that gives us 32 entries per pt, however since the
+* backing page for the pt is 4K, any extra entries we might incorrectly
+* write out should be ignored by the HW. If ever hit such a case this
+* test should catch it since some of our writes would land in scratch.
+*/
+
+ if (!HAS_64K_PAGES(i915)) {
+ pr_info("device lacks compact 64K page support, skipping\n");
+ return 0;
+ }
+
+ if (!HAS_LMEM(i915)) {
+ pr_info("device lacks LMEM support, skipping\n");
+ return 0;
+ }
+
+ /* We want the range to cover multiple page-table boundaries. */
+ obj = i915_gem_object_create_lmem(i915, SZ_4M, 0);
+ if (IS_ERR(obj))
+ return err;
+
+ err = i915_gem_object_pin_pages_unlocked(obj);
+ if (err)
+ goto out_put;
+
+ if (obj->mm.page_sizes.phys < I915_GTT_PAGE_SIZE_64K) {
+ pr_info("LMEM compact unable to allocate huge-page(s)\n");
+ goto out_unpin;
+ }
+
+ /*
+* Disable 2M GTT pages by forcing the page-size to 64K for the GTT
+* insertion.
+*/
+ obj->mm.page_sizes.sg = I915_GTT_PAGE_SIZE_64K;
+
+ err = igt_write_huge(ctx, obj);
+ if (err)
+ pr_err("LMEM compact write-huge failed\n");
+
+out_unpin:
+ i915_gem_object_unpin_pages(obj);
+out_put:
+ i915_gem_object_put(obj);
+
+ if (err == -ENOMEM)
+ err = 0;
+
+ return err;
+}
+
static int igt_tmpfs_fallback(void *arg)
{
struct i915_gem_context *ctx = arg;
@@ -1681,6 +1741,7 @@ int i915_gem_huge_page_live_selftests(struct
drm_i915_private *i915)
SUBTEST(igt_tmpfs_fallback),
SUBTEST(igt_ppgtt_smoke_huge),
SUBTEST(igt_ppgtt_sanity_check),
+ SUBTEST(igt_ppgtt_compact),
};
struct i915_gem_context *ctx;
struct i915_address_space *vm;
diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
index 6bff6bf1a450..fec0f20f1b93 100644
--- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
@@ -233,6 +233,8 @@ static u64 __gen8_ppgtt_clear(struct i915_address_space *
const vm,
start, end, lvl);
} else {
unsigned int count;
+ unsigned int pte = gen8_pd_index(start, 0);
+ unsigned int num_ptes;
u64 *vaddr;
count = gen8_pt_count(start, end);
@@ -242,10 +244,18 @@ static u64 __gen8_ppgtt_clear(struct i915_address_space *
const vm,
atomic_read(>used));
GEM_BUG_ON(!count || count >= atomic_read(>used));
+ num_ptes = count;
+ if (pt->is_compact) {
+ GEM_BUG_ON(num_ptes % 16);
+ GEM_BUG_ON(pte % 16);
+ num_ptes /= 16;
+ pte /= 16;
+ }
+
vaddr = px_vaddr(pt);
- memset64(vaddr + gen8_pd_index(start, 0),
+ memset64(vaddr + pte,
vm->scratch[0]->encode,
-count);
+num_ptes);
atomic_sub(count, >used);
start +=
[Intel-gfx] [PATCH 05/14] drm/i915/gtt/xehpsdv: move scratch page to system memory
From: Matthew Auld
On some platforms the hw has dropped support for 4K GTT pages when
dealing with LMEM, and due to the design of 64K GTT pages in the hw, we
can only mark the *entire* page-table as operating in 64K GTT mode,
since the enable bit is still on the pde, and not the pte. And since we
we still need to allow 4K GTT pages for SMEM objects, we can't have a
"normal" 4K page-table with scratch pointing to LMEM, since that's
undefined from the hw pov. The simplest solution is to just move the 64K
scratch page to SMEM on such platforms and call it a day, since that
should work for all configurations.
Signed-off-by: Matthew Auld
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 1 +
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 23 +--
drivers/gpu/drm/i915/gt/intel_ggtt.c | 2 ++
drivers/gpu/drm/i915/gt/intel_gtt.c | 2 +-
drivers/gpu/drm/i915/gt/intel_gtt.h | 2 ++
drivers/gpu/drm/i915/selftests/mock_gtt.c | 2 ++
6 files changed, 29 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
index 890191f286e3..49e7651d764a 100644
--- a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
@@ -440,6 +440,7 @@ struct i915_ppgtt *gen6_ppgtt_create(struct intel_gt *gt)
ppgtt->base.vm.cleanup = gen6_ppgtt_cleanup;
ppgtt->base.vm.alloc_pt_dma = alloc_pt_dma;
+ ppgtt->base.vm.alloc_scratch_dma = alloc_pt_dma;
ppgtt->base.vm.pte_encode = ggtt->vm.pte_encode;
ppgtt->base.pd = __alloc_pd(I915_PDES);
diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
index 037a9a6e4889..6bff6bf1a450 100644
--- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
@@ -777,10 +777,29 @@ struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt,
*/
ppgtt->vm.has_read_only = !IS_GRAPHICS_VER(gt->i915, 11, 12);
- if (HAS_LMEM(gt->i915))
+ if (HAS_LMEM(gt->i915)) {
ppgtt->vm.alloc_pt_dma = alloc_pt_lmem;
- else
+
+ /*
+* On some platforms the hw has dropped support for 4K GTT pages
+* when dealing with LMEM, and due to the design of 64K GTT
+* pages in the hw, we can only mark the *entire* page-table as
+* operating in 64K GTT mode, since the enable bit is still on
+* the pde, and not the pte. And since we still need to allow
+* 4K GTT pages for SMEM objects, we can't have a "normal" 4K
+* page-table with scratch pointing to LMEM, since that's
+* undefined from the hw pov. The simplest solution is to just
+* move the 64K scratch page to SMEM on such platforms and call
+* it a day, since that should work for all configurations.
+*/
+ if (HAS_64K_PAGES(gt->i915))
+ ppgtt->vm.alloc_scratch_dma = alloc_pt_dma;
+ else
+ ppgtt->vm.alloc_scratch_dma = alloc_pt_lmem;
+ } else {
ppgtt->vm.alloc_pt_dma = alloc_pt_dma;
+ ppgtt->vm.alloc_scratch_dma = alloc_pt_dma;
+ }
err = gen8_init_scratch(>vm);
if (err)
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c
b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index f17383e76eb7..289316007029 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -1077,6 +1077,7 @@ static int gen6_gmch_probe(struct i915_ggtt *ggtt)
ggtt->vm.total = (size / sizeof(gen6_pte_t)) * I915_GTT_PAGE_SIZE;
ggtt->vm.alloc_pt_dma = alloc_pt_dma;
+ ggtt->vm.alloc_scratch_dma = alloc_pt_dma;
ggtt->vm.clear_range = nop_clear_range;
if (!HAS_FULL_PPGTT(i915) || intel_scanout_needs_vtd_wa(i915))
@@ -1129,6 +1130,7 @@ static int i915_gmch_probe(struct i915_ggtt *ggtt)
(struct resource)DEFINE_RES_MEM(gmadr_base, ggtt->mappable_end);
ggtt->vm.alloc_pt_dma = alloc_pt_dma;
+ ggtt->vm.alloc_scratch_dma = alloc_pt_dma;
if (needs_idle_maps(i915)) {
drm_notice(>drm,
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c
b/drivers/gpu/drm/i915/gt/intel_gtt.c
index 2a6eec5f0d58..56fbd37a6b54 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
@@ -298,7 +298,7 @@ int setup_scratch_page(struct i915_address_space *vm)
do {
struct drm_i915_gem_object *obj;
- obj = vm->alloc_pt_dma(vm, size);
+ obj = vm->alloc_scratch_dma(vm, size);
if (IS_ERR(obj))
goto skip;
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h
b/drivers/gpu/drm/i915/gt/intel_gtt.h
index bc6750263359..6d13f4ab4d4a 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.h
+++
[Intel-gfx] [PATCH 04/14] drm/i915: enforce min page size for scratch
From: Matthew Auld If the device needs 64K minimum GTT pages for device local-memory, like on XEHPSDV, then we need to fail the allocation if we can't meet it, instead of falling back to 4K pages, otherwise we can't safely support the insertion of device local-memory pages for this vm, since the HW expects the correct physical alignment and size for every PTE, if we mark the page-table as 64K GTT mode. Signed-off-by: Matthew Auld Signed-off-by: Ramalingam C --- drivers/gpu/drm/i915/gt/intel_gtt.c | 12 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c index 67d14afa6623..2a6eec5f0d58 100644 --- a/drivers/gpu/drm/i915/gt/intel_gtt.c +++ b/drivers/gpu/drm/i915/gt/intel_gtt.c @@ -334,6 +334,18 @@ int setup_scratch_page(struct i915_address_space *vm) if (size == I915_GTT_PAGE_SIZE_4K) return -ENOMEM; + /* +* If we need 64K minimum GTT pages for device local-memory, +* like on XEHPSDV, then we need to fail the allocation here, +* otherwise we can't safely support the insertion of +* local-memory pages for this vm, since the HW expects the +* correct physical alignment and size when the page-table is +* operating in 64K GTT mode, which includes any scratch PTEs, +* since userpsace can still touch them. +*/ + if (HAS_64K_PAGES(vm->i915)) + return -ENOMEM; + size = I915_GTT_PAGE_SIZE_4K; } while (1); } -- 2.20.1
[Intel-gfx] [PATCH 03/14] drm/i915/xehpsdv: enforce min GTT alignment
From: Matthew Auld
For local-memory objects we need to align the GTT addresses to 64K, both
for the ppgtt and ggtt.
Signed-off-by: Matthew Auld
Signed-off-by: Stuart Summers
Signed-off-by: Ramalingam C
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_vma.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index 4b7fc4647e46..1ea1fa08efdf 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -670,8 +670,13 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64
alignment, u64 flags)
}
color = 0;
- if (vma->obj && i915_vm_has_cache_coloring(vma->vm))
- color = vma->obj->cache_level;
+ if (vma->obj) {
+ if (HAS_64K_PAGES(vma->vm->i915) &&
i915_gem_object_is_lmem(vma->obj))
+ alignment = max(alignment, I915_GTT_PAGE_SIZE_64K);
+
+ if (i915_vm_has_cache_coloring(vma->vm))
+ color = vma->obj->cache_level;
+ }
if (flags & PIN_OFFSET_FIXED) {
u64 offset = flags & PIN_OFFSET_MASK;
--
2.20.1
[Intel-gfx] [PATCH 02/14] drm/i915/xehpsdv: set min page-size to 64K
From: Matthew Auld LMEM should be allocated at 64K granularity, since 4K page support will eventually be dropped for LMEM when using the PPGTT. Signed-off-by: Matthew Auld Signed-off-by: Stuart Summers Signed-off-by: Ramalingam C Cc: Joonas Lahtinen Cc: Rodrigo Vivi --- drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 6 +- drivers/gpu/drm/i915/gt/intel_region_lmem.c | 5 - 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c index ddd37ccb1362..f52a06f05fc7 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c @@ -778,6 +778,7 @@ i915_gem_stolen_lmem_setup(struct drm_i915_private *i915, u16 type, struct intel_uncore *uncore = >uncore; struct pci_dev *pdev = to_pci_dev(i915->drm.dev); struct intel_memory_region *mem; + resource_size_t min_page_size; resource_size_t io_start; resource_size_t lmem_size; u64 lmem_base; @@ -789,8 +790,11 @@ i915_gem_stolen_lmem_setup(struct drm_i915_private *i915, u16 type, lmem_size = pci_resource_len(pdev, 2) - lmem_base; io_start = pci_resource_start(pdev, 2) + lmem_base; + min_page_size = HAS_64K_PAGES(i915) ? I915_GTT_PAGE_SIZE_64K : + I915_GTT_PAGE_SIZE_4K; + mem = intel_memory_region_create(i915, lmem_base, lmem_size, -I915_GTT_PAGE_SIZE_4K, io_start, +min_page_size, io_start, type, instance, _region_stolen_lmem_ops); if (IS_ERR(mem)) diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c b/drivers/gpu/drm/i915/gt/intel_region_lmem.c index afb35d2e5c73..073d28d96669 100644 --- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c +++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c @@ -193,6 +193,7 @@ static struct intel_memory_region *setup_lmem(struct intel_gt *gt) struct intel_uncore *uncore = gt->uncore; struct pci_dev *pdev = to_pci_dev(i915->drm.dev); struct intel_memory_region *mem; + resource_size_t min_page_size; resource_size_t io_start; resource_size_t lmem_size; int err; @@ -207,10 +208,12 @@ static struct intel_memory_region *setup_lmem(struct intel_gt *gt) if (GEM_WARN_ON(lmem_size > pci_resource_len(pdev, 2))) return ERR_PTR(-ENODEV); + min_page_size = HAS_64K_PAGES(i915) ? I915_GTT_PAGE_SIZE_64K : + I915_GTT_PAGE_SIZE_4K; mem = intel_memory_region_create(i915, 0, lmem_size, -I915_GTT_PAGE_SIZE_4K, +min_page_size, io_start, INTEL_MEMORY_LOCAL, 0, -- 2.20.1
[Intel-gfx] [PATCH 01/14] drm/i915: Add has_64k_pages flag
From: Stuart Summers
Add a new platform flag, has_64k_pages, for platforms supporting
base page sizes of 64k.
Signed-off-by: Stuart Summers
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_pci.c | 2 ++
drivers/gpu/drm/i915/intel_device_info.h | 1 +
3 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 12256218634f..a16fde38a252 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1714,6 +1714,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_MSLICES(dev_priv) \
(INTEL_INFO(dev_priv)->has_mslices)
+#define HAS_64K_PAGES(dev_priv) (INTEL_INFO(dev_priv)->has_64k_pages)
+
#define HAS_IPC(dev_priv) (INTEL_INFO(dev_priv)->display.has_ipc)
#define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i))
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 169837de395d..8ef484a23652 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1015,6 +1015,7 @@ static const struct intel_device_info xehpsdv_info = {
DGFX_FEATURES,
PLATFORM(INTEL_XEHPSDV),
.display = { },
+ .has_64k_pages = 1,
.pipe_mask = 0,
.platform_engine_mask =
BIT(RCS0) | BIT(BCS0) |
@@ -1033,6 +1034,7 @@ static const struct intel_device_info dg2_info = {
.graphics_rel = 55,
.media_rel = 55,
PLATFORM(INTEL_DG2),
+ .has_64k_pages = 1,
.platform_engine_mask =
BIT(RCS0) | BIT(BCS0) |
BIT(VECS0) | BIT(VECS1) |
diff --git a/drivers/gpu/drm/i915/intel_device_info.h
b/drivers/gpu/drm/i915/intel_device_info.h
index 8e6f48d1eb7b..dd453b96af19 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -123,6 +123,7 @@ enum intel_ppgtt_type {
func(is_dgfx); \
/* Keep has_* in alphabetical order */ \
func(has_64bit_reloc); \
+ func(has_64k_pages); \
func(gpu_reset_clobbers_display); \
func(has_reset_engine); \
func(has_global_mocs); \
--
2.20.1
[Intel-gfx] [PATCH 00/14] drm/i915/dg2: Enabling 64k page size and flat ccs
This series introduces the enabling patches for new flat ccs feature and 64k page support for i915 local memory, along with documentation on the uAPI impact. 64k page support On discrete platforms, starting from DG2, we have to contend with GTT page size restrictions when dealing with I915_MEMORY_CLASS_DEVICE objects. Specifically the hardware only supports 64K or larger GTT page sizes for such memory. The kernel will already ensure that all I915_MEMORY_CLASS_DEVICE memory is allocated using 64K or larger page sizes underneath. Note that the returned size here will always reflect any required rounding up done by the kernel, i.e 4K will now become 64K on devices such as DG2. The GTT alignment will also need be at least 64K for such objects. Note that due to how the hardware implements 64K GTT page support, we have some further complications: 1.) The entire PDE(which covers a 2M virtual address range), must contain only 64K PTEs, i.e mixing 4K and 64K PTEs in the same PDE is forbidden by the hardware. 2.) We still need to support 4K PTEs for I915_MEMORY_CLASS_SYSTEM objects. To handle the above the kernel implements a memory coloring scheme to prevent userspace from mixing I915_MEMORY_CLASS_DEVICE and I915_MEMORY_CLASS_SYSTEM objects in the same PDE. If the kernel is ever unable to evict the required pages for the given PDE(different color) when inserting the object into the GTT then it will simply fail the request. Since userspace needs to manage the GTT address space themselves, special care is needed to ensure this doesn’t happen. The simplest scheme is to simply align and round up all I915_MEMORY_CLASS_DEVICE objects to 2M, which avoids any issues here. At the very least this is likely needed for objects that can be placed in both I915_MEMORY_CLASS_DEVICE and I915_MEMORY_CLASS_SYSTEM, to avoid potential issues when the kernel needs to migrate the object behind the scenes, since that might also involve evicting other objects. To summarise the GTT rules, on platforms like DG2: 1.) All objects that can be placed in I915_MEMORY_CLASS_DEVICE must have 64K alignment. The kernel will reject this otherwise. 2.) All I915_MEMORY_CLASS_DEVICE objects must never be placed in the same PDE with other I915_MEMORY_CLASS_SYSTEM objects. The kernel will reject this otherwise. 3.) Objects that can be placed in both I915_MEMORY_CLASS_DEVICE and I915_MEMORY_CLASS_SYSTEM should probably be aligned and padded out to 2M. Flat CCS: = Gen 12+ devices support 3D surfaces compression and compression formats. This is accomplished by an additional compression control state (CCS) stored for each surface. Gen 12 devices(TGL and DG1) stores compression state in a separate region of memory. It is managed by userspace and has an associated set of userspace managed page tables used by hardware for address translation. In Gen 12.5 devices(XEXPSDV and DG2) Flat CCS is introduced to replace the userspace managed AUX pagetable with the flat indexed region of device memory for storing the compression state GOP Driver steals a chunk of memory for the CCS surface corresponding to the entire range of local memory. The memory required for the CCS of the entire local memory is 1/256 of the main local memory. The Gop driver will also program a secure register (XEHPSDV_FLAT_CCS_BASE_ADDR 0x4910) with this address value. TODO: add patches for the flatccs modifiers and kdoc for them. *** BLURB HERE *** Abdiel Janulgue (1): drm/i915/lmem: Enable lmem for platforms with Flat CCS Ayaz A Siddiqui (1): drm/i915/gt: Clear compress metadata for Gen12.5 >= platforms Bommu Krishnaiah (1): drm/i915: Add vm min alignment support CQ Tang (1): drm/i915/xehpsdv: Add has_flat_ccs to device info Matthew Auld (8): drm/i915/xehpsdv: set min page-size to 64K drm/i915/xehpsdv: enforce min GTT alignment drm/i915: enforce min page size for scratch drm/i915/gtt/xehpsdv: move scratch page to system memory drm/i915/xehpsdv: support 64K GTT pages drm/i915/selftests: account for min_alignment in GTT selftests drm/i915/xehpsdv: implement memory coloring drm/i915/uapi: document behaviour for DG2 64K support Ramalingam C (1): Doc/gpu/rfc/i915: i915 DG2 uAPI Stuart Summers (1): drm/i915: Add has_64k_pages flag Documentation/gpu/rfc/i915_dg2.rst| 47 ++ Documentation/gpu/rfc/index.rst | 3 + drivers/gpu/drm/i915/gem/i915_gem_stolen.c| 6 +- .../gpu/drm/i915/gem/selftests/huge_pages.c | 61 .../i915/gem/selftests/i915_gem_client_blt.c | 23 ++- drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 1 + drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 145 +- drivers/gpu/drm/i915/gt/intel_ggtt.c | 2 + drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 14 ++ drivers/gpu/drm/i915/gt/intel_gt.c| 19 +++ drivers/gpu/drm/i915/gt/intel_gt.h| 1 + drivers/gpu/drm/i915/gt/intel_gtt.c | 23 ++-
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v8,1/8] drm/i915/gem: Break out some shmem backend utils
== Series Details == Series: series starting with [v8,1/8] drm/i915/gem: Break out some shmem backend utils URL : https://patchwork.freedesktop.org/series/95677/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_reset.c:1392:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/i915_perf.c:1442:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1496:15: warning: memset with byte count of 16777216 +./include/asm-generic/bitops/find.h:112:45: warning: shift count is negative (-262080) +./include/asm-generic/bitops/find.h:32:31: warning: shift count is negative (-262080) +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v8,1/8] drm/i915/gem: Break out some shmem backend utils
== Series Details == Series: series starting with [v8,1/8] drm/i915/gem: Break out some shmem backend utils URL : https://patchwork.freedesktop.org/series/95677/ State : warning == Summary == $ dim checkpatch origin/drm-tip 099555c40683 drm/i915/gem: Break out some shmem backend utils 671a8c82b83e drm/i915/ttm: add tt shmem backend -:16: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #16: dropping the shrinker LRU lock and acquiring the object lock it could for total: 0 errors, 1 warnings, 0 checks, 486 lines checked 0cfe455fe862 drm/i915/gtt: drop unneeded make_unshrinkable ff13e70ecb3e drm/i915: drop unneeded make_unshrinkable in free_object 75d83867da45 drm/i915: add some kernel-doc for shrink_pin and friends 025e10342271 drm/i915/ttm: move shrinker management into adjust_lru -:19: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #19: an object. Importantly this covers the case where TTM moves something from total: 0 errors, 1 warnings, 0 checks, 290 lines checked 1c04e4705012 drm/i915/ttm: use cached system pages when evicting lmem b9ff4a500ac8 drm/i915/ttm: enable shmem tt backend
[Intel-gfx] [PATCH 0/4] drm/i915/guc: Inject probe errors for MMIO send, CT send
Injecting probe errors for MMIO send, CT send to make probe flow more robust. Use i915_probe_error to report probe injection errors. Thanneeru Srinivasulu (4): drm/i915/huc: Use i915_probe_error to report early CTB failures drm/i915/huc: Use i915_probe_error to report early HuC failures drm/i915/guc: Inject probe errors for MMIO send drm/i915/guc: Inject probe errors for CT send drivers/gpu/drm/i915/gt/uc/intel_guc.c| 4 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 12 ++-- drivers/gpu/drm/i915/gt/uc/intel_huc.c| 4 ++-- 3 files changed, 16 insertions(+), 4 deletions(-) -- 2.25.1
[Intel-gfx] [PATCH 1/4] drm/i915/huc: Use i915_probe_error to report early CTB failures
Replace DRM_ERROR with CT_PROBE_ERROR to report early CTB failures. Signed-off-by: Thanneeru Srinivasulu --- drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c index 0a3504bc0b61..83764db0fd6d 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c @@ -191,8 +191,8 @@ static int ct_register_buffer(struct intel_guc_ct *ct, u32 type, err = guc_action_register_ct_buffer(ct_to_guc(ct), type, desc_addr, buff_addr, size); if (unlikely(err)) - CT_ERROR(ct, "Failed to register %s buffer (%pe)\n", -guc_ct_buffer_type_to_str(type), ERR_PTR(err)); + CT_PROBE_ERROR(ct, "Failed to register %s buffer (%pe)\n", + guc_ct_buffer_type_to_str(type), ERR_PTR(err)); return err; } -- 2.25.1
[Intel-gfx] [PATCH 4/4] drm/i915/guc: Inject probe errors for CT send
Inject probe errors -ENXIO, -EBUSY for CT send.
Signed-off-by: Thanneeru Srinivasulu
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
index 83764db0fd6d..8ffef3abd3da 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
@@ -765,6 +765,14 @@ int intel_guc_ct_send(struct intel_guc_ct *ct, const u32
*action, u32 len,
u32 status = ~0; /* undefined */
int ret;
+ ret = i915_inject_probe_error(ct_to_i915(ct), -ENXIO);
+ if (ret)
+ return ret;
+
+ ret = i915_inject_probe_error(ct_to_i915(ct), -EBUSY);
+ if (ret)
+ return ret;
+
if (unlikely(!ct->enabled)) {
struct intel_guc *guc = ct_to_guc(ct);
struct intel_uc *uc = container_of(guc, struct intel_uc, guc);
--
2.25.1
[Intel-gfx] [PATCH 3/4] drm/i915/guc: Inject probe errors for MMIO send
Injecting probe errors -ENXIO for MMIO send. Signed-off-by: Thanneeru Srinivasulu --- drivers/gpu/drm/i915/gt/uc/intel_guc.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c index 8f8182bf7c11..490d66712afc 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c @@ -403,6 +403,10 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32 *request, u32 len, int i; int ret; + ret = i915_inject_probe_error(i915, -ENXIO); + if (ret) + return ret; + GEM_BUG_ON(!len); GEM_BUG_ON(len > guc->send_regs.count); -- 2.25.1
[Intel-gfx] [PATCH 2/4] drm/i915/huc: Use i915_probe_error to report early HuC failures
Replace DRM_ERROR with i915_probe_error to report early HuC failures.
Signed-off-by: Thanneeru Srinivasulu
---
drivers/gpu/drm/i915/gt/uc/intel_huc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
index ff4b6869b80b..ff0f5b9130c9 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
@@ -179,7 +179,7 @@ int intel_huc_auth(struct intel_huc *huc)
ret = intel_guc_auth_huc(guc,
intel_guc_ggtt_offset(guc, huc->rsa_data));
if (ret) {
- DRM_ERROR("HuC: GuC did not ack Auth request %d\n", ret);
+ i915_probe_error(gt->i915, "HuC: GuC did not ack Auth request
%d\n", ret);
goto fail;
}
@@ -190,7 +190,7 @@ int intel_huc_auth(struct intel_huc *huc)
huc->status.value,
2, 50, NULL);
if (ret) {
- DRM_ERROR("HuC: Firmware not verified %d\n", ret);
+ i915_probe_error(gt->i915, "HuC: Firmware not verified %d\n",
ret);
goto fail;
}
--
2.25.1
[Intel-gfx] [PATCH v8 7/8] drm/i915/ttm: use cached system pages when evicting lmem
This should let us do an accelerated copy directly to the shmem pages
when temporarily moving lmem-only objects, where the i915-gem shrinker
can later kick in to swap out the pages, if needed.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Reviewed-by: Thomas Hellström
---
drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
index 21a2b37ae1e7..dfbce5607ddc 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
@@ -134,11 +134,11 @@ static enum ttm_caching
i915_ttm_select_tt_caching(const struct drm_i915_gem_object *obj)
{
/*
-* Objects only allowed in system get cached cpu-mappings.
-* Other objects get WC mapping for now. Even if in system.
+* Objects only allowed in system get cached cpu-mappings, or when
+* evicting lmem-only buffers to system for swapping. Other objects get
+* WC mapping for now. Even if in system.
*/
- if (obj->mm.region->type == INTEL_MEMORY_SYSTEM &&
- obj->mm.n_placements <= 1)
+ if (obj->mm.n_placements <= 1)
return ttm_cached;
return ttm_write_combined;
--
2.26.3
[Intel-gfx] [PATCH v8 8/8] drm/i915/ttm: enable shmem tt backend
Turn on the shmem tt backend, and enable shrinking.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Reviewed-by: Thomas Hellström
---
drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
index dfbce5607ddc..99e993caa3d4 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
@@ -1116,7 +1116,8 @@ static u64 i915_ttm_mmap_offset(struct
drm_i915_gem_object *obj)
static const struct drm_i915_gem_object_ops i915_gem_ttm_obj_ops = {
.name = "i915_gem_object_ttm",
- .flags = I915_GEM_OBJECT_SELF_MANAGED_SHRINK_LIST,
+ .flags = I915_GEM_OBJECT_IS_SHRINKABLE |
+I915_GEM_OBJECT_SELF_MANAGED_SHRINK_LIST,
.get_pages = i915_ttm_get_pages,
.put_pages = i915_ttm_put_pages,
--
2.26.3
[Intel-gfx] [PATCH v8 6/8] drm/i915/ttm: move shrinker management into adjust_lru
We currently just evict lmem objects to system memory when under memory
pressure. For this case we might lack the usual object mm.pages, which
effectively hides the pages from the i915-gem shrinker, until we
actually "attach" the TT to the object, or in the case of lmem-only
objects it just gets migrated back to lmem when touched again.
For all cases we can just adjust the i915 shrinker LRU each time we also
adjust the TTM LRU. The two cases we care about are:
1) When something is moved by TTM, including when initially populating
an object. Importantly this covers the case where TTM moves something from
lmem <-> smem, outside of the normal get_pages() interface, which
should still ensure the shmem pages underneath are reclaimable.
2) When calling into i915_gem_object_unlock(). The unlock should
ensure the object is removed from the shinker LRU, if it was indeed
swapped out, or just purged, when the shrinker drops the object lock.
v2(Thomas):
- Handle managing the shrinker LRU in adjust_lru, where it is always
safe to touch the object.
v3(Thomas):
- Pretty much a re-write. This time piggy back off the shrink_pin
stuff, which actually seems to fit quite well for what we want here.
v4(Thomas):
- Just use a simple boolean for tracking ttm_shrinkable.
v5:
- Ensure we call adjust_lru when faulting the object, to ensure the
pages are visible to the shrinker, if needed.
- Add back the adjust_lru when in i915_ttm_move (Thomas)
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Reviewed-by: Thomas Hellström #v4
---
drivers/gpu/drm/i915/gem/i915_gem_object.h| 8 ++
.../gpu/drm/i915/gem/i915_gem_object_types.h | 14 +++-
drivers/gpu/drm/i915/gem/i915_gem_pages.c | 5 +-
drivers/gpu/drm/i915/gem/i915_gem_shrinker.c | 45 --
drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 84 +--
5 files changed, 137 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h
b/drivers/gpu/drm/i915/gem/i915_gem_object.h
index e641db297e0e..3eac8cf2ae10 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h
@@ -294,6 +294,12 @@ i915_gem_object_is_shrinkable(const struct
drm_i915_gem_object *obj)
return i915_gem_object_type_has(obj, I915_GEM_OBJECT_IS_SHRINKABLE);
}
+static inline bool
+i915_gem_object_has_self_managed_shrink_list(const struct drm_i915_gem_object
*obj)
+{
+ return i915_gem_object_type_has(obj,
I915_GEM_OBJECT_SELF_MANAGED_SHRINK_LIST);
+}
+
static inline bool
i915_gem_object_is_proxy(const struct drm_i915_gem_object *obj)
{
@@ -531,6 +537,8 @@ i915_gem_object_pin_to_display_plane(struct
drm_i915_gem_object *obj,
void i915_gem_object_make_unshrinkable(struct drm_i915_gem_object *obj);
void i915_gem_object_make_shrinkable(struct drm_i915_gem_object *obj);
+void __i915_gem_object_make_shrinkable(struct drm_i915_gem_object *obj);
+void __i915_gem_object_make_purgeable(struct drm_i915_gem_object *obj);
void i915_gem_object_make_purgeable(struct drm_i915_gem_object *obj);
static inline bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index f4233c4e8d2e..5718a09f5533 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -34,9 +34,11 @@ struct i915_lut_handle {
struct drm_i915_gem_object_ops {
unsigned int flags;
-#define I915_GEM_OBJECT_IS_SHRINKABLE BIT(1)
-#define I915_GEM_OBJECT_IS_PROXY BIT(2)
-#define I915_GEM_OBJECT_NO_MMAPBIT(3)
+#define I915_GEM_OBJECT_IS_SHRINKABLE BIT(1)
+/* Skip the shrinker management in set_pages/unset_pages */
+#define I915_GEM_OBJECT_SELF_MANAGED_SHRINK_LIST BIT(2)
+#define I915_GEM_OBJECT_IS_PROXY BIT(3)
+#define I915_GEM_OBJECT_NO_MMAPBIT(4)
/* Interface between the GEM object and its backing storage.
* get_pages() is called once prior to the use of the associated set
@@ -485,6 +487,12 @@ struct drm_i915_gem_object {
*/
atomic_t shrink_pin;
+ /**
+* @ttm_shrinkable: True when the object is using shmem pages
+* underneath. Protected by the object lock.
+*/
+ bool ttm_shrinkable;
+
/**
* Priority list of potential placements for this object.
*/
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
index ea6d9b3d2d6b..308e22a80af4 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
@@ -68,7 +68,7 @@ void __i915_gem_object_set_pages(struct drm_i915_gem_object
*obj,
shrinkable = false;
}
- if
[Intel-gfx] [PATCH v8 2/8] drm/i915/ttm: add tt shmem backend
For cached objects we can allocate our pages directly in shmem. This
should make it possible(in a later patch) to utilise the existing
i915-gem shrinker code for such objects. For now this is still disabled.
v2(Thomas):
- Add optional try_to_writeback hook for objects. Importantly we need
to check if the object is even still shrinkable; in between us
dropping the shrinker LRU lock and acquiring the object lock it could for
example have been moved. Also we need to differentiate between
"lazy" shrinking and the immediate writeback mode. Also later we need to
handle objects which don't even have mm.pages, so bundling this into
put_pages() would require somehow handling that edge case, hence
just letting the ttm backend handle everything in try_to_writeback
doesn't seem too bad.
v3(Thomas):
- Likely a bad idea to touch the object from the unpopulate hook,
since it's not possible to hold a reference, without also creating
circular dependency, so likely this is too fragile. For now just
ensure we at least mark the pages as dirty/accessed when called from the
shrinker on WILLNEED objects.
- s/try_to_writeback/shrinker_release_pages, since this can do more
than just writeback.
- Get rid of do_backup boolean and just set the SWAPPED flag prior to
calling unpopulate.
- Keep shmem_tt as lowest priority for the TTM LRU bo_swapout walk, since
these just get skipped anyway. We can try to come up with something
better later.
v4(Thomas):
- s/PCI_DMA/DMA/. Also drop NO_KERNEL_MAPPING and NO_WARN, which
apparently doesn't do anything with streaming mappings.
- Just pass along the error for ->truncate, and assume nothing.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Cc: Christian König
Cc: Oak Zeng
Reviewed-by: Thomas Hellström
Acked-by: Oak Zeng
---
drivers/gpu/drm/i915/gem/i915_gem_object.h| 11 +-
.../gpu/drm/i915/gem/i915_gem_object_types.h | 4 +-
drivers/gpu/drm/i915/gem/i915_gem_pages.c | 6 +-
drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 18 +-
drivers/gpu/drm/i915/gem/i915_gem_shrinker.c | 17 +-
drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 233 --
6 files changed, 247 insertions(+), 42 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h
b/drivers/gpu/drm/i915/gem/i915_gem_object.h
index 9df3ee60604e..e641db297e0e 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h
@@ -93,7 +93,6 @@ void i915_gem_flush_free_objects(struct drm_i915_private
*i915);
struct sg_table *
__i915_gem_object_unset_pages(struct drm_i915_gem_object *obj);
-void i915_gem_object_truncate(struct drm_i915_gem_object *obj);
/**
* i915_gem_object_lookup_rcu - look up a temporary GEM object from its handle
@@ -449,7 +448,7 @@ i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
}
int __i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
-void i915_gem_object_truncate(struct drm_i915_gem_object *obj);
+int i915_gem_object_truncate(struct drm_i915_gem_object *obj);
void i915_gem_object_writeback(struct drm_i915_gem_object *obj);
/**
@@ -612,6 +611,14 @@ int i915_gem_object_wait_migration(struct
drm_i915_gem_object *obj,
bool i915_gem_object_placement_possible(struct drm_i915_gem_object *obj,
enum intel_memory_type type);
+struct sg_table *shmem_alloc_st(struct drm_i915_private *i915,
+ size_t size, struct intel_memory_region *mr,
+ struct address_space *mapping,
+ unsigned int max_segment);
+void shmem_free_st(struct sg_table *st, struct address_space *mapping,
+ bool dirty, bool backup);
+void __shmem_writeback(size_t size, struct address_space *mapping);
+
#ifdef CONFIG_MMU_NOTIFIER
static inline bool
i915_gem_object_is_userptr(struct drm_i915_gem_object *obj)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index 7c3da4e3e737..7dd5f804aab3 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -54,8 +54,10 @@ struct drm_i915_gem_object_ops {
int (*get_pages)(struct drm_i915_gem_object *obj);
void (*put_pages)(struct drm_i915_gem_object *obj,
struct sg_table *pages);
- void (*truncate)(struct drm_i915_gem_object *obj);
+ int (*truncate)(struct drm_i915_gem_object *obj);
void (*writeback)(struct drm_i915_gem_object *obj);
+ int (*shrinker_release_pages)(struct drm_i915_gem_object *obj,
+ bool should_writeback);
int (*pread)(struct drm_i915_gem_object *obj,
const struct drm_i915_gem_pread *arg);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
index
[Intel-gfx] [PATCH v8 5/8] drm/i915: add some kernel-doc for shrink_pin and friends
Attempt to document shrink_pin and the other relevant interfaces that
interact with it, before we start messing with it.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Reviewed-by: Thomas Hellström
---
.../gpu/drm/i915/gem/i915_gem_object_types.h | 24 +-
drivers/gpu/drm/i915/gem/i915_gem_shrinker.c | 31 +++
2 files changed, 54 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index 7dd5f804aab3..f4233c4e8d2e 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -461,6 +461,28 @@ struct drm_i915_gem_object {
* instead go through the pin/unpin interfaces.
*/
atomic_t pages_pin_count;
+
+ /**
+* @shrink_pin: Prevents the pages from being made visible to
+* the shrinker, while the shrink_pin is non-zero. Most users
+* should pretty much never have to care about this, outside of
+* some special use cases.
+*
+* By default most objects will start out as visible to the
+* shrinker(if I915_GEM_OBJECT_IS_SHRINKABLE) as soon as the
+* backing pages are attached to the object, like in
+* __i915_gem_object_set_pages(). They will then be removed the
+* shrinker list once the pages are released.
+*
+* The @shrink_pin is incremented by calling
+* i915_gem_object_make_unshrinkable(), which will also remove
+* the object from the shrinker list, if the pin count was zero.
+*
+* Callers will then typically call
+* i915_gem_object_make_shrinkable() or
+* i915_gem_object_make_purgeable() to decrement the pin count,
+* and make the pages visible again.
+*/
atomic_t shrink_pin;
/**
@@ -522,7 +544,7 @@ struct drm_i915_gem_object {
struct i915_gem_object_page_iter get_dma_page;
/**
-* Element within i915->mm.unbound_list or i915->mm.bound_list,
+* Element within i915->mm.shrink_list or i915->mm.purge_list,
* locked by i915->mm.obj_lock.
*/
struct list_head link;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
b/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
index ae2a8d54b7a4..66121fedc655 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
@@ -463,6 +463,16 @@ void i915_gem_shrinker_taints_mutex(struct
drm_i915_private *i915,
#define obj_to_i915(obj__) to_i915((obj__)->base.dev)
+/**
+ * i915_gem_object_make_unshrinkable - Hide the object from the shrinker. By
+ * default all object types that support shrinking(see IS_SHRINKABLE), will
also
+ * make the object visible to the shrinker after allocating the system memory
+ * pages.
+ * @obj: The GEM object.
+ *
+ * This is typically used for special kernel internal objects that can't be
+ * easily processed by the shrinker, like if they are perma-pinned.
+ */
void i915_gem_object_make_unshrinkable(struct drm_i915_gem_object *obj)
{
struct drm_i915_private *i915 = obj_to_i915(obj);
@@ -513,12 +523,33 @@ static void __i915_gem_object_make_shrinkable(struct
drm_i915_gem_object *obj,
spin_unlock_irqrestore(>mm.obj_lock, flags);
}
+/**
+ * i915_gem_object_make_shrinkable - Move the object to the tail of the
+ * shrinkable list. Objects on this list might be swapped out. Used with
+ * WILLNEED objects.
+ * @obj: The GEM object.
+ *
+ * MUST only be called on objects which have backing pages.
+ *
+ * MUST be balanced with previous call to i915_gem_object_make_unshrinkable().
+ */
void i915_gem_object_make_shrinkable(struct drm_i915_gem_object *obj)
{
__i915_gem_object_make_shrinkable(obj,
_to_i915(obj)->mm.shrink_list);
}
+/**
+ * i915_gem_object_make_purgeable - Move the object to the tail of the
purgeable
+ * list. Used with DONTNEED objects. Unlike with shrinkable objects, the
+ * shrinker will attempt to discard the backing pages, instead of trying to
swap
+ * them out.
+ * @obj: The GEM object.
+ *
+ * MUST only be called on objects which have backing pages.
+ *
+ * MUST be balanced with previous call to i915_gem_object_make_unshrinkable().
+ */
void i915_gem_object_make_purgeable(struct drm_i915_gem_object *obj)
{
__i915_gem_object_make_shrinkable(obj,
--
2.26.3
[Intel-gfx] [PATCH v8 1/8] drm/i915/gem: Break out some shmem backend utils
From: Thomas Hellström
Break out some shmem backend utils for future reuse by the TTM backend:
shmem_alloc_st(), shmem_free_st() and __shmem_writeback() which we can
use to provide a shmem-backed TTM page pool for cached-only TTM
buffer objects.
Main functional change here is that we now compute the page sizes using
the dma segments rather than using the physical page address segments.
v2(Reported-by: kernel test robot )
- Make sure we initialise the mapping on the error path in
shmem_get_pages()
Signed-off-by: Thomas Hellström
Reviewed-by: Matthew Auld
Signed-off-by: Matthew Auld
---
drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 181 +-
1 file changed, 106 insertions(+), 75 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
index 11f072193f3b..36b711ae9e28 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
@@ -25,46 +25,61 @@ static void check_release_pagevec(struct pagevec *pvec)
cond_resched();
}
-static int shmem_get_pages(struct drm_i915_gem_object *obj)
+static void shmem_free_st(struct sg_table *st, struct address_space *mapping,
+ bool dirty, bool backup)
{
- struct drm_i915_private *i915 = to_i915(obj->base.dev);
- struct intel_memory_region *mem = obj->mm.region;
- const unsigned long page_count = obj->base.size / PAGE_SIZE;
+ struct sgt_iter sgt_iter;
+ struct pagevec pvec;
+ struct page *page;
+
+ mapping_clear_unevictable(mapping);
+
+ pagevec_init();
+ for_each_sgt_page(page, sgt_iter, st) {
+ if (dirty)
+ set_page_dirty(page);
+
+ if (backup)
+ mark_page_accessed(page);
+
+ if (!pagevec_add(, page))
+ check_release_pagevec();
+ }
+ if (pagevec_count())
+ check_release_pagevec();
+
+ sg_free_table(st);
+ kfree(st);
+}
+
+static struct sg_table *shmem_alloc_st(struct drm_i915_private *i915,
+ size_t size, struct intel_memory_region
*mr,
+ struct address_space *mapping,
+ unsigned int max_segment)
+{
+ const unsigned long page_count = size / PAGE_SIZE;
unsigned long i;
- struct address_space *mapping;
struct sg_table *st;
struct scatterlist *sg;
- struct sgt_iter sgt_iter;
struct page *page;
unsigned long last_pfn = 0; /* suppress gcc warning */
- unsigned int max_segment = i915_sg_segment_size();
- unsigned int sg_page_sizes;
gfp_t noreclaim;
int ret;
- /*
-* Assert that the object is not currently in any GPU domain. As it
-* wasn't in the GTT, there shouldn't be any way it could have been in
-* a GPU cache
-*/
- GEM_BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS);
- GEM_BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS);
-
/*
* If there's no chance of allocating enough pages for the whole
* object, bail early.
*/
- if (obj->base.size > resource_size(>region))
- return -ENOMEM;
+ if (size > resource_size(>region))
+ return ERR_PTR(-ENOMEM);
st = kmalloc(sizeof(*st), GFP_KERNEL);
if (!st)
- return -ENOMEM;
+ return ERR_PTR(-ENOMEM);
-rebuild_st:
if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
kfree(st);
- return -ENOMEM;
+ return ERR_PTR(-ENOMEM);
}
/*
@@ -73,14 +88,12 @@ static int shmem_get_pages(struct drm_i915_gem_object *obj)
*
* Fail silently without starting the shrinker
*/
- mapping = obj->base.filp->f_mapping;
mapping_set_unevictable(mapping);
noreclaim = mapping_gfp_constraint(mapping, ~__GFP_RECLAIM);
noreclaim |= __GFP_NORETRY | __GFP_NOWARN;
sg = st->sgl;
st->nents = 0;
- sg_page_sizes = 0;
for (i = 0; i < page_count; i++) {
const unsigned int shrink[] = {
I915_SHRINK_BOUND | I915_SHRINK_UNBOUND,
@@ -135,10 +148,9 @@ static int shmem_get_pages(struct drm_i915_gem_object *obj)
if (!i ||
sg->length >= max_segment ||
page_to_pfn(page) != last_pfn + 1) {
- if (i) {
- sg_page_sizes |= sg->length;
+ if (i)
sg = sg_next(sg);
- }
+
st->nents++;
sg_set_page(sg, page, PAGE_SIZE, 0);
} else {
@@ -149,14 +161,65 @@ static int shmem_get_pages(struct drm_i915_gem_object
*obj)
/* Check
[Intel-gfx] [PATCH v8 3/8] drm/i915/gtt: drop unneeded make_unshrinkable
We already do this when mapping the pages. Signed-off-by: Matthew Auld Cc: Thomas Hellström Reviewed-by: Thomas Hellström --- drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 1 - drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 1 - 2 files changed, 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c index 890191f286e3..baea9770200a 100644 --- a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c +++ b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c @@ -185,7 +185,6 @@ static void gen6_alloc_va_range(struct i915_address_space *vm, pt = stash->pt[0]; __i915_gem_object_pin_pages(pt->base); - i915_gem_object_make_unshrinkable(pt->base); fill32_px(pt, vm->scratch[0]->encode); diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c index 037a9a6e4889..8af2f709571c 100644 --- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c +++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c @@ -301,7 +301,6 @@ static void __gen8_ppgtt_alloc(struct i915_address_space * const vm, pt = stash->pt[!!lvl]; __i915_gem_object_pin_pages(pt->base); - i915_gem_object_make_unshrinkable(pt->base); fill_px(pt, vm->scratch[lvl]->encode); -- 2.26.3
[Intel-gfx] [PATCH v8 4/8] drm/i915: drop unneeded make_unshrinkable in free_object
The comment here is no longer accurate, since the current shrinker code requires a full ref before touching any objects. Also unset_pages() should already do the required make_unshrinkable() for us, if needed, which is also nicely balanced with set_pages(). Signed-off-by: Matthew Auld Cc: Thomas Hellström Reviewed-by: Thomas Hellström --- drivers/gpu/drm/i915/gem/i915_gem_object.c | 9 - 1 file changed, 9 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c b/drivers/gpu/drm/i915/gem/i915_gem_object.c index 76ce6a1500bc..1dc3c1940c32 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_object.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c @@ -337,15 +337,6 @@ static void i915_gem_free_object(struct drm_gem_object *gem_obj) */ atomic_inc(>mm.free_count); - /* -* This serializes freeing with the shrinker. Since the free -* is delayed, first by RCU then by the workqueue, we want the -* shrinker to be able to free pages of unreferenced objects, -* or else we may oom whilst there are plenty of deferred -* freed objects. -*/ - i915_gem_object_make_unshrinkable(obj); - /* * Since we require blocking on struct_mutex to unbind the freed * object from the GPU before releasing resources back to the -- 2.26.3
Re: [Intel-gfx] [Linaro-mm-sig] [PATCH] dma-resv: Fix dma_resv_get_fences and dma_resv_copy_fences after conversion
Am 11.10.21 um 14:32 schrieb Tvrtko Ursulin:
On 08/10/2021 13:19, Christian König wrote:
Am 08.10.21 um 12:49 schrieb Tvrtko Ursulin:
On 08/10/2021 11:21, Christian König wrote:
Am 08.10.21 um 11:50 schrieb Tvrtko Ursulin:
From: Tvrtko Ursulin
Cache the count of shared fences in the iterator to avoid
dereferencing
the dma_resv_object outside the RCU protection. Otherwise iterator
and its
users can observe an incosistent state which makes it impossible
to use
safely.
Ah, of course! I've been staring at the code the whole morning and
couldn't see it.
Going to write a testcase to cover that.
Such as:
<6> [187.517041] [IGT] gem_sync: executing
<7> [187.536343] i915 :00:02.0:
[drm:i915_gem_context_create_ioctl [i915]] HW context 1 created
<7> [187.536793] i915 :00:02.0:
[drm:i915_gem_context_create_ioctl [i915]] HW context 1 created
<6> [187.551235] [IGT] gem_sync: starting subtest basic-many-each
<1> [188.935462] BUG: kernel NULL pointer dereference, address:
0010
<1> [188.935485] #PF: supervisor write access in kernel mode
<1> [188.935495] #PF: error_code(0x0002) - not-present page
<6> [188.935504] PGD 0 P4D 0
<4> [188.935512] Oops: 0002 [#1] PREEMPT SMP NOPTI
<4> [188.935521] CPU: 2 PID: 1467 Comm: gem_sync Not tainted
5.15.0-rc4-CI-Patchwork_21264+ #1
<4> [188.935535] Hardware name: /NUC6CAYB, BIOS
AYAPLCEL.86A.0049.2018.0508.1356 05/08/2018
<4> [188.935546] RIP: 0010:dma_resv_get_fences+0x116/0x2d0
<4> [188.935560] Code: 10 85 c0 7f c9 be 03 00 00 00 e8 15 8b df
ff eb bd e8 8e c6 ff ff eb b6 41 8b 04 24 49 8b 55 00 48 89 e7 8d
48 01 41 89 0c 24 <4c> 89 34 c2 e8 41 f2 ff ff 49 89 c6 48 85 c0
75 8c 48 8b 44 24 10
<4> [188.935583] RSP: 0018:c900011dbcc8 EFLAGS: 00010202
<4> [188.935593] RAX: RBX: RCX:
0001
<4> [188.935603] RDX: 0010 RSI: 822e343c RDI:
c900011dbcc8
<4> [188.935613] RBP: c900011dbd48 R08: 88812d255bb8 R09:
fffe
<4> [188.935623] R10: 0001 R11: R12:
c900011dbd44
<4> [188.935633] R13: c900011dbd50 R14: 888113d29cc0 R15:
<4> [188.935643] FS: 7f68d17e9700()
GS:88827790() knlGS:
<4> [188.935655] CS: 0010 DS: ES: CR0: 80050033
<4> [188.935665] CR2: 0010 CR3: 00012d0a4000 CR4:
003506e0
<4> [188.935676] Call Trace:
<4> [188.935685] i915_gem_object_wait+0x1ff/0x410 [i915]
<4> [188.935988] i915_gem_wait_ioctl+0xf2/0x2a0 [i915]
<4> [188.936272] ? i915_gem_object_wait+0x410/0x410 [i915]
<4> [188.936533] drm_ioctl_kernel+0xae/0x140
<4> [188.936546] drm_ioctl+0x201/0x3d0
<4> [188.936555] ? i915_gem_object_wait+0x410/0x410 [i915]
<4> [188.936820] ? __fget_files+0xc2/0x1c0
<4> [188.936830] ? __fget_files+0xda/0x1c0
<4> [188.936839] __x64_sys_ioctl+0x6d/0xa0
<4> [188.936848] do_syscall_64+0x3a/0xb0
<4> [188.936859] entry_SYSCALL_64_after_hwframe+0x44/0xae
If the shared object has changed during the RCU unlocked period
callers will correctly handle the restart on the next iteration.
Signed-off-by: Tvrtko Ursulin
Fixes: 96601e8a4755 ("dma-buf: use new iterator in
dma_resv_copy_fences")
Fixes: d3c80698c9f5 ("dma-buf: use new iterator in
dma_resv_get_fences v3")
Closes:
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgitlab.freedesktop.org%2Fdrm%2Fintel%2F-%2Fissues%2F4274data=04%7C01%7Cchristian.koenig%40amd.com%7Cc22feea06a3f4285cdac08d98a495984%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637692870805160909%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000sdata=6oPR30sWnJe04I4GlhhvJWX3QvwKFIOMW1uOIyWZFOE%3Dreserved=0
Cc: Christian König
Cc: Daniel Vetter
Cc: Sumit Semwal
Cc: linux-me...@vger.kernel.org
Cc: dri-de...@lists.freedesktop.org
Cc: linaro-mm-...@lists.linaro.org
Maybe we should remove cursor->fences altogether, but either way
the patch is Reviewed-by: Christian König
Please push to drm-misc-next ASAP.
Not sure I can or if my push permissions are limited to Intel
branches. I can try once CI gives a green light.
If it doesn't work just ping me and I will push it.
It finally passed CI but it looks like you'll need to push it:
Done.
Christian.
tursulin@tursulin-mobl2:~/wc/dim/src$ dim push-branch drm-misc-next
Enumerating objects: 15, done.
Counting objects: 100% (15/15), done.
Delta compression using up to 8 threads
Compressing objects: 100% (8/8), done.
Writing objects: 100% (8/8), 2.32 KiB | 593.00 KiB/s, done.
Total 8 (delta 7), reused 0 (delta 0), pack-reused 0
error: remote unpack failed: unable to create temporary object directory
To ssh://git.freedesktop.org/git/drm/drm-misc
! [remote rejected] drm-misc-next -> drm-misc-next
(unpacker error)
error: failed to push some refs to
'ssh://git.freedesktop.org/git/drm/drm-misc'
Regards,
Tvrtko
___
Re: [Intel-gfx] [PATCH] drm/i915: Prefer struct_size over open coded arithmetic
Hi, On Sun, Oct 03, 2021 at 12:42:58PM +0200, Len Baker wrote: > As noted in the "Deprecated Interfaces, Language Features, Attributes, > and Conventions" documentation [1], size calculations (especially > multiplication) should not be performed in memory allocator (or similar) > function arguments due to the risk of them overflowing. This could lead > to values wrapping around and a smaller allocation being made than the > caller was expecting. Using those allocations could lead to linear > overflows of heap memory and other misbehaviors. > > In this case these are not actually dynamic sizes: all the operands > involved in the calculation are constant values. However it is better to > refactor them anyway, just to keep the open-coded math idiom out of > code. > > So, add at the end of the struct i915_syncmap a union with two flexible > array members (these arrays share the same memory layout). This is > possible using the new DECLARE_FLEX_ARRAY macro. And then, use the > struct_size() helper to do the arithmetic instead of the argument > "size + count * size" in the kmalloc and kzalloc() functions. > > Also, take the opportunity to refactor the __sync_seqno and __sync_child > making them more readable. > > This code was detected with the help of Coccinelle and audited and fixed > manually. > > [1] > https://www.kernel.org/doc/html/latest/process/deprecated.html#open-coded-arithmetic-in-allocator-arguments > > Signed-off-by: Len Baker > --- > drivers/gpu/drm/i915/i915_syncmap.c | 12 > 1 file changed, 8 insertions(+), 4 deletions(-) I received a mail telling that this patch doesn't build: == Series Details == Series: drm/i915: Prefer struct_size over open coded arithmetic URL : https://patchwork.freedesktop.org/series/95408/ State : failure But it builds without error against linux-next (tag next-20211001). Against which tree and branch do I need to build? Regards, Len
Re: [Intel-gfx] [PATCH] dma-resv: Fix dma_resv_get_fences and dma_resv_copy_fences after conversion
On 08/10/2021 13:19, Christian König wrote:
Am 08.10.21 um 12:49 schrieb Tvrtko Ursulin:
On 08/10/2021 11:21, Christian König wrote:
Am 08.10.21 um 11:50 schrieb Tvrtko Ursulin:
From: Tvrtko Ursulin
Cache the count of shared fences in the iterator to avoid dereferencing
the dma_resv_object outside the RCU protection. Otherwise iterator
and its
users can observe an incosistent state which makes it impossible to use
safely.
Ah, of course! I've been staring at the code the whole morning and
couldn't see it.
Going to write a testcase to cover that.
Such as:
<6> [187.517041] [IGT] gem_sync: executing
<7> [187.536343] i915 :00:02.0:
[drm:i915_gem_context_create_ioctl [i915]] HW context 1 created
<7> [187.536793] i915 :00:02.0:
[drm:i915_gem_context_create_ioctl [i915]] HW context 1 created
<6> [187.551235] [IGT] gem_sync: starting subtest basic-many-each
<1> [188.935462] BUG: kernel NULL pointer dereference, address:
0010
<1> [188.935485] #PF: supervisor write access in kernel mode
<1> [188.935495] #PF: error_code(0x0002) - not-present page
<6> [188.935504] PGD 0 P4D 0
<4> [188.935512] Oops: 0002 [#1] PREEMPT SMP NOPTI
<4> [188.935521] CPU: 2 PID: 1467 Comm: gem_sync Not tainted
5.15.0-rc4-CI-Patchwork_21264+ #1
<4> [188.935535] Hardware name: /NUC6CAYB, BIOS
AYAPLCEL.86A.0049.2018.0508.1356 05/08/2018
<4> [188.935546] RIP: 0010:dma_resv_get_fences+0x116/0x2d0
<4> [188.935560] Code: 10 85 c0 7f c9 be 03 00 00 00 e8 15 8b df ff
eb bd e8 8e c6 ff ff eb b6 41 8b 04 24 49 8b 55 00 48 89 e7 8d 48 01
41 89 0c 24 <4c> 89 34 c2 e8 41 f2 ff ff 49 89 c6 48 85 c0 75 8c 48
8b 44 24 10
<4> [188.935583] RSP: 0018:c900011dbcc8 EFLAGS: 00010202
<4> [188.935593] RAX: RBX: RCX:
0001
<4> [188.935603] RDX: 0010 RSI: 822e343c RDI:
c900011dbcc8
<4> [188.935613] RBP: c900011dbd48 R08: 88812d255bb8 R09:
fffe
<4> [188.935623] R10: 0001 R11: R12:
c900011dbd44
<4> [188.935633] R13: c900011dbd50 R14: 888113d29cc0 R15:
<4> [188.935643] FS: 7f68d17e9700()
GS:88827790() knlGS:
<4> [188.935655] CS: 0010 DS: ES: CR0: 80050033
<4> [188.935665] CR2: 0010 CR3: 00012d0a4000 CR4:
003506e0
<4> [188.935676] Call Trace:
<4> [188.935685] i915_gem_object_wait+0x1ff/0x410 [i915]
<4> [188.935988] i915_gem_wait_ioctl+0xf2/0x2a0 [i915]
<4> [188.936272] ? i915_gem_object_wait+0x410/0x410 [i915]
<4> [188.936533] drm_ioctl_kernel+0xae/0x140
<4> [188.936546] drm_ioctl+0x201/0x3d0
<4> [188.936555] ? i915_gem_object_wait+0x410/0x410 [i915]
<4> [188.936820] ? __fget_files+0xc2/0x1c0
<4> [188.936830] ? __fget_files+0xda/0x1c0
<4> [188.936839] __x64_sys_ioctl+0x6d/0xa0
<4> [188.936848] do_syscall_64+0x3a/0xb0
<4> [188.936859] entry_SYSCALL_64_after_hwframe+0x44/0xae
If the shared object has changed during the RCU unlocked period
callers will correctly handle the restart on the next iteration.
Signed-off-by: Tvrtko Ursulin
Fixes: 96601e8a4755 ("dma-buf: use new iterator in
dma_resv_copy_fences")
Fixes: d3c80698c9f5 ("dma-buf: use new iterator in
dma_resv_get_fences v3")
Closes:
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgitlab.freedesktop.org%2Fdrm%2Fintel%2F-%2Fissues%2F4274data=04%7C01%7Cchristian.koenig%40amd.com%7Cc22feea06a3f4285cdac08d98a495984%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637692870805160909%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000sdata=6oPR30sWnJe04I4GlhhvJWX3QvwKFIOMW1uOIyWZFOE%3Dreserved=0
Cc: Christian König
Cc: Daniel Vetter
Cc: Sumit Semwal
Cc: linux-me...@vger.kernel.org
Cc: dri-de...@lists.freedesktop.org
Cc: linaro-mm-...@lists.linaro.org
Maybe we should remove cursor->fences altogether, but either way the
patch is Reviewed-by: Christian König
Please push to drm-misc-next ASAP.
Not sure I can or if my push permissions are limited to Intel
branches. I can try once CI gives a green light.
If it doesn't work just ping me and I will push it.
It finally passed CI but it looks like you'll need to push it:
tursulin@tursulin-mobl2:~/wc/dim/src$ dim push-branch drm-misc-next
Enumerating objects: 15, done.
Counting objects: 100% (15/15), done.
Delta compression using up to 8 threads
Compressing objects: 100% (8/8), done.
Writing objects: 100% (8/8), 2.32 KiB | 593.00 KiB/s, done.
Total 8 (delta 7), reused 0 (delta 0), pack-reused 0
error: remote unpack failed: unable to create temporary object directory
To ssh://git.freedesktop.org/git/drm/drm-misc
! [remote rejected] drm-misc-next -> drm-misc-next (unpacker error)
error: failed to push some refs to 'ssh://git.freedesktop.org/git/drm/drm-misc'
Regards,
Tvrtko
[Intel-gfx] ✓ Fi.CI.IGT: success for dma-resv: Fix dma_resv_get_fences and dma_resv_copy_fences after conversion (rev4)
== Series Details == Series: dma-resv: Fix dma_resv_get_fences and dma_resv_copy_fences after conversion (rev4) URL : https://patchwork.freedesktop.org/series/95605/ State : success == Summary == CI Bug Log - changes from CI_DRM_10712_full -> Patchwork_21303_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_21303_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_create@create-massive: - shard-skl: NOTRUN -> [DMESG-WARN][1] ([i915#3002]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21303/shard-skl5/igt@gem_cre...@create-massive.html * igt@gem_ctx_persistence@legacy-engines-mixed: - shard-snb: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#1099]) +5 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21303/shard-snb6/igt@gem_ctx_persiste...@legacy-engines-mixed.html * igt@gem_ctx_persistence@many-contexts: - shard-tglb: [PASS][3] -> [FAIL][4] ([i915#2410]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10712/shard-tglb1/igt@gem_ctx_persiste...@many-contexts.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21303/shard-tglb2/igt@gem_ctx_persiste...@many-contexts.html * igt@gem_eio@unwedge-stress: - shard-tglb: [PASS][5] -> [TIMEOUT][6] ([i915#2369] / [i915#3063] / [i915#3648]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10712/shard-tglb6/igt@gem_...@unwedge-stress.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21303/shard-tglb7/igt@gem_...@unwedge-stress.html - shard-snb: NOTRUN -> [FAIL][7] ([i915#3354]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21303/shard-snb2/igt@gem_...@unwedge-stress.html * igt@gem_exec_fair@basic-none@rcs0: - shard-iclb: [PASS][8] -> [FAIL][9] ([i915#2842]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10712/shard-iclb7/igt@gem_exec_fair@basic-n...@rcs0.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21303/shard-iclb8/igt@gem_exec_fair@basic-n...@rcs0.html * igt@gem_exec_fair@basic-pace@rcs0: - shard-kbl: [PASS][10] -> [FAIL][11] ([i915#2842]) +3 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10712/shard-kbl4/igt@gem_exec_fair@basic-p...@rcs0.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21303/shard-kbl4/igt@gem_exec_fair@basic-p...@rcs0.html * igt@gem_exec_fair@basic-pace@vecs0: - shard-tglb: [PASS][12] -> [FAIL][13] ([i915#2842]) +1 similar issue [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10712/shard-tglb3/igt@gem_exec_fair@basic-p...@vecs0.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21303/shard-tglb8/igt@gem_exec_fair@basic-p...@vecs0.html * igt@gem_exec_flush@basic-batch-kernel-default-cmd: - shard-snb: NOTRUN -> [SKIP][14] ([fdo#109271]) +393 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21303/shard-snb2/igt@gem_exec_fl...@basic-batch-kernel-default-cmd.html * igt@gem_exec_whisper@basic-queues-forked-all: - shard-glk: [PASS][15] -> [DMESG-WARN][16] ([i915#118]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10712/shard-glk7/igt@gem_exec_whis...@basic-queues-forked-all.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21303/shard-glk9/igt@gem_exec_whis...@basic-queues-forked-all.html * igt@gem_pread@exhaustion: - shard-snb: NOTRUN -> [WARN][17] ([i915#2658]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21303/shard-snb6/igt@gem_pr...@exhaustion.html - shard-kbl: NOTRUN -> [WARN][18] ([i915#2658]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21303/shard-kbl4/igt@gem_pr...@exhaustion.html * igt@gem_render_copy@x-tiled-to-vebox-yf-tiled: - shard-kbl: NOTRUN -> [SKIP][19] ([fdo#109271]) +87 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21303/shard-kbl6/igt@gem_render_c...@x-tiled-to-vebox-yf-tiled.html * igt@gem_softpin@evict-snoop-interruptible: - shard-tglb: NOTRUN -> [SKIP][20] ([fdo#109312]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21303/shard-tglb3/igt@gem_soft...@evict-snoop-interruptible.html * igt@gem_softpin@noreloc-s3: - shard-apl: [PASS][21] -> [DMESG-WARN][22] ([i915#180]) +2 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10712/shard-apl8/igt@gem_soft...@noreloc-s3.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21303/shard-apl3/igt@gem_soft...@noreloc-s3.html * igt@gem_userptr_blits@vma-merge: - shard-snb: NOTRUN -> [FAIL][23] ([i915#2724]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21303/shard-snb6/igt@gem_userptr_bl...@vma-merge.html
Re: [Intel-gfx] [PATCH 2/2] drm/i915/pmu: Connect engine busyness stats from GuC to pmu
On 07/10/2021 23:55, Umesh Nerlige Ramappa wrote:
With GuC handling scheduling, i915 is not aware of the time that a
context is scheduled in and out of the engine. Since i915 pmu relies on
this info to provide engine busyness to the user, GuC shares this info
with i915 for all engines using shared memory. For each engine, this
info contains:
- total busyness: total time that the context was running (total)
- id: id of the running context (id)
- start timestamp: timestamp when the context started running (start)
At the time (now) of sampling the engine busyness, if the id is valid
(!= ~0), and start is non-zero, then the context is considered to be
active and the engine busyness is calculated using the below equation
engine busyness = total + (now - start)
All times are obtained from the gt clock base. For inactive contexts,
engine busyness is just equal to the total.
The start and total values provided by GuC are 32 bits and wrap around
in a few minutes. Since perf pmu provides busyness as 64 bit
monotonically increasing values, there is a need for this implementation
to account for overflows and extend the time to 64 bits before returning
busyness to the user. In order to do that, a worker runs periodically at
frequency = 1/8th the time it takes for the timestamp to wrap. As an
example, that would be once in 27 seconds for a gt clock frequency of
19.2 MHz.
Note:
There might be an overaccounting of busyness due to the fact that GuC
may be updating the total and start values while kmd is reading them.
(i.e kmd may read the updated total and the stale start). In such a
case, user may see higher busyness value followed by smaller ones which
would eventually catch up to the higher value.
v2: (Tvrtko)
- Include details in commit message
- Move intel engine busyness function into execlist code
- Use union inside engine->stats
- Use natural type for ping delay jiffies
- Drop active_work condition checks
- Use for_each_engine if iterating all engines
- Drop seq locking, use spinlock at guc level to update engine stats
- Document worker specific details
v3: (Tvrtko/Umesh)
- Demarcate guc and execlist stat objects with comments
- Document known over-accounting issue in commit
- Provide a consistent view of guc state
- Add hooks to gt park/unpark for guc busyness
- Stop/start worker in gt park/unpark path
- Drop inline
- Move spinlock and worker inits to guc initialization
- Drop helpers that are called only once
v4: (Tvrtko/Matt/Umesh)
- Drop addressed opens from commit message
- Get runtime pm in ping, remove from the park path
- Use cancel_delayed_work_sync in disable_submission path
- Update stats during reset prepare
- Skip ping if reset in progress
- Explicitly name execlists and guc stats objects
- Since disable_submission is called from many places, move resetting
stats to intel_guc_submission_reset_prepare
Signed-off-by: John Harrison
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 28 +--
drivers/gpu/drm/i915/gt/intel_engine_types.h | 33 ++-
.../drm/i915/gt/intel_execlists_submission.c | 34 +++
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 2 +
.../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h | 1 +
drivers/gpu/drm/i915/gt/uc/intel_guc.h| 26 ++
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c| 21 ++
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.h| 5 +
drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 13 +
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 238 ++
.../gpu/drm/i915/gt/uc/intel_guc_submission.h | 2 +
drivers/gpu/drm/i915/i915_reg.h | 2 +
12 files changed, 377 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 38436f4b5706..6b783fdcba2a 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1873,23 +1873,6 @@ void intel_engine_dump(struct intel_engine_cs *engine,
intel_engine_print_breadcrumbs(engine, m);
}
-static ktime_t __intel_engine_get_busy_time(struct intel_engine_cs *engine,
- ktime_t *now)
-{
- struct intel_engine_execlists_stats *stats = >stats.execlists;
- ktime_t total = stats->total;
-
- /*
-* If the engine is executing something at the moment
-* add it to the total.
-*/
- *now = ktime_get();
- if (READ_ONCE(stats->active))
- total = ktime_add(total, ktime_sub(*now, stats->start));
-
- return total;
-}
-
/**
* intel_engine_get_busy_time() - Return current accumulated engine busyness
* @engine: engine to report on
@@ -1899,16 +1882,7 @@ static ktime_t __intel_engine_get_busy_time(struct
intel_engine_cs *engine,
*/
ktime_t intel_engine_get_busy_time(struct intel_engine_cs *engine, ktime_t
*now)
{
- struct intel_engine_execlists_stats *stats = >stats.execlists;
-
[Intel-gfx] ✓ Fi.CI.BAT: success for dma-resv: Fix dma_resv_get_fences and dma_resv_copy_fences after conversion (rev4)
== Series Details == Series: dma-resv: Fix dma_resv_get_fences and dma_resv_copy_fences after conversion (rev4) URL : https://patchwork.freedesktop.org/series/95605/ State : success == Summary == CI Bug Log - changes from CI_DRM_10712 -> Patchwork_21303 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21303/index.html Known issues Here are the changes found in Patchwork_21303 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live@hangcheck: - fi-snb-2600:[PASS][1] -> [INCOMPLETE][2] ([i915#3921]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10712/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21303/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html * igt@kms_chamelium@dp-crc-fast: - fi-kbl-7500u: [PASS][3] -> [FAIL][4] ([i915#1372]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10712/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21303/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html * igt@kms_flip@basic-plain-flip@c-dp1: - fi-cfl-8109u: [PASS][5] -> [FAIL][6] ([i915#4165]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10712/fi-cfl-8109u/igt@kms_flip@basic-plain-f...@c-dp1.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21303/fi-cfl-8109u/igt@kms_flip@basic-plain-f...@c-dp1.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b: - fi-cfl-8109u: [PASS][7] -> [DMESG-WARN][8] ([i915#295]) +14 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10712/fi-cfl-8109u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-b.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21303/fi-cfl-8109u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-b.html Possible fixes * igt@gem_exec_suspend@basic-s0: - fi-tgl-1115g4: [FAIL][9] ([i915#1888]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10712/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21303/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s0.html [i915#1372]: https://gitlab.freedesktop.org/drm/intel/issues/1372 [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#295]: https://gitlab.freedesktop.org/drm/intel/issues/295 [i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921 [i915#4165]: https://gitlab.freedesktop.org/drm/intel/issues/4165 Participating hosts (40 -> 37) -- Missing(3): fi-ilk-m540 fi-bsw-cyan fi-hsw-4200u Build changes - * Linux: CI_DRM_10712 -> Patchwork_21303 CI-20190529: 20190529 CI_DRM_10712: 1b294c898346dc6c27264a2b900f7a7353b6bd96 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6241: 426723f979380f18f9c07d36ebac3a52f760ba7e @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_21303: 2ef0df1434bfc3a36bd9acf3f045a75520ae6acb @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 2ef0df1434bf dma-resv: Fix dma_resv_get_fences and dma_resv_copy_fences after conversion == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21303/index.html
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for dma-resv: Fix dma_resv_get_fences and dma_resv_copy_fences after conversion (rev4)
== Series Details == Series: dma-resv: Fix dma_resv_get_fences and dma_resv_copy_fences after conversion (rev4) URL : https://patchwork.freedesktop.org/series/95605/ State : warning == Summary == $ dim checkpatch origin/drm-tip 2ef0df1434bf dma-resv: Fix dma_resv_get_fences and dma_resv_copy_fences after conversion -:16: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #16: <7> [187.536343] i915 :00:02.0: [drm:i915_gem_context_create_ioctl [i915]] HW context 1 created total: 0 errors, 1 warnings, 0 checks, 57 lines checked
Re: [Intel-gfx] [PATCH v2 11/11] drm/i915/xehpsdv: Initialize multi-tiles
On 09/10/2021 00:33, Matt Roper wrote:
From: Tvrtko Ursulin
Check how many extra GT tiles are available on the system and setup
register access for all of them. We can detect how may GT tiles are
available by reading a register on the root tile. The same register
returns the tile ID on all tiles.
v2:
- Include some additional refactor that didn't get squashed in properly
on v1.
With v2 we should probably add Co-authored-by since, by a quick look,
seems half of the patch is no longer mine?
Regards,
Tvrtko
Bspec: 33407
Original-author: Abdiel Janulgue
Signed-off-by: Tvrtko Ursulin
Cc: Matthew Auld
Cc: Daniele Ceraolo Spurio
Cc: Joonas Lahtinen
Cc: Paulo Zanoni
Cc: Andi Shyti
Signed-off-by: Paulo Zanoni
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Michal Wajdeczko
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +-
drivers/gpu/drm/i915/gt/intel_gt.c| 83 +--
drivers/gpu/drm/i915/gt/intel_gt.h| 4 +-
drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 +
drivers/gpu/drm/i915/i915_drv.h | 7 +-
drivers/gpu/drm/i915/i915_pci.c | 40 +--
drivers/gpu/drm/i915/i915_reg.h | 4 ++
drivers/gpu/drm/i915/intel_device_info.h | 15
8 files changed, 145 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 2ae57e4656a3..1d9fcf9572ca 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -525,7 +525,7 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt
*gt)
u16 vdbox_mask;
u16 vebox_mask;
- info->engine_mask = INTEL_INFO(i915)->platform_engine_mask;
+ GEM_BUG_ON(!info->engine_mask);
if (GRAPHICS_VER(i915) < 11)
return info->engine_mask;
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index 6528d21e68eb..0879e30ace7c 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -912,14 +912,17 @@ u32 intel_gt_read_register_fw(struct intel_gt *gt,
i915_reg_t reg)
return intel_uncore_read_fw(gt->uncore, reg);
}
-static int
-tile_setup(struct intel_gt *gt, unsigned int id, phys_addr_t phys_addr)
+int intel_tile_setup(struct intel_gt *gt, unsigned int id, phys_addr_t
phys_addr)
{
struct drm_i915_private *i915 = gt->i915;
struct intel_uncore *uncore;
struct intel_uncore_mmio_debug *mmio_debug;
int ret;
+ /* For Modern GENs size of GTTMMADR is 16MB (for each tile) */
+ if (GEM_WARN_ON(pci_resource_len(to_pci_dev(i915->drm.dev), 0) < (id +
1) * SZ_16M))
+ return -EINVAL;
+
if (id) {
uncore = kzalloc(sizeof(*uncore), GFP_KERNEL);
if (!uncore)
@@ -943,6 +946,16 @@ tile_setup(struct intel_gt *gt, unsigned int id,
phys_addr_t phys_addr)
if (ret)
return ret;
+ /* Which tile am I? default to zero on single tile systems */
+ if (HAS_REMOTE_TILES(i915)) {
+ u32 instance =
+ __raw_uncore_read32(gt->uncore, XEHPSDV_MTCFG_ADDR) &
+ TILE_NUMBER;
+
+ if (GEM_WARN_ON(instance != id))
+ return -ENXIO;
+ }
+
gt->phys_addr = phys_addr;
return 0;
@@ -958,25 +971,87 @@ static void tile_cleanup(struct intel_gt *gt)
}
}
+static unsigned int tile_count(struct drm_i915_private *i915)
+{
+ u32 mtcfg;
+
+ /*
+* We use raw MMIO reads at this point since the
+* MMIO vfuncs are not setup yet
+*/
+ mtcfg = __raw_uncore_read32(>uncore, XEHPSDV_MTCFG_ADDR);
+ return REG_FIELD_GET(TILE_COUNT, mtcfg) + 1;
+}
+
int intel_probe_gts(struct drm_i915_private *i915)
{
struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
+ const struct intel_gt_definition *gtdef;
+ struct intel_gt *gt;
phys_addr_t phys_addr;
unsigned int mmio_bar;
+ unsigned int i, tiles;
int ret;
mmio_bar = GRAPHICS_VER(i915) == 2 ? 1 : 0;
phys_addr = pci_resource_start(pdev, mmio_bar);
/* We always have at least one primary GT on any device */
- ret = tile_setup(>gt, 0, phys_addr);
+ gt = >gt;
+ gt->name = "Primary GT";
+ gt->info.engine_mask = INTEL_INFO(i915)->platform_engine_mask;
+
+ drm_dbg(>drm, "Setting up %s %u\n", gt->name, gt->info.id);
+ ret = intel_tile_setup(gt, 0, phys_addr);
if (ret)
return ret;
i915->gts[0] = >gt;
- /* TODO: add more tiles */
+ tiles = tile_count(i915);
+ drm_dbg(>drm, "Tile count: %u\n", tiles);
+
+ for (gtdef = INTEL_INFO(i915)->extra_gts, i = 1;
+gtdef && i < tiles;
+gtdef++, i++) {
+ if (GEM_WARN_ON(i >= I915_MAX_GTS)) {
+ ret = -EINVAL;
+
