On Tue, Oct 17, 2023, at 00:10, Andi Shyti wrote:
> Hi Arnd,
>
>> static void rc6_res_reg_init(struct intel_rc6 *rc6)
>> {
>> -memset(rc6->res_reg, INVALID_MMIO_REG.reg, sizeof(rc6->res_reg));
>
> This is a complex initialization, indeed... how about just
>
>memset(rc6->res_reg, 0,
== Series Details ==
Series: drm/i915/mtl: avoid stringop-overflow warning (rev3)
URL : https://patchwork.freedesktop.org/series/125198/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13763 -> Patchwork_125198v3
Summary
== Series Details ==
Series: drm/i915/mtl: avoid stringop-overflow warning (rev3)
URL : https://patchwork.freedesktop.org/series/125198/
State : warning
== Summary ==
Error: dim checkpatch failed
2de375bf1f63 drm/i915/mtl: avoid stringop-overflow warning
-:6: WARNING:COMMIT_LOG_LONG_LINE:
== Series Details ==
Series: drm/i915: Define and use GuC and CTB TLB invalidation routines (rev3)
URL : https://patchwork.freedesktop.org/series/125177/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13763 -> Patchwork_125177v3
== Series Details ==
Series: drm/i915: Define and use GuC and CTB TLB invalidation routines (rev3)
URL : https://patchwork.freedesktop.org/series/125177/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915: Define and use GuC and CTB TLB invalidation routines (rev3)
URL : https://patchwork.freedesktop.org/series/125177/
State : warning
== Summary ==
Error: dim checkpatch failed
163a738cf408 drm/i915: Add GuC TLB Invalidation device info flags
2804b180223e
== Series Details ==
Series: drm/i915/gvt: Optimize mmio_offset_compare() for efficiency (rev3)
URL : https://patchwork.freedesktop.org/series/125181/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13763 -> Patchwork_125181v3
== Series Details ==
Series: drm/i915: Prevent potential null-ptr-deref in engine_init_common (rev6)
URL : https://patchwork.freedesktop.org/series/124971/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13763 -> Patchwork_124971v6
== Series Details ==
Series: drm/i915/display: Reset message bus after each read/write operation
(rev4)
URL : https://patchwork.freedesktop.org/series/124602/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13763 -> Patchwork_124602v4
== Series Details ==
Series: drm/i915: Move the g45 PEG band gap HPD workaround to the HPD code
(rev4)
URL : https://patchwork.freedesktop.org/series/125053/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13763 -> Patchwork_125053v4
== Series Details ==
Series: drm/i915/bios: Clamp VBT HDMI level shift on BDW (rev3)
URL : https://patchwork.freedesktop.org/series/125120/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13763 -> Patchwork_125120v3
Summary
== Series Details ==
Series: drm/i915: Define and use GuC and CTB TLB invalidation routines (rev2)
URL : https://patchwork.freedesktop.org/series/125177/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13763 -> Patchwork_125177v2
== Series Details ==
Series: drm/i915: Define and use GuC and CTB TLB invalidation routines (rev2)
URL : https://patchwork.freedesktop.org/series/125177/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915: Define and use GuC and CTB TLB invalidation routines (rev2)
URL : https://patchwork.freedesktop.org/series/125177/
State : warning
== Summary ==
Error: dim checkpatch failed
acdcc1363f96 drm/i915: Add GuC TLB Invalidation device info flags
e74140ccddc9
On 10/16/2023 4:24 PM, John Harrison wrote:
On 10/16/2023 15:55, Vinay Belgaumkar wrote:
This bit does not cause an explicit L3 flush. We already use
At all? Or only on newer hardware? And as a genuine spec change or as
a bug / workaround?
If the hardware has re-purposed the bit then it is
On 10/16/2023 15:55, Vinay Belgaumkar wrote:
This bit does not cause an explicit L3 flush. We already use
At all? Or only on newer hardware? And as a genuine spec change or as a
bug / workaround?
If the hardware has re-purposed the bit then it is probably worth at
least adding a comment to
This bit does not cause an explicit L3 flush. We already use
PIPE_CONTROL_DC_FLUSH_ENABLE for that purpose.
Cc: Nirmoy Das
Cc: Mikka Kuoppala
Signed-off-by: Vinay Belgaumkar
---
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git
Hi Arnd,
> static void rc6_res_reg_init(struct intel_rc6 *rc6)
> {
> - memset(rc6->res_reg, INVALID_MMIO_REG.reg, sizeof(rc6->res_reg));
This is a complex initialization, indeed... how about just
memset(rc6->res_reg, 0, sizeof(rc6->res_reg));
> + i915_reg_t
From: Arnd Bergmann
The newly added memset() causes a warning for some reason I could not figure
out:
In file included from arch/x86/include/asm/string.h:3,
from drivers/gpu/drm/i915/gt/intel_rc6.c:6:
In function 'rc6_res_reg_init',
inlined from 'intel_rc6_init' at
On Mon, Oct 16, 2023 at 03:55:44PM +0300, Mika Kahola wrote:
> Every know and then we receive the following error when running
> for example IGT test kms_flip.
>
> [drm] *ERROR* PHY G Read 0d80 failed after 3 retries.
> [drm] *ERROR* PHY G Write 0d81 failed after 3 retries.
>
> Since the error
On Mon, Oct 16, 2023 at 09:02:38AM +0100, Tvrtko Ursulin wrote:
>
> On 13/10/2023 21:51, Rodrigo Vivi wrote:
> > On Thu, Sep 28, 2023 at 01:48:34PM +0100, Tvrtko Ursulin wrote:
> > >
> > > On 27/09/2023 20:34, Belgaumkar, Vinay wrote:
> > > >
> > > > On 9/21/2023 3:41 AM, Tvrtko Ursulin wrote:
The original code used conditional branching in the mmio_offset_compare
function to compare two values and return -1, 1, or 0 based on the
result. However, the list_sort comparison function only needs results
<0, >0, or =0. This patch optimizes the code to make the comparison
branchless, improving
The original code used conditional branching in the mmio_offset_compare
function to compare two values and return -1, 1, or 0 based on the
result. However, the list_sort comparison function only needs results
<0, >0, or =0. This patch optimizes the code to make the comparison
branchless, improving
On Thu, Oct 12, 2023 at 06:12:26PM +0200, Greg KH wrote:
> On Thu, Oct 12, 2023 at 04:53:38PM +0300, Ville Syrjälä wrote:
> > On Thu, Oct 12, 2023 at 03:40:08PM +0200, Greg KH wrote:
> > > On Thu, Oct 12, 2023 at 04:28:01PM +0300, Ville Syrjala wrote:
> > > > From: Ville Syrjälä
> > > >
> > > >
On Fri, Oct 13, 2023 at 12:53:59PM +0200, Andi Shyti wrote:
> Hi Ville,
>
> > If we can't find a free fence register to handle a fault in the GMADR
> > range just return VM_FAULT_NOPAGE without populating the PTE so that
> > userspace will retry the access and trigger another fault. Eventually
>
-Original Message-
From: Cavitt, Jonathan
Sent: Monday, October 16, 2023 7:51 AM
To: intel-gfx@lists.freedesktop.org
Cc: Gupta, saurabhg ; Cavitt, Jonathan
; chris.p.wil...@linux.intel.com; Iddamsetty,
Aravind ; Yang, Fei ; Shyti,
Andi ; Harrison, John C ; Das,
Nirmoy ; Krzysztofik,
Enable GuC TLB invalidations for MTL. Though more platforms than just
MTL support GuC TLB invalidations, MTL is presently the only platform
that requires it for any purpose, so only enable it there for now to
minimize cross-platform impact.
Signed-off-by: Jonathan Cavitt
Reviewed-by: Andi Shyti
From: Prathap Kumar Valsan
The GuC firmware had defined the interface for Translation Look-Aside
Buffer (TLB) invalidation. We should use this interface when
invalidating the engine and GuC TLBs.
Add additional functionality to intel_gt_invalidate_tlb, invalidating
the GuC TLBs and falling back
Implement GuC-based TLB invalidations and use them on MTL.
Some complexity in the implementation was introduced early on
and will be required for range-based TLB invalidations.
RFC: https://patchwork.freedesktop.org/series/124922/
v2:
- Add missing supporting patches.
v3:
- Split suspend/resume
For the gt_tlb live selftest, when operating on the GSC engine,
increase the timeout from 10 ms to 200 ms because the GSC
engine is a bit slower than the rest.
Signed-off-by: Jonathan Cavitt
Reviewed-by: Andi Shyti
Acked-by: Tvrtko Ursulin
Reviewed-by: Nirmoy Das
---
It is not an error for GuC TLB invalidations to fail when the GT is
wedged or disabled, so do not process a wait failure as one in
guc_send_invalidate_tlb.
Signed-off-by: Fei Yang
Signed-off-by: Jonathan Cavitt
CC: John Harrison
Reviewed-by: Andi Shyti
Acked-by: Tvrtko Ursulin
Acked-by:
In case of GT is suspended, don't allow submission of new TLB invalidation
request and cancel all pending requests. The TLB entries will be
invalidated either during GuC reload or on system resume.
Signed-off-by: Fei Yang
Signed-off-by: Jonathan Cavitt
CC: John Harrison
Reviewed-by: Andi Shyti
As of now, there is no mechanism for tracking a given request's
progress through the queue. Instead, add a helper that returns
an estimated maximum time the queue should take to drain if
completely full.
Suggested-by: John Harrison
Signed-off-by: Jonathan Cavitt
Reviewed-by: Andi Shyti
Add device info flags for if GuC TLB Invalidation is enabled.
Signed-off-by: Jonathan Cavitt
Reviewed-by: Andi Shyti
Acked-by: Tvrtko Ursulin
Reviewed-by: Nirmoy Das
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/intel_device_info.h | 1 +
2 files changed, 3
On Sat, Oct 14, 2023 at 05:20:12AM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: Store DSC DPCD capabilities in the connector (rev9)
> URL : https://patchwork.freedesktop.org/series/124723/
> State : failure
Thanks for the reviews, I pushed the patchset.
The failure is
Every know and then we receive the following error when running
for example IGT test kms_flip.
[drm] *ERROR* PHY G Read 0d80 failed after 3 retries.
[drm] *ERROR* PHY G Write 0d81 failed after 3 retries.
Since the error is sporadic in nature, the patch proposes
to reset the message bus after
== Series Details ==
Series: Framework for display parameters (rev3)
URL : https://patchwork.freedesktop.org/series/124645/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13758 -> Patchwork_124645v3
Summary
---
== Series Details ==
Series: Framework for display parameters (rev3)
URL : https://patchwork.freedesktop.org/series/124645/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: Framework for display parameters (rev3)
URL : https://patchwork.freedesktop.org/series/124645/
State : warning
== Summary ==
Error: dim checkpatch failed
b5f879154dd6 drm/i915/display: Add framework to add parameters specific to
display
Traceback (most recent
> -Original Message-
> From: Vivi, Rodrigo
> Sent: Friday, October 13, 2023 11:22 PM
> To: Kahola, Mika
> Cc: intel-gfx@lists.freedesktop.org; Sousa, Gustavo
> Subject: Re: [PATCH v2] drm/i915/display: Reset message bus after each
> read/write operation
>
> On Fri, Oct 13, 2023 at
Also make module parameter as non writable.
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_display.h | 2 +-
drivers/gpu/drm/i915/i915_params.c | 3 +--
2 files changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.h
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_display_device.c | 2 +-
drivers/gpu/drm/i915/display/intel_display_params.c | 3 +++
drivers/gpu/drm/i915/display/intel_display_params.h | 1 +
drivers/gpu/drm/i915/i915_params.c | 3 ---
Generally we have writable device parameters in debugfs. No need
to allow writing module parameters.
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_display_params.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_display.h| 2 +-
drivers/gpu/drm/i915/display/intel_display_params.c | 3 +++
drivers/gpu/drm/i915/display/intel_display_params.h | 1 +
drivers/gpu/drm/i915/i915_params.c | 3 ---
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_display_params.c | 3 +++
drivers/gpu/drm/i915/display/intel_display_params.h | 1 +
drivers/gpu/drm/i915/display/intel_dp.c | 6 +++---
drivers/gpu/drm/i915/i915_params.c | 3 ---
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_display_params.c | 5 +
drivers/gpu/drm/i915/display/intel_display_params.h | 1 +
drivers/gpu/drm/i915/display/intel_display_power.c | 2 +-
drivers/gpu/drm/i915/i915_params.c | 5 -
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_display_device.c | 3 ++-
drivers/gpu/drm/i915/display/intel_display_params.c | 3 +++
drivers/gpu/drm/i915/display/intel_display_params.h | 1 +
drivers/gpu/drm/i915/i915_params.c | 3 ---
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_display_params.c | 3 +++
drivers/gpu/drm/i915/display/intel_display_params.h | 1 +
drivers/gpu/drm/i915/display/intel_dpt.c| 6 --
drivers/gpu/drm/i915/display/intel_fb.c | 2 +-
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_backlight.c | 9 +
drivers/gpu/drm/i915/display/intel_display_params.c | 9 -
drivers/gpu/drm/i915/display/intel_display_params.h | 1 +
drivers/gpu/drm/i915/i915_params.c | 7 ---
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_crt.c| 4 ++--
drivers/gpu/drm/i915/display/intel_display_params.c | 4
drivers/gpu/drm/i915/display/intel_display_params.h | 1 +
drivers/gpu/drm/i915/i915_params.c | 4
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_display_params.c | 4
drivers/gpu/drm/i915/display/intel_display_params.h | 1 +
drivers/gpu/drm/i915/display/intel_display_reset.c | 2 +-
drivers/gpu/drm/i915/i915_params.c | 4
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_display_params.c | 4
drivers/gpu/drm/i915/display/intel_display_params.h | 1 +
drivers/gpu/drm/i915/display/intel_display_power.c | 12 ++--
drivers/gpu/drm/i915/i915_params.c | 4
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_bios.c | 2 +-
drivers/gpu/drm/i915/display/intel_display_params.c | 4
drivers/gpu/drm/i915/display/intel_display_params.h | 1 +
drivers/gpu/drm/i915/i915_params.c | 4
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_bios.c | 4 ++--
drivers/gpu/drm/i915/display/intel_display_params.c | 6 ++
drivers/gpu/drm/i915/display/intel_display_params.h | 1 +
drivers/gpu/drm/i915/i915_params.c | 6 --
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_display_params.c | 4
drivers/gpu/drm/i915/display/intel_display_params.h | 1 +
drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c | 4 ++--
drivers/gpu/drm/i915/i915_params.c| 4
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_display_params.c | 3 +++
drivers/gpu/drm/i915/display/intel_display_params.h | 1 +
drivers/gpu/drm/i915/display/skl_watermark.c| 5 +++--
drivers/gpu/drm/i915/i915_params.c | 3 ---
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/hsw_ips.c | 4 ++--
drivers/gpu/drm/i915/display/intel_display_params.c | 2 ++
drivers/gpu/drm/i915/display/intel_display_params.h | 1 +
drivers/gpu/drm/i915/i915_params.c | 2 --
Signed-off-by: Jouni Högander
---
.../gpu/drm/i915/display/intel_display_params.c | 15 +++
.../gpu/drm/i915/display/intel_display_params.h | 5 +
drivers/gpu/drm/i915/display/intel_psr.c | 14 +++---
drivers/gpu/drm/i915/i915_params.c| 15
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_display_params.c | 3 +++
drivers/gpu/drm/i915/display/intel_display_params.h | 1 +
drivers/gpu/drm/i915/display/intel_opregion.c | 2 +-
drivers/gpu/drm/i915/i915_params.c | 3 ---
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_display_params.c | 4
drivers/gpu/drm/i915/display/intel_display_params.h | 3 ++-
drivers/gpu/drm/i915/display/intel_lvds.c | 4 ++--
drivers/gpu/drm/i915/i915_params.c | 4
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_display_params.c | 4
drivers/gpu/drm/i915/display/intel_display_params.h | 1 +
drivers/gpu/drm/i915/display/intel_panel.c | 4 ++--
drivers/gpu/drm/i915/i915_params.c | 4
GPU error dump contained all module parameters. If we are moving
display parameters to intel_display_params.[ch] they are not dumped
into GPU error dump. This patch is adding moved display parameters
back to GPU error dump. Display parameters are also included in
i915_capabilities
v2: Add
Currently all module parameters are handled by i915_param.c/h. This
is a problem for display parameters when Xe driver is used. Add
a mechanism to add parameters specific to the display. This is mainly
copied from i915_[debugfs]_params.[ch]. Parameters are not yet moved. This
is done by subsequent
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/i9xx_wm.c | 2 +-
drivers/gpu/drm/i915/display/intel_display_params.c | 4
drivers/gpu/drm/i915/display/intel_display_params.h | 3 ++-
drivers/gpu/drm/i915/display/intel_fbc.c| 10 +-
Currently all module parameters are handled by i915_param.c/h. This
is a problem for display parameters when Xe driver is used.
This patch set adds a mechanism to add parameters specific to the
display. This is mainly copied from existing i915 parameters
implementation with some naming changes
== Series Details ==
Series: drm/i915/display: Use dma_fence interfaces instead of i915_sw_fence
URL : https://patchwork.freedesktop.org/series/125160/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13756 -> Patchwork_125160v1
Hi Alexander,
> +static int i915_spi_init_mtd(struct i915_spi *spi, struct device *device,
> + unsigned int nparts)
> +{
> + unsigned int i;
> + unsigned int n;
> + struct mtd_partition *parts = NULL;
> + int ret;
> +
> + dev_dbg(device, "registering
We are preparing for Xe driver. Xe driver doesn't have i915_sw_fence
implementation. Lets drop i915_sw_fence usage from display code and
use dma_fence interfaces directly.
For this purpose stack dma fences from related objects into old and new
plane states using drm_gem_plane_helper_prepare_fb.
On 13/10/2023 21:51, Rodrigo Vivi wrote:
On Thu, Sep 28, 2023 at 01:48:34PM +0100, Tvrtko Ursulin wrote:
On 27/09/2023 20:34, Belgaumkar, Vinay wrote:
On 9/21/2023 3:41 AM, Tvrtko Ursulin wrote:
On 20/09/2023 22:56, Vinay Belgaumkar wrote:
Provide a bit to disable waitboost while
Hi Andi,
On 10/14/2023 10:51 AM, Andi Shyti wrote:
Hi Nirmoy,
On Fri, Oct 13, 2023 at 03:44:39PM +0200, Nirmoy Das wrote:
gen8_ggtt_invalidate() is only needed for limited set of platforms
where GGTT is mapped as WC otherwise this can cause unwanted
side-effects on XE_HP platforms where
On 10/13/2023 6:15 PM, Daniel Vetter wrote:
On Fri, Oct 13, 2023 at 02:28:21PM +0200, Nirmoy Das wrote:
Hi Ville,
On 10/13/2023 12:50 PM, Ville Syrjälä wrote:
On Fri, Oct 13, 2023 at 12:31:40PM +0200, Nirmoy Das wrote:
gen8_ggtt_invalidate() is only needed for limitted set of platforms
== Series Details ==
Series: Add helper for range_bpg_offset and minor fixes
URL : https://patchwork.freedesktop.org/series/125159/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13756 -> Patchwork_125159v1
Summary
---
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