Ironlake is where the PCH split started.
Signed-off-by: Eric Anholt e...@anholt.net
---
drivers/gpu/drm/i915/intel_display.c | 361 ++
1 files changed, 150 insertions(+), 211 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915
On Wed, 30 Mar 2011 18:16:11 +0100, Chris Wilson ch...@chris-wilson.co.uk
wrote:
On Wed, 30 Mar 2011 09:59:55 -0700, Eric Anholt e...@anholt.net wrote:
On Wed, 30 Mar 2011 08:09:47 +0100, Chris Wilson ch...@chris-wilson.co.uk
wrote:
The series looks really good, only one quibble below
---
I don't have GT1 to test with. Does this fix VS regressions for
people with that hardware?
src/mesa/drivers/dri/i965/brw_context.c| 13 +++--
src/mesa/drivers/dri/i965/gen6_vs_state.c |2 +-
src/mesa/drivers/dri/i965/gen6_wm_state.c |2 +-
From: Chris Wilson ch...@chris-wilson.co.uk
Rely on the GPU snooping into the CPU cache for appropriately bound
objects on MI_FLUSH. Or perhaps one day we will have a cache-coherent
CPU/GPU package...
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
Signed-off-by: Eric Anholt e...@anholt.net
cachelines when required. However,
we start simple.
[v2: Move the set to uncached above the clflush. Otherwise, we'd skip
the clflush and try to scan out data that was still sitting in the
cache.]
Signed-off-by: Eric Anholt e...@anholt.net
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
toward those two.
Signed-off-by: Eric Anholt e...@anholt.net
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
Signed-off-by: Eric Anholt e...@anholt.net
---
drivers/gpu/drm/i915/i915_gem.c | 18 +-
1 files changed, 17 insertions(+), 1 deletions(-)
diff --git a/drivers/gpu/drm
On Mon, 28 Mar 2011 15:37:37 -0700, Ben Widawsky b...@bwidawsk.net wrote:
On Mon, Mar 28, 2011 at 10:55:40AM -0700, Eric Anholt wrote:
---
I suspect due to
FORCEWAKE, which also means that I can't necessarily trust that the
bit was unset originally), I got only hangs from 3D.
If you
On Tue, 22 Mar 2011 13:51:58 +, Chris Wilson ch...@chris-wilson.co.uk
wrote:
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
Again, needs more justification. For example, I would expect us not to
bother with the GTT on SNB pread/pwrite, and just read the backing pages
(they're in our
On Fri, 18 Mar 2011 08:22:16 -0700, Keith Packard kei...@keithp.com wrote:
On Fri, 18 Mar 2011 08:02:09 +, Chris Wilson ch...@chris-wilson.co.uk
wrote:
A broken implementation of is_pot() prevented the detection of when a
singular pipe was enabled.
- return mask (mask -mask)
On Thu, 17 Mar 2011 19:29:03 -0700, Ben Widawsky b...@bwidawsk.net wrote:
From: Ben Widawsky bwida...@gmail.com
Have the assembler support creating a byte array for binary blob-like
inclusion. In my case, to write some exception handler which is not
jit'd.
I don't have push access, so if
This provided a 10.4% +/- 1.5% (n=3) performance improvement on
openarena on my laptop. We have more room to improve with doing LLC
caching for display using GFDT, and in doing LLC+MLC caching, but this
was an easy performance win and incremental improvement toward those
two.
Signed-off-by: Eric
On Sat, 12 Mar 2011 04:47:23 +0800, Zou, Nanhai nanhai@intel.com wrote:
Like we have discussed.
I think set FB uncached, batch buffer and ring buffer LLC cached.
everything else LLC+MLC cached may get the best performance.
I don't see how batch or ring uncached should be faster than cache.
The specs say to do so.
Signed-off-by: Eric Anholt e...@anholt.net
---
This patch is not actually tested, it was just left in my tree from
rebasing it around since its previous submission. The change in this
version is that the NONE is actually the correct value (3, not 2).
drivers/gpu/drm
On Mon, 17 Jan 2011 17:38:23 +, Simon Farnsworth
simon.farnswo...@onelan.co.uk wrote:
In our application, the screen is never rotated from the point of view
of the driver; instead, the compositor applies a suitable rotation as
it composites the display. This works fine on 945, but on 965,
On Thu, 23 Dec 2010 12:30:29 +, Chris Wilson ch...@chris-wilson.co.uk
wrote:
On Thu, 23 Dec 2010 12:07:22 +, Chris Wilson ch...@chris-wilson.co.uk
wrote:
I tweaked the patch to pass the watermark structs through to the check
routine. The box survives s2ram, but I have now also
On Thu, 16 Dec 2010 09:51:51 +, Chris Wilson ch...@chris-wilson.co.uk
wrote:
On Thu, 16 Dec 2010 13:29:09 +0800, Zhenyu Wang zhen...@linux.intel.com
wrote:
Useful for debugging hang bug that not require GPU auto reset,
to grab INSTDONE bits and make aub dump life easy.
That has the
On Tue, 14 Dec 2010 18:19:30 +, Chris Wilson ch...@chris-wilson.co.uk
wrote:
On Tue, 14 Dec 2010 10:06:46 -0800, Eric Anholt e...@anholt.net wrote:
It's required by the specs, but we don't know why. Let's not find out
why.
Any feel at all for the level of impact of not disabling
On Tue, 14 Dec 2010 12:55:59 +0800, Zhenyu Wang zhen...@linux.intel.com wrote:
It appears Sandybridge PIPE_CONTROL write out buffer need
to be set as cached, currently LLC cached, in order to read
back correct counter. Otherwise I can always be possible to
get corrupted 64-bit PS_DEPTH_COUNT
It's required by the specs, but we don't know why. Let's not find out
why.
Signed-off-by: Eric Anholt e...@anholt.net
---
drivers/gpu/drm/i915/i915_reg.h |3 +++
drivers/gpu/drm/i915/intel_display.c |2 ++
2 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu
On Thu, 18 Nov 2010 09:32:58 +0800, Eric Anholt e...@anholt.net wrote:
The pipe is always set to 8BPC, but here we were leaving whatever
previous bits were set by the BIOS in place.
This series has now been tested on a DP system. We got flashing garbage
due to the BIOS having configured 6BPC
On Thu, 18 Nov 2010 14:53:24 +, Chris Wilson ch...@chris-wilson.co.uk
wrote:
Eric, only 3 patches (1, 5, 6) turned up in my inbox, can you either resend
these to me or push to your tree?
Sorry the formatting of the mails produced was confusing. The others
were the DP fixes and the comment
Signed-off-by: Eric Anholt e...@anholt.net
---
drivers/gpu/drm/i915/i915_drv.c |7 +--
1 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 57e892d..af2de29 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b
This has proven sufficient to recover from a hang of the GPU using the
gem_bad_blit test while at the KMS console then starting X. When
attempting the same during an X session, the timer doesn't appear to
trigger.
Signed-off-by: Eric Anholt e...@anholt.net
---
drivers/gpu/drm/i915/i915_drv.c
This only applies to Ironlake.
Signed-off-by: Eric Anholt e...@anholt.net
---
drivers/gpu/drm/i915/intel_dp.c | 21 +
1 files changed, 21 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index c8e0055..252bf7c
The specs say to do so.
Signed-off-by: Eric Anholt e...@anholt.net
---
drivers/gpu/drm/i915/i915_reg.h |1 +
drivers/gpu/drm/i915/intel_display.c |1 +
2 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
The pipe is always set to 8BPC, but here we were leaving whatever
previous bits were set by the BIOS in place.
Signed-off-by: Eric Anholt e...@anholt.net
---
drivers/gpu/drm/i915/i915_reg.h |1 +
drivers/gpu/drm/i915/intel_display.c |4 +++-
2 files changed, 4 insertions(+), 1
On Wed, 17 Nov 2010 04:25:25 +, Peter Clifton pc...@cam.ac.uk wrote:
After some discussion with Eric on IRC, this is what I came up with
(which appears to work!)
The other way (fix up dead code eliminator) ended up deleting the same
gen code while also deleting C code. As I thought about
On Sat, 06 Nov 2010 09:23:06 +, Peter Clifton pc...@cam.ac.uk wrote:
Fixes corruption with glBufferSubData on my machine,
Can someone review and push?
Looks good. Thanks!
pgpj9dGzySOaO.pgp
Description: PGP signature
___
Intel-gfx mailing list
This is not known to fix any particular bugs we have, but the spec
says to do it, and the BIOS hadn't already set it up on my system.
Signed-off-by: Eric Anholt e...@anholt.net
---
drivers/gpu/drm/i915/i915_reg.h | 13 +
drivers/gpu/drm/i915/intel_display.c |6 ++
2
On Mon, 01 Nov 2010 22:19:34 +, Peter Clifton pc...@cam.ac.uk wrote:
On Mon, 2010-11-01 at 14:41 -0700, Eric Anholt wrote:
I'm going to look at the case I think I hit an improvement for and
dissect _why_, then get back to you.
I'll check this again shortly.. (I recall I was testing
On Tue, 02 Nov 2010 20:20:14 +0800, ykzhao yakui.z...@intel.com wrote:
On Tue, 2010-11-02 at 04:23 +0800, Eric Anholt wrote:
Improves nexuiz performance by about 1% on my system.
CC: Arjan and linux-acpi mailing list.
It seems that the selection of C-state will become very sensitive to IO
This is the logical partner to the already exported io_schedule() and
schedule_timeout(), and will be used by the DRM.
Signed-off-by: Eric Anholt e...@anholt.net
---
kernel/sched.c |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/kernel/sched.c b/kernel/sched.c
index
This is a series I came up with as a result of KS discussions. The
plan was to pin the CPU C state to keep the GPU going as fast as
possible while it was active, since there's some relation between the
two (we don't know for sure yet, per chipset, whether it's due to
latency of DMA writes having
reduce memory bandwidth, which can
reduce GPU performance and increase the time we wait!
Signed-off-by: Eric Anholt e...@anholt.net
---
drivers/gpu/drm/i915/i915_gem.c |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915
-by: Eric Anholt e...@anholt.net
---
drivers/gpu/drm/i915/intel_display.c |7 +++
1 files changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 990f065..d7b0c7d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
On Mon, 1 Nov 2010 17:00:46 -0400, Andrew Lutomirski l...@mit.edu wrote:
Out of curiousity, what happened to ACPI_BM_BREAK_EN here:
https://bugs.freedesktop.org/show_bug.cgi?id=30364
On my box, that register is (according to setpci) 0x00, but I'm
testing on an ICH9M and I don't seem to be
On Sun, 31 Oct 2010 01:15:34 +, Peter Clifton pc...@cam.ac.uk wrote:
Hi guys,
I was just poking around looking for somewhere quick and dirty to shove
my new experimental DRM IOCTL for retrieving IDLE data from the GPU. I
was looking at the various breakpoints in the debugger, and found
On Tue, 26 Oct 2010 04:35:33 +0100, Peter Clifton pc...@cam.ac.uk wrote:
On Mon, 2010-10-25 at 12:44 -0700, Eric Anholt wrote:
So, what if the problem is that our URB allocations aren't big enough?
I would expect that to look kind of like what I'm seeing. One
experiment would be to go
On Fri, 20 Aug 2010 17:58:12 +0100, Chris Wilson ch...@chris-wilson.co.uk
wrote:
We were failing when trying to allocate the resource for MMIO of the
MCHBAR because we forgot to specify what type of resource we wanted.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
Cc: Jesse Barnes
On Sun, 22 Aug 2010 12:05:41 +0100, Chris Wilson ch...@chris-wilson.co.uk
wrote:
Only stop trying if the aux channel sucessfully reports that the
transmission was completed, otherwise try again. On the 5th failure,
bail and report that something is amiss.
This fixes a sporadic failure in
On Wed, 4 Aug 2010 15:52:19 +1000, Dave Airlie airl...@gmail.com wrote:
From: Dave Airlie airl...@redhat.com
Like on Sandybridge, disabling the DAC here when doing CRT load detect
avoids forever hangs waiting on the hardware.
test procedure on HP 2740p:
boot with no VGA plugged in, start
On Wed, 11 Aug 2010 10:31:33 +0100, Chris Wilson ch...@chris-wilson.co.uk
wrote:
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
Without breaking out the docs, I don't know what this does. Better
commit message?
pgpwuoDZxJ5oL.pgp
Description: PGP signature
On Wed, 18 Aug 2010 12:00:29 -0700, Jesse Barnes jbar...@virtuousgeek.org
wrote:
This set replaces the last one, and includes an additional patch to fix
our vblank wait code, which is apparently important especially when
dealing with link training.
It also contains a patch to address Adam's
On Mon, 09 Aug 2010 18:04:50 +0100, Chris Wilson ch...@chris-wilson.co.uk
wrote:
On Mon, 9 Aug 2010 09:45:38 -0700, Jesse Barnes jbar...@virtuousgeek.org
wrote:
Is this hack even needed? I noticed on my 945GM that INSTDONE has a
stuck bit when I use this code, removing it didn't seem to
On Sun, 8 Aug 2010 12:01:38 +0100, Chris Wilson ch...@chris-wilson.co.uk
wrote:
If we disable the pipe and the GPU is currently waiting on a scanline
WAIT_FOR_EVENT, the GPU will hang. Fortunately, there is a magic bit
which we can write on i915+ to break this wait before disabling the
pipe.
On Wed, 4 Aug 2010 13:50:22 +0100, Chris Wilson ch...@chris-wilson.co.uk
wrote:
This patchset touches virtually all of i915/intel*.c simply to subclass
encoders and connectors, then cleans up intel_sdvo in order to add a few
more TV properties.
Applied to for-linus. It's early, let's get
On Wed, 4 Aug 2010 13:55:32 +0100, Chris Wilson ch...@chris-wilson.co.uk
wrote:
This avoids the excess flush and requests on idle rings (and spamming
the debug log ;-)
Applied to for-linus.
pgpX8IaVxLdZK.pgp
Description: PGP signature
___
On Wed, 4 Aug 2010 14:09:45 +0100, Chris Wilson ch...@chris-wilson.co.uk
wrote:
This spinlock only served debugging purposes in a time when we could not
be sure of the mutex ever being released upon a GPU hang. As we now
should be able rely on hangcheck to do the job for us (and that error
On Wed, 4 Aug 2010 21:11:13 +0200, Daniel Vetter dan...@ffwll.ch wrote:
On Wed, Aug 04, 2010 at 08:57:26PM +0200, Daniel Vetter wrote:
On Wed, Aug 04, 2010 at 03:36:30PM +0100, Chris Wilson wrote:
Incorporates a similar patch by Daniel Vetter, the alteration being to
report the current
On Wed, 4 Aug 2010 12:37:41 +0100, Chris Wilson ch...@chris-wilson.co.uk
wrote:
This debugging trace was useful for finding the fbcon regression on
i965, and it may prove useful again in future.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
Applied to for-linus.
pgpZZLQVEkKgE.pgp
On Wed, 4 Aug 2010 15:18:11 +0100, Chris Wilson ch...@chris-wilson.co.uk
wrote:
The goal here is to simplify the ringbuffer emission so that we can avoid
the function call overhead when writing into the ringbuffer.
Sweet. Applied.
pgpDCN497TLQN.pgp
Description: PGP signature
On Wed, 4 Aug 2010 16:22:28 +0100, Chris Wilson ch...@chris-wilson.co.uk
wrote:
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
Any clarification what the impact was here?
pgpJukfKw83yH.pgp
Description: PGP signature
___
Intel-gfx mailing list
On Fri, 25 Jun 2010 13:40:23 +0800, Zou Nan hai nanhai@intel.com wrote:
RC6 requires setup logical render context
Signed-off-by: Zou Nan hai nanhai@intel.com
---
drivers/gpu/drm/i915/i915_drv.h |1 +
drivers/gpu/drm/i915/i915_reg.h | 13 +++-
On Sun, 18 Jul 2010 12:05:54 +0100, Chris Wilson ch...@chris-wilson.co.uk
wrote:
Move the common routines into separate functions to not only increase
readability, but also throwaway surplus code.
In doing so, we review the calculation of the aspect preserving scaling
and avoid the use of
On Sat, 17 Jul 2010 20:23:57 +0100, Chris Wilson ch...@chris-wilson.co.uk
wrote:
Reduce the number of variables used and improve readability by scoping.
Lots of conflicts here.
pgpXCKVnbf0jU.pgp
Description: PGP signature
___
Intel-gfx mailing list
On Fri, 16 Jul 2010 14:46:32 -0400, Adam Jackson a...@redhat.com wrote:
Signed-off-by: Adam Jackson a...@redhat.com
Applied this series to -next.
pgpauz7TxSsc2.pgp
Description: PGP signature
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
On Mon, 19 Jul 2010 09:43:13 +0100, Chris Wilson ch...@chris-wilson.co.uk
wrote:
From: Zhao Yakui yakui.z...@intel.com
Signed-off-by: Zhao Yakui yakui.z...@intel.com
Reviewed-by: Chris Wilson ch...@chris-wilson.co.uk
Cc: sta...@kernel.org
Chris, thanks for reviewing this! Applied to
On Mon, 19 Jul 2010 14:25:42 +0100, Chris Wilson ch...@chris-wilson.co.uk
wrote:
Subclass intel_encoder to reduce the pointer dance through
intel_encoder-dev_priv.
10 files changed, 831 insertions(+), 928 deletions(-)
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
Lots of conflicts
On Mon, 12 Jul 2010 19:35:38 +0100, Chris Wilson ch...@chris-wilson.co.uk
wrote:
Apparently i830 and i845 cannot handle any stride that is not a multiple
of 256, unlike their brethren which do support 64 byte aligned strides.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
Cc:
On Tue, 13 Jul 2010 13:52:17 +0100, Chris Wilson ch...@chris-wilson.co.uk
wrote:
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
Applied to -next.
pgphX89exKhrx.pgp
Description: PGP signature
___
Intel-gfx mailing list
On Mon, 19 Jul 2010 19:59:52 +0100, Chris Wilson ch...@chris-wilson.co.uk
wrote:
Even though we have enough padding that it should be ok, round up the
watermark entries to the next unit to be on the safe side...
v2: Use the DIV_ROUND_UP macro
v3: Spotted a few more missing round-ups.
On Mon, 19 Jul 2010 21:46:08 +0100, Chris Wilson ch...@chris-wilson.co.uk
wrote:
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
Cc: Jesse Barnes jbar...@virtuousgeek.org
Nice. Applied to -next.
pgp60zAuzf7Di.pgp
Description: PGP signature
On Fri, 23 Jul 2010 23:18:51 +0100, Chris Wilson ch...@chris-wilson.co.uk
wrote:
If we fail to flush outstanding GPU writes but return the memory to the
system, we risk corrupting memory should the GPU recovery and complete
those writes. On the other hand, if we bail early and free the object
On Fri, 23 Jul 2010 16:29:06 -0400, Andrew Lutomirski l...@mit.edu wrote:
On Fri, Jul 23, 2010 at 4:13 PM, Eric Anholt e...@anholt.net wrote:
On Fri, 23 Jul 2010 14:00:30 -0400, Andrew Lutomirski l...@mit.edu wrote:
AFAICT intel hardware wants a 129-entry LUT when using high precision
gamma
On Sun, 25 Jul 2010 15:29:25 -0400, Andrew Lutomirski l...@mit.edu wrote:
For well over a year now, I (and apparently lots of other people) have
had to run patched kernels to avoid crippling hotplug storms.
As far as I can tell, on my laptop, enabling DPC_HOTPLUG_INT_EN is
safe, but setting
On Wed, 21 Jul 2010 13:57:47 -0700, Jesse Barnes jbar...@virtuousgeek.org
wrote:
Fixes https://bugs.freedesktop.org/show_bug.cgi?id=29141 though the
workaround itself is still a bit of a mystery.
Applied to for-linus.
pgp9QaYjGkmgZ.pgp
Description: PGP signature
On Fri, 2 Jul 2010 16:43:30 -0400, Adam Jackson a...@redhat.com wrote:
Fixes an Ironlake laptop with a 68.940MHz 1280x800 panel and 120MHz SSC
reference clock.
More generally, the 0.488% tolerance used before is just too tight to
reliably find a PLL setting. I extracted the search
On Mon, 26 Jul 2010 10:23:23 -0700, Jesse Barnes jbar...@virtuousgeek.org
wrote:
On Thu, 22 Jul 2010 13:18:19 -0700
Jesse Barnes jbar...@virtuousgeek.org wrote:
When enabling the eDP port, we need to make sure the panel is turned on
after training the link. If we don't, it likely won't
On Fri, 23 Jul 2010 23:32:05 +0100, Chris Wilson ch...@chris-wilson.co.uk
wrote:
This fixes a potential modesetting error during boot with plymouth on
Broadwater and Crestline introduced with 9df47c. The framebuffer was
hard-coding an alignment of 64K, but the modesetting code required the
On Fri, 23 Jul 2010 15:20:00 -0700, Jesse Barnes jbar...@virtuousgeek.org
wrote:
We're really supposed to do this to avoid trouble with underflows when
multiple planes are active.
Fixes https://bugs.freedesktop.org/show_bug.cgi?id=26987.
Signed-off-by: Jesse Barnes
On Thu, 22 Jul 2010 08:12:20 -0700, Jesse Barnes jbar...@virtuousgeek.org
wrote:
We should only free the compressed llb if we allocated it in the first
place otherwise we'll panic at unload time.
Applied to for-linus.
pgpTjtkm30tPv.pgp
Description: PGP signature
On Fri, 02 Jul 2010 10:45:45 +0200, Thomas Bächler tho...@archlinux.org wrote:
Am 02.07.2010 00:41, schrieb Eric Anholt:
On Wed, 9 Jun 2010 21:40:54 +0200, Thomas Bächler tho...@archlinux.org
wrote:
On some machines (currently only the Toshiba Tecra A11 is known), the GPU
locks up when
On Wed, 7 Jul 2010 14:06:43 -0700, Jesse Barnes jbar...@virtuousgeek.org
wrote:
Since mode-clock is in kHz we should be checking against 270
instead of just 27000. This patch gets my x201s working again (well
working as well as it ever was anyway).
When looking for this I also noticed
On Mon, 5 Jul 2010 18:01:47 +0100, Chris Wilson ch...@chris-wilson.co.uk
wrote:
When trying to keep track of features between the kernel, the 2D driver,
mesa and the specs, it helps to list any other name by which the device
is referred to.
Applied this series to -next.
pgplCnse1VpIH.pgp
On Fri, 2 Jul 2010 15:02:17 +0100, Chris Wilson ch...@chris-wilson.co.uk
wrote:
From: Daniel Vetter daniel.vet...@ffwll.ch
This does two little changes:
- Add an alignment parameter for evict_something. It's not really great to
whack a carefully sized hole into the gtt with the wrong
On Fri, 2 Jul 2010 08:57:15 +0100, Chris Wilson ch...@chris-wilson.co.uk
wrote:
Oops, when merging the extra details following an OOM, I missed that
driver_private is now NULL and the correct way to convert from the
drm_gem_object into the drm_i915_gem_object is to use to_intel_bo().
On Sun, 6 Jun 2010 13:21:26 +0100, Chris Wilson ch...@chris-wilson.co.uk
wrote:
We generally issue an error message at the point of failure, and so this
warning with a fairly pointless stacktrace is superfluous and ugly.
Needless to say, the common trigger for this WARN happens to be EIO
On Sun, 6 Jun 2010 12:16:24 +0100, Chris Wilson ch...@chris-wilson.co.uk
wrote:
References:
Bug 26691 - Spurious hangcheck whilst executing a long shader over a
large vertex buffer
https://bugs.freedesktop.org/show_bug.cgi?id=26691
This is a nice workaround to the
On Fri, 25 Jun 2010 15:32:14 -0400, Adam Jackson a...@redhat.com wrote:
Unmask the bits for link training reporting before starting link
training. If stage 1 training finished before we unmask them, then we'd
spin around in a loop a few times until smashing on through. Which is
harmless,
On Sat, 12 Jun 2010 14:32:22 +0800, Zhenyu Wang zhen...@linux.intel.com wrote:
From: Zhao Yakui yakui.z...@intel.com
The non-8 BPC can be used for the eDP output device that is
connected through DP-A or DP-D on PCH. In such case we should
set the PIPECONF dither correctly.
Applied all of
On Fri, 2 Jul 2010 15:02:10 +0100, Chris Wilson ch...@chris-wilson.co.uk
wrote:
This is a resend of Daniel Vetter's drm mm work to provide a basis for
performing fair eviction in i915. I've taken the liberty of attaching the
acks and review comments from the previous round, so please look
On Mon, 5 Jul 2010 10:25:57 +0100, Chris Wilson ch...@chris-wilson.co.uk
wrote:
The original i965 requires an alignment of 128K for the display surface
with linear memory, so increase the requirement from 64k for these
chipsets. For the later chipsets in the i965 family, only a 4k alignment
On Wed, 30 Jun 2010 13:16:00 -0700, Jesse Barnes jbar...@virtuousgeek.org
wrote:
Having two sets has made me think I caught a bug more than once now.
Applied this series to -next.
pgpD7e5eD06If.pgp
Description: PGP signature
___
Intel-gfx mailing
On Wed, 9 Jun 2010 21:40:54 +0200, Thomas Bächler tho...@archlinux.org wrote:
On some machines (currently only the Toshiba Tecra A11 is known), the GPU
locks up when modeset is forced on LID open. This patch adds a new DMI
blacklist and omits modesetting for all matches.
Fixes
On Wed, 9 Jun 2010 17:04:24 +0100, Chris Wilson ch...@chris-wilson.co.uk
wrote:
Oops, when merging the extra details following an OOM, I missed that
driver_private is now NULL and the correct way to convert from the
drm_gem_object into the drm_i915_gem_object is to use to_intel_bo().
BUG:
Keithp was asking me about how many buffers of what sizes we create when
I was working on the libdrm changes for memory management, so I figured
I'd post some numbers I took. Here's firefox-talos-gfx under cairo-gl:
4kb: 123163
8kb: 7247
12kb: 21319
16kb: 69737
24kb: 291
32kb: 14
On Tue, 8 Jun 2010 21:54:03 +1000, Dave Airlie airl...@gmail.com wrote:
On Tue, Jun 8, 2010 at 7:56 PM, Eric Anholt e...@anholt.net wrote:
On Tue, 8 Jun 2010 09:16:13 +1000, Dave Airlie airl...@gmail.com wrote:
On Tue, Jun 8, 2010 at 6:55 AM, Eric Anholt e...@anholt.net wrote:
For whatever
On Mon, 7 Jun 2010 13:54:05 +1000 (EST), Robert Lowery
rglow...@exemail.com.au wrote:
We had two cases recently where the rounding to powers of two hurt
badly: 4:2:0 YUV HD video frames would round up from 2.2MB to 4MB,
Urban Terror was hitting aperture size limitations. Mipmap trees for
We had two cases recently where the rounding to powers of two hurt
badly: 4:2:0 YUV HD video frames would round up from 2.2MB to 4MB,
Urban Terror was hitting aperture size limitations. Mipmap trees for
power of two sizes will land right in the middle between two cache
buckets.
By giving a few
On Thu, 27 May 2010 13:18:22 +0100, Chris Wilson ch...@chris-wilson.co.uk
wrote:
The callers expect us to cleanup any partially initialised structures
before reporting the error.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
Applied this series.
pgpyyBZHNgCia.pgp
Description: PGP
On Thu, 27 May 2010 14:21:01 +0100, Chris Wilson ch...@chris-wilson.co.uk
wrote:
We can avoid an early clflush when pwriting if we use the current CPU
write domain rather than moving the object to the GTT domain for the
purposes of the pwrite. This has the advantage of not flushing the
On Thu, 27 May 2010 14:15:34 +0100, Chris Wilson ch...@chris-wilson.co.uk
wrote:
As we do not have a requirement to be atomic and avoid sleeping whilst
performing the slow copy for shmem based pread and pwrite, we can use
kmap instead, thus simplifying the code.
Signed-off-by: Chris Wilson
On Fri, 21 May 2010 09:40:45 -0700, Jesse Barnes jbar...@virtuousgeek.org
wrote:
FBC disable on 965 can take long enough to trigger latency checks in the
kernel so be sure to timeout after a reasonable period.
Fixes https://bugzilla.kernel.org/show_bug.cgi?id=15015.
Tested-by: James Ettle
On Mon, 17 May 2010 14:23:52 +0100, Daniel J Blueman daniel.blue...@gmail.com
wrote:
While investigating Intel i5 Arrandale GPU lockups with -rc4, I
noticed a lock imbalance.
Signed-off-by: Daniel J Blueman daniel.blue...@gmail.com
Applied. Thanks!
pgpI2j3wFbsWY.pgp
Description: PGP
On Tue, 25 May 2010 13:06:50 +0800, Xiang, Haihao haihao.xi...@intel.com
wrote:
This interface is the same as drm_intel_bo_alloc except the allocated
size isn't rounded up, so it bypasses the cache bucket.
The size of the BO created by drm_intel_bo_alloc for a 1920x800,4:2:0 YUV
planar
On Mon, 24 May 2010 16:46:29 -0400, Adam Jackson a...@redhat.com wrote:
Disable the CRT plug interrupt while doing the force cycle, explicitly
clear any CRT interrupt we may have generated, and restore when done.
Should mitigate interrupt storms from hotplug detection.
Nice, I've been hoping
On Tue, 18 May 2010 12:24:51 +0100, Chris Wilson ch...@chris-wilson.co.uk
wrote:
References:
Bug 15733 - Crash when accessing nonexistent GTT entries in i915
https://bugzilla.kernel.org/show_bug.cgi?id=15733
On G33 and above, the size of the GTT space is determined by the GMCH
On Tue, 18 May 2010 12:24:51 +0100, Chris Wilson ch...@chris-wilson.co.uk
wrote:
References:
Bug 15733 - Crash when accessing nonexistent GTT entries in i915
https://bugzilla.kernel.org/show_bug.cgi?id=15733
On G33 and above, the size of the GTT space is determined by the GMCH
On Sat, 15 May 2010 09:31:17 -0700, Jesse Barnes jbar...@virtuousgeek.org
wrote:
On Sat, 15 May 2010 09:57:03 +0100
Chris Wilson ch...@chris-wilson.co.uk wrote:
We can, by virtue of a vblank interrupt firing in the middle of
setting up the unpin work (i.e. after we set the unpin_work
On Thu, 13 May 2010 14:45:43 -0400, Adam Jackson a...@redhat.com wrote:
Signed-off-by: Adam Jackson a...@redhat.com
---
drivers/gpu/drm/i915/intel_dp.c |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
401 - 500 of 511 matches
Mail list logo
