Planes are a bit like half-CRTCs. They have a location and fb, but
don't drive outputs directly. Add support for handling them to the core
KMS code.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/drm_crtc.c | 230
drivers
To properly support the various plane formats supported by different
hardware, the kernel must know the pixel format of a framebuffer object.
So add a new ioctl taking a format argument corresponding to a fourcc
name from videodev2.h.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
The video sprites support video surface formats natively and can handle
scaling well. So add support for them using the new DRM core overlay
support functions.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/Makefile |1 +
drivers/gpu/drm/i915
The old overlay block has all sorts of quirks and is very different than
ILK+ video sprites. So rename it to legacy to make that clear and clash
less with core overlay support.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/i915_debugfs.c |2 +-
drivers/gpu
On Tue, 7 Jun 2011 13:07:39 -0700
Jesse Barnes jbar...@virtuousgeek.org wrote:
+#define DRM_MODE_PLANE_FORMAT_YUV422 1 /* YUV 4:2:2 packed */
+#define DRM_MODE_PLANE_FORMAT_RGBX101010 2 /* RGB 10bpc, ign. alpha */
+#define DRM_MODE_PLANE_FORMAT_RGBX8883 /* Standard
On Wed, 8 Jun 2011 11:41:17 +0200
Marcus Lorentzon marcus.xm.lorent...@stericsson.com wrote:
On 06/07/2011 11:01 PM, Jesse Barnes wrote:
On Tue, 7 Jun 2011 13:07:39 -0700
Jesse Barnesjbar...@virtuousgeek.org wrote:
+/* Planes blend with or override other bits on the CRTC
in
need of more splitting though. The case statement should be split into
per-chipset flip command generation.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/intel_display.c | 21 -
1 files changed, 16 insertions(+), 5 deletions(-)
diff --git
On Tue, 14 Jun 2011 00:29:08 -0700
Kenneth Graunke kenn...@whitecape.org wrote:
On 06/13/2011 03:22 PM, Chris Wilson wrote:
On Tue, 14 Jun 2011 00:14:11 -0700, Kenneth Graunkekenn...@whitecape.org
wrote:
On 06/09/2011 12:14 PM, Jesse Barnes wrote:
Found a couple more problems:
1
Use the blit ring for submitting flips since the render ring doesn't
generate flip complete interrupts.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/intel_display.c | 25 +
1 files changed, 25 insertions(+), 0 deletions(-)
diff --git
This makes things a little clearer and prevents us from running old code
on a new chipset that may not be supported.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/i915_drv.h |3 +
drivers/gpu/drm/i915/intel_display.c | 196
This makes things a little clearer and prevents us from running old code
on a new chipset that may not be supported.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/i915_drv.h |3 +
drivers/gpu/drm/i915/intel_display.c | 202
On Tue, 7 Jun 2011 13:07:38 -0700
Jesse Barnes jbar...@virtuousgeek.org wrote:
This patchset updates the previous one, incorporating the feedback I
received:
1) uses the v4l fourcc codes to communicate pixel format
2) adds a new addfb ioctl that takes a format
3) adds working SNB
On Tue, 14 Jun 2011 12:34:54 -0700
Jesse Barnes jbar...@virtuousgeek.org wrote:
Use the blit ring for submitting flips since the render ring doesn't
generate flip complete interrupts.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/intel_display.c | 26
Per the specs and to address
https://bugs.freedesktop.org/show_bug.cgi?id=36888.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/intel_display.c |8 ++--
1 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b
This makes things a little clearer and prevents us from running old code
on a new chipset that may not be supported.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/i915_drv.h |3 +
drivers/gpu/drm/i915/intel_display.c | 269
Use the blit ring for submitting flips since the render ring doesn't
generate flip complete interrupts.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/intel_display.c | 30 ++
1 files changed, 30 insertions(+), 0 deletions(-)
diff
On Thu, 16 Jun 2011 11:54:50 -0700
Ben Widawsky b...@bwidawsk.net wrote:
On Thu, Jun 16, 2011 at 09:19:14AM -0700, Jesse Barnes wrote:
Use the blit ring for submitting flips since the render ring doesn't
generate flip complete interrupts.
Signed-off-by: Jesse Barnes jbar
Updated with comment.
--
Jesse Barnes, Intel Open Source Technology Center
From 41bdb7457beb023faa0d465f483ab793ba8896e1 Mon Sep 17 00:00:00 2001
From: Jesse Barnes jbar...@virtuousgeek.org
Date: Tue, 14 Jun 2011 11:08:03 -0700
Subject: [PATCH] drm/i915: add Ivy Bridge page flip support
Use
issue(stutter and hangcheck) is gone, now.
The issue described as bug 36407 isn’t able to be reproduced.
The bug 36653 is still there.
Thanks for testing, looks like this is an important fix (36652 is what
I think you mean on the last one?).
--
Jesse Barnes, Intel Open Source Technology Center
This version adds both source and dest rect params to the set_plane
ioctl, and makes the source fixed point to support hardware that needs
it.
I haven't changed the name of the SNB implementation yet (per Chris's
suggestions) but will before it gets upstream.
I'd be interested to see whether
Planes are a bit like half-CRTCs. They have a location and fb, but
don't drive outputs directly. Add support for handling them to the core
KMS code.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/drm_crtc.c | 235 +++-
drivers
To properly support the various plane formats supported by different
hardware, the kernel must know the pixel format of a framebuffer object.
So add a new ioctl taking a format argument corresponding to a fourcc
name from videodev2.h.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
The old overlay block has all sorts of quirks and is very different than
ILK+ video sprites. So rename it to legacy to make that clear and clash
less with core overlay support.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/i915_debugfs.c |2 +-
drivers/gpu
The video sprites support video surface formats natively and can handle
scaling well. So add support for them using the new DRM core overlay
support functions.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/Makefile |1 +
drivers/gpu/drm/i915
(multiple Watt) power savings, and we
really want it to be robust.
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On Tue, 21 Jun 2011 10:55:39 +0200
Marcus Lorentzon marcus.xm.lorent...@stericsson.com wrote:
On 06/20/2011 10:11 PM, Jesse Barnes wrote:
This version adds both source and dest rect params to the set_plane
ioctl, and makes the source fixed point to support hardware that needs
it.
I
On Tue, 21 Jun 2011 06:21:11 -0500
Rob Clark robdcl...@gmail.com wrote:
On Mon, Jun 20, 2011 at 3:11 PM, Jesse Barnes jbar...@virtuousgeek.org
wrote:
This version adds both source and dest rect params to the set_plane
ioctl, and makes the source fixed point to support hardware that needs
On Tue, 21 Jun 2011 18:12:56 +0200 (CEST)
Nicolas Kalkhof nkalk...@web.de wrote:
Hi Jesse,
thanks for the infiormation. I've switched rc6 off by
echo 0 /sys/module/i915/parameters/i915_enable_rc6
this should do it, right?
cat /sys/module/i915/parameters/i915_enable_rc6 yields 0
Are you
. But then if you're keeping your GPU busy, you probably
want the extra performance.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2f967af..15ee639 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers
Chris Wilson ch...@chris-wilson.co.uk wrote:
On Tue, 21 Jun 2011 15:24:24 -0700, Jesse Barnes
jbar...@virtuousgeek.org wrote:
The ring frequency scaling table tells the PCU to treat certain GPU
frequencies as if they were a given CPU frequency for purposes of
scaling the ring frequency
On Wed, 22 Jun 2011 11:42:04 -0700
Eric Anholt e...@anholt.net wrote:
On Tue, 21 Jun 2011 15:24:24 -0700, Jesse Barnes jbar...@virtuousgeek.org
wrote:
The ring frequency scaling table tells the PCU to treat certain GPU
frequencies as if they were a given CPU frequency for purposes
On Wed, 22 Jun 2011 11:42:04 -0700
Eric Anholt e...@anholt.net wrote:
On Tue, 21 Jun 2011 15:24:24 -0700, Jesse Barnes jbar...@virtuousgeek.org
wrote:
The ring frequency scaling table tells the PCU to treat certain GPU
frequencies as if they were a given CPU frequency for purposes
I tested again and things were working as expected. This patch adds a
debugfs file for dumping the ring freq table, can you guys test it out
(try disabling the call to update the table, dump it, make sure it's 0,
then re-enable and make sure it's programmed correctly).
--
Jesse Barnes, Intel
On Thu, 23 Jun 2011 21:08:02 +0100
Chris Wilson ch...@chris-wilson.co.uk wrote:
On Thu, 23 Jun 2011 10:11:26 -0700, Jesse Barnes jbar...@virtuousgeek.org
wrote:
I tested again and things were working as expected. This patch adds a
debugfs file for dumping the ring freq table, can you guys
This allows drivers and other code to get the max reported CPU frequency.
Initial use is for scaling ring frequency with GPU frequency in the i915
driver.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/cpufreq/cpufreq.c | 20
include/linux/cpufreq.h
frequency into account.
The main downside of keeping the ring frequency high while the CPU is
at a low frequency (or asleep altogether) is increased power
consumption. But then if you're keeping your GPU busy, you probably
want the extra performance.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
This update includes the fixes requested by Chris. The DP link
bandwidth calculation change seems ok here at least for basic mode sets
at different depths, but wider testing is definitely needed.
Thanks,
Jesse
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These bits are reserved on ILK+ (ILK+ provides this feature in the
transcoder and pipe configuration instead, which we already set).
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/intel_hdmi.c |3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git
This prevents us from setting reserved or incorrect bits on CougarPoint.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/intel_display.c | 15 +--
1 files changed, 9 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b
This may not be the default value, so pull the bpc out of the pipe reg
and write it to the DP transcoder so proper dithering and signaling
occurs.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/intel_display.c |3 ++-
1 files changed, 2 insertions(+), 1
The pipe may be driving various bpp values depending on the display
configuration, so take that into account when calculating link bandwidth
requirements.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/intel_dp.c |5 ++---
1 files changed, 2 insertions(+), 3
in calculating bandwidth requirements (defaults to 24bpp on pre-ILK).
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/intel_display.c | 194 ++
drivers/gpu/drm/i915/intel_drv.h |1 +
2 files changed, 153 insertions(+), 42 deletions
To properly drive a framebuffer with a new depth or bpp, dither settings
and link bandwidth calculations may change, so make sure we go through a
full mode set in that case.
Reported-by: Chris Wilson ch...@chris-wilson.co.uk
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu
This will catch bad fb configs earlier.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/intel_display.c |5 +
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index
On Mon, 27 Jun 2011 20:40:08 +0100
Chris Wilson ch...@chris-wilson.co.uk wrote:
On Fri, 24 Jun 2011 11:13:14 -0700, Jesse Barnes jbar...@virtuousgeek.org
wrote:
The ring frequency scaling table tells the PCU to treat certain GPU
frequencies as if they were a given CPU frequency
don't know what
function it should follow.
ia_freq 800 shouldn't break anything, but would probably result in
sub-optimal GPU performance. OTOH it would save power...
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Intel
)
- use tsc_khz as a fallback if the cpufreq driver doesn't give us a freq
(from Chris)
Tested-by: Eric Anholt e...@anholt.net
Reviewed-by: Eric Anholt e...@anholt.net
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/i915_debugfs.c | 43
This lets us make the various IRQ functions static and helps avoid
problems like the one fixed in drm/i915: Use chipset-specific irq
installers where one of the exported functions was called rather than
the chipset specific version.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/i915_debugfs.c | 39 +++
drivers/gpu/drm/i915/i915_reg.h |4 ++-
drivers/gpu/drm/i915/i915_suspend.c |4 ++-
drivers/gpu/drm/i915/intel_display.c | 58
On Tue, 28 Jun 2011 13:52:00 -0700
Keith Packard kei...@keithp.com wrote:
On Tue, 28 Jun 2011 13:00:41 -0700, Jesse Barnes jbar...@virtuousgeek.org
wrote:
This lets us make the various IRQ functions static and helps avoid
problems like the one fixed in drm/i915: Use chipset-specific irq
They use the same register interfaces, so we can simply enable the
existing code on IVB.
v2:
- resolve conflict with ring freq scaling, we can enable it too
v3:
- resolve conflict again, this time on drm-intel-next
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm
support for CEC?
There's no driver support for CEC right now; I haven't looked at the
feature closely enough yet to know whether current hw can support it.
If it mainly involves additional info frames then we can likely handle
it with existing stuff...
--
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,
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On Thu, 30 Jun 2011 18:37:13 +0100
Simon Farnsworth simon.farnswo...@onelan.co.uk wrote:
On Thursday 30 June 2011, Jesse Barnes jbar...@virtuousgeek.org wrote:
On Thu, 30 Jun 2011 18:19:20 +0100
Barry Scott barry.sc...@onelan.co.uk wrote:
The HW needs to support the 1 wire
In an attempt to fix 38862 and 38863.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/i915_irq.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 2e18161..23d1ae6 100644
Makes it easier to search for DP related constants.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/intel_dp.c | 18 ++
1 files changed, 10 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915
When a hotplug event is received, we need to check the receiver cap bits
in case they've changed (as they might with a hub or chain config).
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/intel_dp.c | 11 +++
1 files changed, 11 insertions(+), 0 deletions
If the receiver goes away, drop any associated CRTC. This will force a
full mode set on any subsequent setcrtc call, which is what we need if
the receiver is gone and the link is down.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/intel_dp.c | 10 --
1
Make its usage a little more clear.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/intel_dp.c | 11 ++-
1 files changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index d7a8d24..ac6334d
A regular mode set can be considered a DPMS on state as far as
receiver detection goes.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/intel_dp.c |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu
When link training or detection fails, set the receiver_configured flag
to false to reflect the current state.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/intel_dp.c |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/i915
By default, the GPU will only share a very small portion of the CPU
cache. With this change, both the GPU and CPU will have full access to
the cache, which should help (sometimes a lot) in most cases.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/i915_reg.h
On Fri, 01 Jul 2011 16:41:06 -0700
Keith Packard kei...@keithp.com wrote:
On Fri, 1 Jul 2011 15:22:51 -0700, Jesse Barnes jbar...@virtuousgeek.org
wrote:
Especially after a hotplug or power status change, the sink may not
reply immediately to a link status query. So retry 3 times per
On Tue, 05 Jul 2011 21:27:35 -0700
Eric Anholt e...@anholt.net wrote:
On Fri, 1 Jul 2011 15:22:51 -0700, Jesse Barnes jbar...@virtuousgeek.org
wrote:
Especially after a hotplug or power status change, the sink may not
reply immediately to a link status query. So retry 3 times per
...
If anything, using __read_mostly appropriately should *increase*
performance, not decrease it. But I think we'd have to measure real
hard to notice anything at all for this particular set of changes
(though __read_mostly is definitely the right thing to do).
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, looks good.
Reviewed-by: Jesse Barnes jbar...@virtuousgeek.org
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|= (DPFC_CTL_FENCE_EN | dev_priv-cfb_fence);
I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
Yes, extra bits! Looks like the latest specs don't restrict this bit
to being SNB only or anything, so setting it here looks good.
Reviewed-by: Jesse Barnes jbar...@virtuousgeek.org
--
Jesse
Wilson ch...@chris-wilson.co.uk
---
Yeah just disabling it is probably better than trying to let the hw
figure out what to recompress since it likely won't be worthwhile.
Reviewed-by: Jesse Barnes jbar...@virtuousgeek.org
--
Jesse Barnes, Intel Open Source Technology Center
/intel_display.c | 50
+-
4 files changed, 30 insertions(+), 34 deletions(-)
The code motion made me look twice, but it's a real fix.
Reviewed-by: Jesse Barnes jbar...@virtuousgeek.org
--
Jesse Barnes, Intel Open Source Technology Center
you test module unload/reload as well to make sure the work
teardown is working correctly?
Reviewed-by: Jesse Barnes jbar...@virtuousgeek.org
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Addresses review comments, in particular:
- pull out the retry code into a separate function
- fix hotplug handling differently (just try to poke the sink on every
hot plug if it was ever configured, i.e. has an assigned crtc)
- add sink power management
Thanks,
Jesse
Makes it easier to search for DP related constants.
Reviewed-by: Keith Packard kei...@keithp.com
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/intel_dp.c | 18 ++
1 files changed, 10 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm
When a hotplug event is received, we need to check the receiver cap bits
in case they've changed (as they might with a hub or chain config).
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/intel_dp.c | 11 +++
1 files changed, 11 insertions(+), 0 deletions
DisplayPort spec.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/intel_dp.c | 15 ++-
1 files changed, 10 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index a9a5051..70075d9 100644
--- a/drivers
uevents), we need to unconditionally check the link and try to
bring it up on hot plug.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/intel_dp.c |6 +-
1 files changed, 1 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu
When checking link status during a hot plug event or detecting sink
presence, we need to retry 3 times per the spec (section 9.1 of the 1.1a
DisplayPort spec). Consolidate the retry code into a
native_aux_read_retry function for use by get_link_status and _detect.
Signed-off-by: Jesse Barnes
On sinks with a DPCD rev of 1.1 or greater, we can send sink power
management commands to address 0x600 per section 5.1.5 of the
DisplayPort 1.1a spec.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/intel_dp.c | 35 +++
1 files
On Ironlake and above, we have per-transcoder DIP registers, so use them
for sending DIPs like AVI infoframes on ILK and above.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/i915_reg.h | 14 +
drivers/gpu/drm/i915/intel_hdmi.c | 39
On Thu, 21 Jul 2011 19:30:00 +0900
Joonyoung Shim dofm...@gmail.com wrote:
Hi,
simple questions :)
2011/6/21 Jesse Barnes jbar...@virtuousgeek.org:
Planes are a bit like half-CRTCs. They have a location and fb, but
don't drive outputs directly. Add support for handling them
On Thu, 21 Jul 2011 19:15:24 +0900
Joonyoung Shim dofm...@gmail.com wrote:
Hi,
2011/6/16 Jesse Barnes jbar...@virtuousgeek.org:
On Tue, 7 Jun 2011 13:07:38 -0700
Jesse Barnes jbar...@virtuousgeek.org wrote:
This patchset updates the previous one, incorporating the feedback I
On Fri, 22 Jul 2011 08:52:52 -0500
Rob Clark robdcl...@gmail.com wrote:
On Mon, Jun 20, 2011 at 3:11 PM, Jesse Barnes jbar...@virtuousgeek.org
wrote:
/**
+ * drm_plane_funcs - driver plane control functions
+ * @update_plane: update the plane configuration
+ */
+struct
|= DPLL_VCO_ENABLE;
Maybe this part would be cleaner if you added G4x support to
choose_pipe_bpp_dither and called it here instead?
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http
On Wed, 15 Jun 2011 23:32:33 +0200
Jesse Barnes jbar...@virtuousgeek.org wrote:
Per the specs and to address
https://bugs.freedesktop.org/show_bug.cgi?id=36888.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/intel_display.c |8 ++--
1 files changed
and probably lots of
other random DP related failures.
Looks like the -detect function is similarly protected at the call
site (though one level up in -fill_modes), so it should be safe.
Looks like all the call sites in the link_status function are safe too.
Reviewed-by: Jesse Barnes jbar...@virtuousgeek.org
my
Reviewed-by: Jesse Barnes jbar...@virtuousgeek.org to 1/5 and 2/5.
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)
dev_priv-no_aux_handshake =
intel_dp-dpcd[DP_MAX_DOWNSPREAD]
Reviewed-by: Jesse Barnes jbar...@virtuousgeek.org
Now we just have to enable fast link training in the eDP case (and
optionally when we know the DP monitor hasn't changed, just
to that pch port
Signed-off-by: Keith Packard kei...@keithp.com
---
Ah nice catch. I expect one day we'll have all the chipset and PCH
differences coded...
Reviewed-by: Jesse Barnes jbar...@virtuousgeek.org
--
Jesse Barnes, Intel Open Source Technology Center
was held across the helper too.
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to weird DP behavior.
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commit 2a9852c3809f5fd03a4755381e2ef47da72d22ef
Author: Jesse Barnes jbar...@virtuousgeek.org
Date: Fri Jul 22 13:17:05 2011 -0700
drm/i915: apply timing generator bug workaround on CPT and PPT
and wasn't able to reproduce it. I may have been just getting lucky,
but it's worth having you
Mainly for use in debugging and benchmarking, this file allows the user
to control the max frequency used by the GPU. Frequency may still vary
based on workload (if the frequency is set to higher than the minimum)
but won't go over the newly set value.
Signed-off-by: Jesse Barnes jbar
int intel_crtc_mode_set(struct drm_crtc *crtc,
drm_vblank_post_modeset(dev, pipe);
+ intel_crtc-dpms_mode = DRM_MODE_DPMS_ON;
+
return ret;
}
Aside from a general objection about our seeming inability to track
DPMS state properly:
Reviewed-by: Jesse Barnes jbar
failures.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/i915_reg.h |5 +
drivers/gpu/drm/i915/intel_display.c |4
2 files changed, 9 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
Mainly for use in debugging and benchmarking, this file allows the user
to control the max frequency used by the GPU. Frequency may still vary
based on workload (if the frequency is set to higher than the minimum)
but won't go over the newly set value.
Signed-off-by: Jesse Barnes jbar
On Wed, 27 Jul 2011 23:08:08 -0700
Keith Packard kei...@keithp.com wrote:
On Wed, 27 Jul 2011 09:06:09 -0700, Jesse Barnes jbar...@virtuousgeek.org
wrote:
I tried this last week with my patch
So, with the intel_crtc DPMS tracking fixed, this problem can now be
easily reproduced
After writing to the plane control reg we need to write to the surface
reg to trigger the double buffered register latch.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/intel_display.c |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git
These bits moved around on SNB and above.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/i915_reg.h |7 +++
drivers/gpu/drm/i915/intel_display.c | 34 ++
2 files changed, 41 insertions(+), 0 deletions(-)
diff --git
The EDID parser will zero out the bpc value, and the driver needs to handle
that case. In our picker, we'll just ignore 0 values as far as bpp
picking goes.
Fixes https://bugs.freedesktop.org/show_bug.cgi?id=39323.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915
a little prettier (used to have occasional dots crawl
across the display).
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/intel_display.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm
These bits moved around on SNB and above.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/i915_reg.h | 12
drivers/gpu/drm/i915/intel_display.c | 34 ++
2 files changed, 46 insertions(+), 0 deletions(-)
diff
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