Re: [Intel-gfx] [PATCH v8 6/6] drm/i915/perf: Implement I915_PERF_ADD/REMOVE_CONFIG interface

On 1 August 2017 at 11:58, Lionel Landwerlin <lionel.g.landwer...@intel.com> wrote: > On 31/07/17 18:36, Matthew Auld wrote: >> >> On 28 July 2017 at 18:10, Lionel Landwerlin >> <lionel.g.landwer...@intel.com> wrote: >>> >>> The motiva

Re: [Intel-gfx] [PATCH i-g-t 02/11] tests/perf: add per context filtering test for gen8+

On 4 August 2017 at 12:20, Lionel Landwerlin wrote: > From: Robert Bragg > > Signed-off-by: Robert Bragg > Signed-off-by: Lionel Landwerlin > --- > tests/perf.c | 806 >

Re: [Intel-gfx] [PATCH 01/16] drm/i915: Keep a small stash of preallocated WC pages

tash global. > > Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk> fwiw, Reviewed-by: Matthew Auld <matthew.a...@intel.com> ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH i-g-t] tests/perf: follow up build fix

On 4 August 2017 at 17:23, Lionel Landwerlin <lionel.g.landwer...@intel.com> wrote: > Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com> > Fixes: adcde8ac ("tests/perf: fix build where system headers don't have Gen8 > formats") Tested-by: Matth

Re: [Intel-gfx] [PATCH i-g-t] tests/perf: fix userspace configs issues on HSW

> configs") > Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com> Crumbs... Reviewed-by: Matthew Auld <matthew.a...@intel.com> ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 00/23] huge gtt pages

On 22 August 2017 at 15:23, Chris Wilson <ch...@chris-wilson.co.uk> wrote: > Quoting Chris Wilson (2017-08-22 15:21:10) >> Quoting Matthew Auld (2017-08-21 19:34:40) >> > Some more improvements as per Chris' comments. >> > >> > Mat

Re: [Intel-gfx] [PATCH i-g-t 05/11] tests/perf: rework oa-exponent test

On 22 August 2017 at 15:56, Lionel Landwerlin <lionel.g.landwer...@intel.com> wrote: > On 10/08/17 14:15, Matthew Auld wrote: > > On 4 August 2017 at 12:20, Lionel Landwerlin > <lionel.g.landwer...@intel.com> wrote: > > New issues that were discovered while

Re: [Intel-gfx] [PATCH] drm/i915: don't do allocate_va_range again on pin update

On 12 May 2017 at 10:31, Chris Wilson <ch...@chris-wilson.co.uk> wrote: > On Fri, May 12, 2017 at 10:14:23AM +0100, Chris Wilson wrote: >> From: Matthew Auld <matthew.a...@intel.com> >> >> If a vma is already bound to a ppgtt, we incorrectly call >> allocate

[Intel-gfx] [PATCH 16/17] drm/i915: enable platform support for 2M pages

For gen8+ enable platform level support for 2M pages. Also enable for mock testing. Signed-off-by: Matthew Auld <matthew.a...@intel.com> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> --- drivers/gpu/drm/i915/i915_pci.c | 9 ++--- drivers/gpu/drm/i9

[Intel-gfx] [PATCH 14/17] drm/i915/debugfs: include some gtt_page_size metrics

Good to know, mostly for debugging purposes. Signed-off-by: Matthew Auld <matthew.a...@intel.com> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> --- drivers/gpu/drm/i915/i915_debugfs.c | 37 ++--- 1 file changed, 34 insertions(+), 3 deletions(-)

[Intel-gfx] [PATCH 03/17] drm/i915: align the vma start to the gtt page size

When inserting into a 48bit PPGTT we need to align the vma start address to the required page size boundary. The size will already be aligned so no padding is needed. Signed-off-by: Matthew Auld <matthew.a...@intel.com> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Cc: Chri

[Intel-gfx] [PATCH 17/17] drm/i915: enable platform support for 1G pages

For gen8+ enable platform level support for 1G pages. Also enable for mock testing. Signed-off-by: Matthew Auld <matthew.a...@intel.com> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> --- drivers/gpu/drm/i915/i915_pci.c | 9 ++--- drivers/gpu/drm/i9

[Intel-gfx] [PATCH 04/17] drm/i915: align 64K objects to 2M

ris-wilson.co.uk> Signed-off-by: Matthew Auld <matthew.a...@intel.com> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> --- drivers/gpu/drm/i915/i915_vma.c | 9 + 1 file changed, 9 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i91

[Intel-gfx] [PATCH 12/17] drm/i915: support inserting 2M pages into the 48b PPGTT

To enable 2M pages we set the PS bit of PDE, aka PDE[7] to indicate a 2M page and not a page-table. Signed-off-by: Matthew Auld <matthew.a...@intel.com> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> --- drivers/gpu/drm/i915/i915_ge

[Intel-gfx] [PATCH 09/17] drm/i915: enable IPS bit for 64K pages

Before we can enable 64K pages through the IPS bit, we must first enable it through MMIO, otherwise the page-walker will simply ignore it. Signed-off-by: Matthew Auld <matthew.a...@intel.com> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> --- drivers/gpu/drm/i915/i91

[Intel-gfx] [PATCH 15/17] drm/i915: enable platform support for 64K pages

For gen9+ enable platform level support for 64K pages. Also enable for mock testing. Signed-off-by: Matthew Auld <matthew.a...@intel.com> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> --- drivers/gpu/drm/i915/i915_pci.c | 6 -- drivers/gpu/drm/i9

[Intel-gfx] [PATCH 13/17] drm/i915: support inserting 1G pages into the 48b PPGTT

To enable 1G pages we set the PS bit in the PDPE, aka PDPE[7] to indicate a 1G page, and not a PD. Signed-off-by: Matthew Auld <matthew.a...@intel.com> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> --- drivers/gpu/drm/i915/i915_ge

[Intel-gfx] [PATCH 10/17] drm/i915: support inserting 64K pages into the 48b PPGTT

If we set the IPS bit, aka PDE[11] then every 16th entry should be used to index, the HW makes no assumptions for any other PTEs. Signed-off-by: Matthew Auld <matthew.a...@intel.com> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> --- drivers/gpu/drm/i915/i915_ge

[Intel-gfx] [PATCH] drm/i915: use vma->size for appgtt allocate_va_range

a->size. Fixes: ff685975d97f ("drm/i915: Move allocate_va_range to GTT") Signed-off-by: Matthew Auld <matthew.a...@intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> --- drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git

[Intel-gfx] [PATCH 02/17] drm/i915: introduce gtt page size

In preparation for supporting huge gtt pages for the ppgtt, we introduce a gtt_page_size member for gem objects. We fill in the gtt page size by scanning the sg table to determine the max page size which satisfies the alignment for each sg entry. Signed-off-by: Matthew Auld <matthe

[Intel-gfx] [PATCH 11/17] drm/i915: disable GTT cache for 2M/1G pages

When SW enables the use of 2M/1G pages, it must disable the GTT cache. Signed-off-by: Matthew Auld <matthew.a...@intel.com> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> --- drivers/gpu/drm/i915/intel_pm.c | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-)

[Intel-gfx] [PATCH 06/17] mm/shmem: expose driver overridable huge option

. Signed-off-by: Matthew Auld <matthew.a...@intel.com> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Cc: Dave Hansen <dave.han...@intel.com> Cc: Daniel Vetter <dan...@ffwll.ch> Cc: Hugh Dickins <hu...@google.com> Cc: linux...@kvack.org --- include/linux/shmem_fs.h

[Intel-gfx] [PATCH 07/17] drm/i915: request THP for shmem backed objects

Default to transparent-huge-pages for shmem backed objects through the SHMEM_HUGE_WITHIN_SIZE huge option. Best effort only. Signed-off-by: Matthew Auld <matthew.a...@intel.com> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Cc: Dave Hansen <dave.han...@intel.com> Cc:

[Intel-gfx] [PATCH 00/17] add support for huge-gtt-pages

this addresses the concerns from the last version. Matthew Auld (17): drm/i915: introduce page_size_mask to dev_info drm/i915: introduce gtt page size drm/i915: align the vma start to the gtt page size drm/i915: align 64K objects to 2M drm/i915: fallback to normal pages on vma insert failure mm

[Intel-gfx] [PATCH 01/17] drm/i915: introduce page_size_mask to dev_info

In preparation for huge gtt pages expose a page_size_mask as part of the device info, to indicate the page sizes supported by the HW. Currently only 4K is supported. Signed-off-by: Matthew Auld <matthew.a...@intel.com> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Cc: M

[Intel-gfx] [PATCH 08/17] drm/i915: pass gtt page size to insert_entries

Expose a page size parameter for insert_entries, this is only relevant for inserting into the 4lvl ppgtt where we pass the gtt_page_size of the object. Signed-off-by: Matthew Auld <matthew.a...@intel.com> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> --- drivers/

[Intel-gfx] [PATCH 05/17] drm/i915: fallback to normal pages on vma insert failure

Part of the cost in choosing huge-gtt-pages is potentially using a larger alignment and/or size. Therefore if our vma insert fails either because of the insert/reserve or the pin-offset-fixed we should fallback to normal pages and retry before giving up. Signed-off-by: Matthew Auld <matthe

Re: [Intel-gfx] [PATCH] drm/i915: Exclude top-page for ppgtt as well as ggtt

re is no reason > to believe that the hw restriction is any less severe. > > Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk> Reviewed-by: Matthew Auld <matthew.a...@intel.com> ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org h

Re: [Intel-gfx] [PATCH v16 08/17] drm/i915/perf: Add OA unit support for Gen 8+

nagement now that we monitor sseu > configuration changes in a later patch (Lionel) > Remove usleep after programming the NOA configs on Gen8+, this > doesn't seem to be needed (Lionel) > > v15: Respect coding style for block comments (Chris) > > Signed-off-by:

Re: [Intel-gfx] [PATCH v16 08/17] drm/i915/perf: Add OA unit support for Gen 8+

nagement now that we monitor sseu > configuration changes in a later patch (Lionel) > Remove usleep after programming the NOA configs on Gen8+, this > doesn't seem to be needed (Lionel) > > v15: Respect coding style for block comment

Re: [Intel-gfx] [PATCH i-g-t 21/29] igt/perf: make stream_fd a global variable

On 25 April 2017 at 23:32, Lionel Landwerlin wrote: > When debugging unstable tests on new platforms we currently we don't > cleanup everything well in between different tests. Since only a > single OA stream fd can be opened at a time, having the stream_fd as a >

[Intel-gfx] [PATCH 17/19] drm/i915: enable platform support for 64K pages

For gen9+ enable platform level support for 64K pages. Also enable for mock testing. Signed-off-by: Matthew Auld <matthew.a...@intel.com> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> --- drivers/gpu/drm/i915/i915_pci.c | 3 ++- drivers/gpu/drm/i9

[Intel-gfx] [PATCH 14/19] drm/i915/debugfs: include some gtt page size metrics

Good to know, mostly for debugging purposes. Signed-off-by: Matthew Auld <matthew.a...@intel.com> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> --- drivers/gpu/drm/i915/i915_debugfs.c | 42 + 1 file changed, 38 insertions(+), 4 deletions(-)

[Intel-gfx] [PATCH 13/19] drm/i915: accurate page size tracking for the ppgtt

Now that we support multiple page sizes for the ppgtt, it would be useful to track the real usage for debugging purposes. Signed-off-by: Matthew Auld <matthew.a...@intel.com> --- drivers/gpu/drm/i915/i915_gem_gtt.c| 16 drivers/gpu/drm/i915/i915_gem_object.

[Intel-gfx] [PATCH 15/19] drm/i915/selftests: basic huge page tests

Signed-off-by: Matthew Auld <matthew.a...@intel.com> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> --- drivers/gpu/drm/i915/i915_gem.c| 1 + drivers/gpu/drm/i915/selftests/huge_pa

[Intel-gfx] [PATCH 19/19] drm/i915: enable platform support for 1G pages

For gen8+ enable platforms which support the 48b PPGTT, enable support for 1G pages. Also enable for mock testing. Signed-off-by: Matthew Auld <matthew.a...@intel.com> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> --- drivers/gpu/drm/i915/i915_pci.c | 6 +++

[Intel-gfx] [PATCH 04/19] drm/i915: introduce page_size members

along with the pages. Signed-off-by: Matthew Auld <matthew.a...@intel.com> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Daniel Vetter <dan...@ffwll.ch> --- drivers/gpu/drm/i915/i915_drv.h | 5 +

[Intel-gfx] [PATCH 06/19] drm/i915: align 64K objects to 2M

ris-wilson.co.uk> Signed-off-by: Matthew Auld <matthew.a...@intel.com> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> --- drivers/gpu/drm/i915/i915_vma.c | 10 +- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_vma.c b/dr

[Intel-gfx] [PATCH 02/19] drm/i915/gemfs: enable THP

Enable transparent-huge-pages through gemfs by mounting with huge=within_size. Signed-off-by: Matthew Auld <matthew.a...@intel.com> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> --- drivers/gpu/drm/i915/i915_gemfs.c | 16 +

[Intel-gfx] [PATCH 05/19] drm/i915: align the vma start to the largest gtt page size

into the lower 32bits we don't force any alignment. v2: various improvements suggested by Chris Signed-off-by: Matthew Auld <matthew.a...@intel.com> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> --- drivers/gpu/drm/i9

[Intel-gfx] [PATCH 07/19] drm/i915: pass the vma to insert_entries

ing into the 48b PPGTT. This is especially true for 64K where we can't just arbitrarily use it, since we require aligning/padding the vm space to 2M, which sometimes we can't enforce in the upper levels. Suggested-by: Chris Wilson <ch...@chris-wilson.co.uk> Signed-off-by: Matthew Auld &

[Intel-gfx] [PATCH 00/19] huge gtt pages

Hopefully addresses the feedback from the previous round. Matthew Auld (19): drm/i915: introduce simple gemfs drm/i915/gemfs: enable THP drm/i915: introduce page_size_mask to dev_info drm/i915: introduce page_size members drm/i915: align the vma start to the largest gtt page size drm

[Intel-gfx] [PATCH 01/19] drm/i915: introduce simple gemfs

objects. v2: various improvements suggested by Joonas Signed-off-by: Matthew Auld <matthew.a...@intel.com> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> --- drivers/gpu/drm/i915/Makefile| 1 + dr

[Intel-gfx] [PATCH 10/19] drm/i915: support 1G pages for the 48b PPGTT

Support inserting 1G gtt pages into the 48b PPGTT. Signed-off-by: Matthew Auld <matthew.a...@intel.com> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> --- drivers/gpu/drm/i915/i915_gem_gtt.c | 72 ++--- drivers/gpu/drm/i915/i915_gem_gtt.h | 2

[Intel-gfx] [PATCH 03/19] drm/i915: introduce page_size_mask to dev_info

In preparation for huge gtt pages expose a page_size_mask as part of the device info, to indicate the page sizes supported by the HW. Currently only 4K is supported. Signed-off-by: Matthew Auld <matthew.a...@intel.com> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Cc: M

[Intel-gfx] [PATCH 09/19] drm/i915: disable GTT cache for 2M/1G pages

When SW enables the use of 2M/1G pages, it must disable the GTT cache. v2: don't disable for Cherryview which doesn't even support 48b PPGTT! Signed-off-by: Matthew Auld <matthew.a...@intel.com> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Cc: Chris Wilson <ch...@chr

[Intel-gfx] [PATCH 11/19] drm/i915: support 2M pages for the 48b PPGTT

Signed-off-by: Matthew Auld <matthew.a...@intel.com> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> --- drivers/gpu/drm/i915/i915_gem_gtt.c | 8 drivers/gpu/drm/i915/i915_gem_gtt.h | 2 ++ 2 files changed, 10 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_

[Intel-gfx] [PATCH 16/19] drm/i915/selftests: mix huge pages

Try to mix sg page sizes for 4K, 64K and 2M pages. Suggested-by: Chris Wilson <ch...@chris-wilson.co.uk> Signed-off-by: Matthew Auld <matthew.a...@intel.com> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> --- drivers/gpu/drm/i915/selftests/scatterlist.c | 15 +

[Intel-gfx] [PATCH 12/19] drm/i915: support 64K pages for the 48b PPGTT

Signed-off-by: Matthew Auld <matthew.a...@intel.com> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> --- drivers/gpu/drm/i915/i915_gem_gtt.c | 26 ++ drivers/gpu/drm/i915/i915_gem_gtt.h | 1 + 2 files changed, 27 insertions(+) diff --git a/drivers/

[Intel-gfx] [PATCH 08/19] drm/i915: enable IPS bit for 64K pages

Before we can enable 64K pages through the IPS bit, we must first enable it through MMIO, otherwise the page-walker will simply ignore it. Signed-off-by: Matthew Auld <matthew.a...@intel.com> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> --- drivers/gpu/drm/i915/i91

[Intel-gfx] [PATCH 18/19] drm/i915: enable platform support for 2M pages

For gen8+ platforms which support the 48b PPGTT, enable platform level support for 2M pages. Also enable for mock testing. Signed-off-by: Matthew Auld <matthew.a...@intel.com> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> --- drivers/gpu/drm/i915/i915_pci.c

[Intel-gfx] [PATCH] drm/i915: pass the vma to insert_entries

. This is especially true for 64K where we can't just arbitrarily use it, since we require aligning/padding the vm space to 2M, which sometimes we can't enforce in the upper levels. Suggested-by: Chris Wilson <ch...@chris-wilson.co.uk> Signed-off-by: Matthew Auld <matthew.a...@intel.com>

Re: [Intel-gfx] [PATCH 10/19] drm/i915: support 1G pages for the 48b PPGTT

On 21 June 2017 at 23:51, Chris Wilson <ch...@chris-wilson.co.uk> wrote: > Quoting Chris Wilson (2017-06-21 22:49:07) >> Quoting Matthew Auld (2017-06-21 21:33:36) >> > Support inserting 1G gtt pages into the 48b PPGTT. >> > >> > Signed-off-by: Matthew Aul

Re: [Intel-gfx] [PATCH 12/19] drm/i915: support 64K pages for the 48b PPGTT

On 21 June 2017 at 22:55, Chris Wilson <ch...@chris-wilson.co.uk> wrote: > Quoting Matthew Auld (2017-06-21 21:33:38) >> Signed-off-by: Matthew Auld <matthew.a...@intel.com> >> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> >> --- >&

Re: [Intel-gfx] [PATCH 14/14] drm/i915/perf: add GLK support

tamp base are we just assuming it's the same as BXT, or did you find it somewhere in the bspec, because I had no such luck? Otherwise assuming the configs are indeed correct and with a proper commit message: Reviewed-by: Matthew Auld <matthew.a.

Re: [Intel-gfx] [PATCH 12/14] drm/i915: add KBL GT2/GT3 check macros

On 05/17, Lionel Landwerlin wrote: > Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com> With a proper commit message: Reviewed-by: Matthew Auld <matthew.a...@intel.com> > --- > drivers/gpu/drm/i915/i915_drv.h | 4 > 1 file changed, 4 insertions(+) &

Re: [Intel-gfx] [PATCH 02/17] drm/i915: introduce gtt page size

On 16 May 2017 at 10:59, Chris Wilson <ch...@chris-wilson.co.uk> wrote: > On Tue, May 16, 2017 at 09:29:33AM +0100, Matthew Auld wrote: >> In preparation for supporting huge gtt pages for the ppgtt, we introduce >> a gtt_page_size member for gem objects. We fill

Re: [Intel-gfx] [PATCH 02/17] drm/i915: introduce gtt page size

On 23 May 2017 at 13:54, Chris Wilson <ch...@chris-wilson.co.uk> wrote: > On Tue, May 23, 2017 at 01:42:56PM +0100, Matthew Auld wrote: >> On 16 May 2017 at 10:59, Chris Wilson <ch...@chris-wilson.co.uk> wrote: >> > On Tue, May 16, 2017 at 09:29:33AM +0100, Matthew Au

Re: [Intel-gfx] [PATCH] drm/i915/selftests: Silence compiler warning in igt_ctx_exec

onas.lahti...@linux.intel.com> > Cc: Tvrtko Ursulin <tvrtko.ursu...@intel.com> > Cc: Matthew Auld <matthew.a...@intel.com> > c: <drm-intel-fi...@lists.freedesktop.org> # v4.12-rc1+ Cc: <drm-intel-fi...@lists.freedesktop.org> # v4.12-rc1+ Reviewed-by: Matthew Auld &

Re: [Intel-gfx] [PATCH 13/14] drm/i915/perf: add KBL support

On 05/17, Lionel Landwerlin wrote: > Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com> With some kind of commit message: Reviewed-by: Matthew Auld <matthew.a...@intel.com> ___ Intel-gfx mailing list Intel-gfx@lists.

Re: [Intel-gfx] [PATCH 06/14] drm/i915/perf: rework mux configurations queries

const struct i915_oa_reg *mux_regs; > - int mux_regs_len; > + const struct i915_oa_reg *mux_regs[1]; > + int mux_regs_lens[1]; > + int n_mux_regs; So this is more like n_mux_configs ? Reviewed-by:

[Intel-gfx] [PATCH 14/15] drm/i915: enable platform support for 2M pages

For gen8+ enable platform level support for 2M pages. Also enable for mock testing. Signed-off-by: Matthew Auld <matthew.a...@intel.com> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> --- drivers/gpu/drm/i915/i915_pci.c | 9 ++--- drivers/gpu/drm/i9

[Intel-gfx] [PATCH 00/15] huge gtt pages

Not too different from the last posting, except we now request thp through our own tmpfs mount and try to support mixed gtt page sizes for a given object. Matthew Auld (15): drm/i915: really simple gemfs drm/i915: enable THP for gemfs drm/i915: introduce page_size_mask to dev_info drm

[Intel-gfx] [PATCH 07/15] drm/i915: pass mm.gtt_page_sizes to ppgtt insert_entries

/padding the vm space to 2M, which sometimes we can't enforce. Signed-off-by: Matthew Auld <matthew.a...@intel.com> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> --- drivers/gpu/drm/i915/i915_gem_gtt.c | 24 drivers/gpu/drm/i915/i9

[Intel-gfx] [PATCH 05/15] drm/i915: align the vma start to the largest gtt page size

alignment. Signed-off-by: Matthew Auld <matthew.a...@intel.com> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> --- drivers/gpu/drm/i915/i915_vma.c | 12 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm

[Intel-gfx] [PATCH 13/15] drm/i915: enable platform support for 64K pages

For gen9+ enable platform level support for 64K pages. Also enable for mock testing. Signed-off-by: Matthew Auld <matthew.a...@intel.com> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> --- drivers/gpu/drm/i915/i915_pci.c | 6 -- drivers/gpu/drm/i9

[Intel-gfx] [PATCH 01/15] drm/i915: really simple gemfs

objects. Signed-off-by: Matthew Auld <matthew.a...@intel.com> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> --- drivers/gpu/drm/i915/Makefile| 1 + drivers/gpu/drm/i915/i915_drv.h | 13 ++

[Intel-gfx] [PATCH 03/15] drm/i915: introduce page_size_mask to dev_info

In preparation for huge gtt pages expose a page_size_mask as part of the device info, to indicate the page sizes supported by the HW. Currently only 4K is supported. Signed-off-by: Matthew Auld <matthew.a...@intel.com> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Cc: M

[Intel-gfx] [PATCH 09/15] drm/i915: disable GTT cache for 2M/1G pages

When SW enables the use of 2M/1G pages, it must disable the GTT cache. Signed-off-by: Matthew Auld <matthew.a...@intel.com> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> --- drivers/gpu/drm/i915/intel_pm.c | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-)

[Intel-gfx] [PATCH 11/15] drm/i915: accurate page size tracking for the ppgtt

Now that we support multiple page sizes for the ppgtt, it would be useful to track the real usage for debugging purposes. Signed-off-by: Matthew Auld <matthew.a...@intel.com> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> --- drivers/gpu/drm/i915/i915_gem_gtt.c

[Intel-gfx] [PATCH 04/15] drm/i915: introduce gem object page_sizes

We need to track the possible page sizes given the layout of the sg table, in preparation for supporting huge gtt pages. Note that this does in any way represent the real gtt page size usage. Signed-off-by: Matthew Auld <matthew.a...@intel.com> Cc: Joonas Lahtinen <joonas.lahti...@linux.

[Intel-gfx] [PATCH 02/15] drm/i915: enable THP for gemfs

Enable transparent-huge-pages through gemfs by mounting with huge=within_size. Signed-off-by: Matthew Auld <matthew.a...@intel.com> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> --- drivers/gpu/drm/i915

[Intel-gfx] [PATCH 10/15] drm/i915: support huge gtt pages for the 48b PPGTT

Support inserting huge gtt pages into the 48b PPGTT, including mixed-mode where we allow a mixture of gtt page sizes. Signed-off-by: Matthew Auld <matthew.a...@intel.com> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc:

[Intel-gfx] [PATCH 15/15] drm/i915: enable platform support for 1G pages

For gen8+ enable platform level support for 1G pages. Also enable for mock testing. Signed-off-by: Matthew Auld <matthew.a...@intel.com> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> --- drivers/gpu/drm/i915/i915_pci.c | 9 ++--- drivers/gpu/drm/i9

[Intel-gfx] [PATCH 06/15] drm/i915: align 64K objects to 2M

ris-wilson.co.uk> Signed-off-by: Matthew Auld <matthew.a...@intel.com> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> --- drivers/gpu/drm/i915/i915_vma.c | 18 ++ 1 file changed, 18 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/d

[Intel-gfx] [PATCH 12/15] drm/i915/debugfs: include some gtt page size metrics

Good to know, mostly for debugging purposes. Signed-off-by: Matthew Auld <matthew.a...@intel.com> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> --- drivers/gpu/drm/i915/i915_debugfs.c | 40 ++--- 1 file changed, 37 insertions(+), 3 deletions(-)

[Intel-gfx] [PATCH 08/15] drm/i915: enable IPS bit for 64K pages

Before we can enable 64K pages through the IPS bit, we must first enable it through MMIO, otherwise the page-walker will simply ignore it. Signed-off-by: Matthew Auld <matthew.a...@intel.com> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> --- drivers/gpu/drm/i915/i91

Re: [Intel-gfx] [PATCH 01/15] drm/i915: really simple gemfs

On 1 June 2017 at 11:49, Joonas Lahtinen <joonas.lahti...@linux.intel.com> wrote: > On ke, 2017-05-31 at 19:51 +0100, Matthew Auld wrote: >> Not a fully blown gemfs, just our very own tmpfs kernel mount. Doing so >> moves us away from the shmemfs shm_mnt, and giv

Re: [Intel-gfx] [PATCH i-g-t 21/29] igt/perf: make stream_fd a global variable

a time, having the stream_fd as a > global variable helps us cleanup the state between tests. > > Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com> So just improve the tests such that they do the necessary cleanup? But if you feel this is better, then: Review

Re: [Intel-gfx] [PATCH i-g-t 02/29] igt/perf: improve robustness of polling/blocking tests

each) so that a single tick represents a much > smaller proportion of the total duration (0.1%) and the stime thresholds > are now set at 1% of the total duration. > > Signed-off-by: Robert Bragg <rob...@sixbynine.org> I did r-b this in the past, so: Reviewed-by: Matthew Auld <ma

Re: [Intel-gfx] [PATCH i-g-t 03/29] igt/perf: init timestamp freq and oa format per devid

On 25 April 2017 at 23:32, Lionel Landwerlin <lionel.g.landwer...@intel.com> wrote: > From: Robert Bragg <rob...@sixbynine.org> > > Signed-off-by: Robert Bragg <rob...@sixbynine.org> > Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>

Re: [Intel-gfx] [PATCH i-g-t 20/29] igt/perf: add utility function for checking periodic reports

seem to correlate > +* with a timer trigger reason) so we instead infer which > +* reports are timer triggered by checking if the least > +* significant bits are zero and the exponent bit is set. > +*/ > +

Re: [Intel-gfx] [PATCH v16 16/17] drm/i915/perf: notify sseu configuration changes

On 5 June 2017 at 15:48, Lionel Landwerlin wrote: > This adds the ability for userspace to request that the kernel track & > record sseu configuration changes. These changes are inserted into the > perf stream so that userspace can interpret the OA reports using the

Re: [Intel-gfx] [PATCH v16 15/17] drm/i915/perf: allow NOA muxes reprogramming before workloads

On 5 June 2017 at 15:48, Lionel Landwerlin wrote: > Dynamic slices/subslices shutdown will effectivelly loose the NOA > configuration uploaded in the slices/subslices. > > Here we introduce a new parameter to configure the i915 perf driver > when userspace wants to

Re: [Intel-gfx] [PATCH v3 1/2] drm/i915/perf: disable clk ratio reports on gen9

On 18 September 2017 at 12:21, Lionel Landwerlin <lionel.g.landwer...@intel.com> wrote: > We're doing this on all Gen9 based platforms, let's just check the gen > rather than listing every single platforms. > > Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com&

Re: [Intel-gfx] [PATCH] drm/i915/selftests: Disable iommu for the mock device

gt; Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk> > Tested-by: Elizabeth De La Torre Mena <elizabethx.de.la.torre.m...@intel.com> Reviewed-by: Matthew Auld <matthew.a...@intel.com> ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH] drm/i915/selftests: Only touch archdata.iommu when it exists

rm/i915/selftests: Disable iommu for the mock device") > Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk> > Cc: Matthew Auld <matthew.a...@intel.com> Reviewed-by: Matthew Auld <matthew.a...@intel.com> ___ Intel

Re: [Intel-gfx] [PATCH i-g-t v5 05/11] tests/perf: remove frequency related changes

On 08/31, Lionel Landwerlin wrote: > Experience shows that most of the issues we face with periodicity of > the reports produced by the OA unit are related to power management, > not frequency. > > Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com> Ok. Revi

Re: [Intel-gfx] [PATCH i-g-t v5 06/11] tests/perf: rework oa-exponent test

; + intel_batchbuffer_free(lh.batch); > + > + if (lh.context) > + drm_intel_gem_context_destroy(lh.context); > + > + if (lh.bufmgr) > + drm_intel_bufmgr_destroy(lh.bufmgr); > +} > + > static void > test_oa_exponents(void) > { > - ig

Re: [Intel-gfx] [PATCH i-g-t v5 04/11] tests/perf: rc6: try to guess when rc6 is disabled

On 08/31, Lionel Landwerlin wrote: > Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com> Reviewed-by: Matthew Auld <matthew.a...@intel.com> ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesk

Re: [Intel-gfx] [PATCH i-g-t v5 10/11] tests/perf: prevent power management to kick in when necessary

m> Seems to cure the oa-exponents test for me, so: Reviewed-by: Matthew Auld <matthew.a...@intel.com> ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH 09/21] drm/i915: align 64K objects to 2M

ops Suggested-by: Chris Wilson <ch...@chris-wilson.co.uk> Signed-off-by: Matthew Auld <matthew.a...@intel.com> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> --- drivers/gpu/drm/i915/i915_vma.c | 10 +- 1 file cha

[Intel-gfx] [PATCH 06/21] drm/i915: introduce page_size members

along with the pages. v4: bunch of improvements from Joonas Signed-off-by: Matthew Auld <matthew.a...@intel.com> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Daniel Vetter <dan...@ffwll.ch> Reviewed-by: Joona

[Intel-gfx] [PATCH 04/21] drm/i915: introduce page_sizes field to dev_info

In preparation for huge gtt pages expose page_sizes as part of the device info, to indicate the page sizes supported by the HW. Currently only 4K is supported. v2: s/page_size_mask/page_sizes/ Signed-off-by: Matthew Auld <matthew.a...@intel.com> Cc: Joonas Lahtinen <joo

[Intel-gfx] [PATCH 02/21] drm/i915: introduce simple gemfs

objects. v2: various improvements suggested by Joonas v3: move gemfs instance to i915.mm and simplify now that we have file_setup_with_mnt v4: fallback to tmpfs shm_mnt upon failure to setup gemfs Signed-off-by: Matthew Auld <matthew.a...@intel.com> Cc: Joonas Lahtinen <joo

[Intel-gfx] [PATCH 08/21] drm/i915: align the vma start to the largest gtt page size

into the lower 32bits we don't force any alignment. v2: various improvements suggested by Chris v3: use set_pages and better placement of page_sizes Signed-off-by: Matthew Auld <matthew.a...@intel.com> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Cc: Chris Wilson

[Intel-gfx] [PATCH 07/21] drm/i915: introduce vm set_pages/clear_pages

check v3: GEM_BUG_ON(vma->pages) following i915_vma_remove Suggested-by: Chris Wilson <ch...@chris-wilson.co.uk> Signed-off-by: Matthew Auld <matthew.a...@intel.com> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> ---

[Intel-gfx] [PATCH 03/21] drm/i915/gemfs: enable THP

Enable transparent-huge-pages through gemfs by mounting with huge=within_size. Signed-off-by: Matthew Auld <matthew.a...@intel.com> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> --- drivers/gpu/drm/i915/i915_gemfs.c | 14

[Intel-gfx] [PATCH 05/21] drm/i915: push set_pages down to the callers

Wilson <ch...@chris-wilson.co.uk> Signed-off-by: Matthew Auld <matthew.a...@intel.com> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> Reviewed-by: Joonas Lahtinen <joonas.lahti...@linux.intel.com> --- d

[Intel-gfx] [PATCH 11/21] drm/i915: disable GTT cache for 2M pages

When SW enables the use of 2M/1G pages, it must disable the GTT cache. v2: don't disable for Cherryview which doesn't even support 48b PPGTT! v3: explicitly check that the system does support 2M/1G pages Signed-off-by: Matthew Auld <matthew.a...@intel.com> Cc: Joonas Lahtinen <joo

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