Re: [Intel-gfx] [PATCH 06/21] drm/i915/guc: Use guc_class instead of engine_class in fw interface

hing and use the GuC definitions for the firmware interface. We also keep the same class id in the ctx descriptor to be able to have the same values in the driver and firmware logs. Signed-off-by: Michel Thierry Signed-off-by: Rodrigo Vivi Signed-off-by: Michal Wajdeczko Cc: Daniele Ceraolo Spurio

Re: [Intel-gfx] [PATCH] drm/i915/selftests: ring all doorbells in igt_guc_doorbells

haven't misprogrammed any WQ or stage descriptor data. This will also help validating upcoming changes in the db programming flow. Cc: Michel Thierry Cc: Michal Wajdeczko Signed-off-by: Daniele Ceraolo Spurio --- drivers/gpu/drm/i915/intel_guc_fwif.h | 1 + drivers/gpu/drm/i915

Re: [Intel-gfx] [PATCH 2/3] drm/i915: Do not short-circuit tasklets during reset

On 7/13/2018 1:41 PM, Chris Wilson wrote: Quoting Chris Wilson (2018-07-13 21:35:28) Inside intel_engine_is_idle(), we flush the tasklet to ensure that is being run in a timely fashion (ksoftirqd has taught us to expect the worst). However, if we are in the middle of reset, the HW may not yet

Re: [Intel-gfx] [PATCH 2/3] drm/i915: Do not short-circuit tasklets during reset

led(t)) I would add a comment that this catches any reset in progress as it isn't as clear as using reset_in_progress (although you explain why in the commit message). Up-to you. Reviewed-by: Michel Thierry + t->func(t->data); +

Re: [Intel-gfx] [PATCH 2/4] drm/i915/selftests: Include the start of each subtest in the GEM trace

On 7/13/2018 1:18 PM, Chris Wilson wrote: Knowing the boundary of each subtest can be instrumental in digesting the voluminous trace output and finding the critical piece of information. Signed-off-by: Chris Wilson Reviewed-by: Michel Thierry --- drivers/gpu/drm/i915/selftests

Re: [Intel-gfx] [PATCH 1/4] drm/i915/execlists: Check reset_in_progress()

On 7/13/2018 1:18 PM, Chris Wilson wrote: Check that reset_in_progress() is true when we process the reset. Signed-off-by: Chris Wilson Reviewed-by: Michel Thierry --- drivers/gpu/drm/i915/intel_lrc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/intel_lrc.c

Re: [Intel-gfx] [PATCH] drm/i915/execlists: Drop clear_gtiir() on GPU reset

915/icl: Correctly clear lost ctx-switch interrupts across reset for Gen11") References: fd8526e50902 ("drm/i915/execlists: Trust the CSB") If I read "drm/i915/execlists: Trust the CSB" correctly, reset_irq is indeed no longer needed as you say. Signed-off-by: Chris Wilson

Re: [Intel-gfx] [PATCH v3 2/3] drm/i915/uc: Fetch GuC/HuC firmwares from guc/huc specific init

struct. v2: don't forget to move wopcm_init - Michele v3: fetch in init_misc phase - Michal Signed-off-by: Michal Wajdeczko Cc: Daniele Ceraolo Spurio Cc: Michel Thierry Reviewed-by: Michel Thierry #2 R-b stands for v3 --- drivers/gpu/drm/i915/i915_gem.c | 7 --- drivers/gpu/drm/i915

Re: [Intel-gfx] [PATCH v3 1/3] drm/i915/guc: Use intel_guc_init_misc to hide GuC internals

On 6/28/2018 7:15 AM, Michal Wajdeczko wrote: We will add more init steps to misc phase and there is no need to expose them separately for use in uc_init_misc function. Signed-off-by: Michal Wajdeczko Cc: Michel Thierry --- drivers/gpu/drm/i915/intel_guc.c | 28

Re: [Intel-gfx] [PATCH] drm/i915: Disable bh around call to tasklet

al Wajdeczko Cc: Michał Winiarski Cc: Michel Thierry --- drivers/gpu/drm/i915/intel_engine_cs.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c index 32bf3a408d46..d3264bd6e9dc 100644 --- a/drivers/gpu/drm/i915

Re: [Intel-gfx] [PATCH v2 1/2] drm/i915/uc: Fetch GuC/HuC firmwares from guc/huc specific init

forget to move wopcm_init - Michele I'm not Italian ;) Signed-off-by: Michal Wajdeczko Cc: Daniele Ceraolo Spurio Cc: Michel Thierry --- drivers/gpu/drm/i915/i915_gem.c | 8 drivers/gpu/drm/i915/intel_guc.c | 7 ++- drivers/gpu/drm

Re: [Intel-gfx] [PATCH] drm/i915/uc: Fetch GuC/HuC firmwares from guc/huc specific init

le Ceraolo Spurio Cc: Michel Thierry --- drivers/gpu/drm/i915/intel_guc.c | 7 ++- drivers/gpu/drm/i915/intel_huc.c | 8 drivers/gpu/drm/i915/intel_huc.h | 6 ++ drivers/gpu/drm/i915/intel_uc.c | 37 - 4 files changed, 40 insertions(+), 18

Re: [Intel-gfx] [PATCH] drm/i915/guc: Print CTL params passed to Guc

On 06/15/2018 07:10 AM, Michal Wajdeczko wrote: While debugging we may want to examine params passed to GuC. Print them all if config I915_DEBUG_GUC is enabled. Signed-off-by: Michal Wajdeczko Cc: Daniele Ceraolo Spurio Cc: Michel Thierry --- drivers/gpu/drm/i915/intel_guc.c | 5 + 1

[Intel-gfx] [PATCH v3 2/2] drm/i915/perf: fix gen11 engine class shift

fic_ctx_id had this problem. v2: Just use the upper 32 bits of lrc_desc (Chris) v3: If we use the lrc_desc, we must apply the ctx_id_mask too (Lionel) Fixes: 61d5676b5561 ("drm/i915/perf: fix ctx_id read with GuC & ICL") Signed-off-by: Michel Thierry Cc: Lionel Landwerlin Cc: Chris

[Intel-gfx] [PATCH v2 1/2] drm/i915/perf: use the lrc_desc to get the ctx hw id in gen8-10

The upper 32 bits of the lrc_desc (bits 52-32 to be precise) are the context hw id in GEN8-10, so use them and have one less thing to maintain in the unlikely case we change the descriptor sw fields. v2: If we use the lrc_desc, we must apply the ctx_id_mask too (Lionel) Signed-off-by: Michel

Re: [Intel-gfx] [PATCH 1/2] drm/i915/perf: use the lrc_desc to get the ctx hw id in gen8-10

On 6/4/2018 4:11 PM, Lionel Landwerlin wrote: On 04/06/18 22:40, Michel Thierry wrote: The upper 32 bits of the lrc_desc (bits 52-32 to be precise) are the context hw id in GEN8-10, so use them and have one less thing to maintain in the unlikely case we change the descriptor sw fields. Signed

[Intel-gfx] [PATCH v2 2/2] drm/i915/perf: fix gen11 engine class shift

fic_ctx_id had this problem. v2: Just use the upper 32 bits of lrc_desc (Chris) Fixes: 61d5676b5561 ("drm/i915/perf: fix ctx_id read with GuC & ICL") Signed-off-by: Michel Thierry Cc: Lionel Landwerlin Cc: Chris Wilson --- drivers/gpu/drm/i915/i915_perf.c | 7 +-- 1 fil

[Intel-gfx] [PATCH 1/2] drm/i915/perf: use the lrc_desc to get the ctx hw id in gen8-10

The upper 32 bits of the lrc_desc (bits 52-32 to be precise) are the context hw id in GEN8-10, so use them and have one less thing to maintain in the unlikely case we change the descriptor sw fields. Signed-off-by: Michel Thierry Cc: Lionel Landwerlin Cc: Chris Wilson --- drivers/gpu/drm/i915

Re: [Intel-gfx] [PATCH] drm/i915/perf: fix gen11 engine class shift

On 6/4/2018 2:03 PM, Chris Wilson wrote: Quoting Michel Thierry (2018-06-04 19:17:24) Use the correct engine class shift value while storing the ctx hw id. Fixes the copy+paste error from commit 61d5676b5561 ("drm/i915/perf: fix ctx_id read with GuC & ICL"). Apologies fo

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/perf: fix gen11 engine class shift

On 06/04/2018 11:58 AM, Patchwork wrote: == Series Details == Series: drm/i915/perf: fix gen11 engine class shift URL : https://patchwork.freedesktop.org/series/44216/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_4277 -> Patchwork_9187 = == Summary - FAILURE ==

[Intel-gfx] [PATCH] drm/i915/perf: fix gen11 engine class shift

fic_ctx_id had this problem. Signed-off-by: Michel Thierry Cc: Lionel Landwerlin Cc: Chris Wilson --- drivers/gpu/drm/i915/i915_perf.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c index a6c8d61add0c..c15c7

Re: [Intel-gfx] [PATCH v4 2/2] drm/i915/perf: fix ctx_id read with GuC & ICL

unters Acked-by: Chris Wilson Please ping Michel for an r-b confirmation on using the lrca for the guc ctx_id. -Chris Got the information from Michel initially ;) Will wait for his Rb on the last version. Both patches, Reviewed-by: Michel Thierry

Re: [Intel-gfx] [PATCH v2 1/2] drm/i915: drop one bit on the hw_id when using guc

riting this... Reviewed-by: Michel Thierry ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH v2 2/2] drm/i915/perf: fix ctx_id read with GuC & ICL

On 6/1/2018 10:08 AM, Lionel Landwerlin wrote: On 01/06/18 16:18, Chris Wilson wrote: Quoting Lionel Landwerlin (2018-06-01 10:52:15) + /* +* The LRCA is aligned to a page. As a result the +* lower 12bits are always at 0 and

Re: [Intel-gfx] [PATCH] drm/i915/guc: Disable preemption if it fails

stop trying to do any further preemption on this engine. References: https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_2235/shard-apl4/igt@gem_exec_sched...@preempt-bsd.html Signed-off-by: Chris Wilson Cc: Michal Wajdeczko Cc: Michel Thierry Cc: Michałt Winiarski Reviewed-by: Michel T

Re: [Intel-gfx] [PATCH 2/2] drm/i915/perf: fix ctx_id read with GuC & ICL

n11), but not me. Reviewed-by: Michel Thierry Signed-off-by: Lionel Landwerlin Fixes: 1de401c08fa805 ("drm/i915/perf: enable perf support on ICL") Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104252 BSpec: 1237 Testcase: igt/perf/gen8-unprivileged-single-ctx-counters --- drivers

Re: [Intel-gfx] [PATCH 1/2] drm/i915: drop one bit on the hw_id when using guc

return MAX_GUC_CONTEXT_HW_ID; + + return MAX_CONTEXT_HW_ID; +} + What was the reason of moving this out of i915_gem_context.c? I don't see any other user. Everything else looks good to me so Reviewed-by: Michel Thierry int i915_gem_contexts_set_dynamic_sseu(struct d

Re: [Intel-gfx] [PATCH v8 6/8] drm/i915: create context image vma in kernel context

Hi, On 5/29/2018 12:16 PM, Lionel Landwerlin wrote: We want to be able to modify other context images from the kernel context in a following commit. To be able to do this we need to map the context image into the kernel context's ppgtt. Signed-off-by: Lionel Landwerlin ---

Re: [Intel-gfx] [PATCH] drm/i915/icl: Read the correct Gen11 interrupt registers

On 5/16/2018 4:39 PM, Paulo Zanoni wrote: Em Qui, 2018-05-10 às 14:59 -0700, Oscar Mateo escreveu: Stop reading some now deprecated interrupt registers in both debugfs and error state. Instead, read the new equivalents in the Gen11 interrupt repartitioning scheme. Note that the equivalent to

Re: [Intel-gfx] [BACKPORT v4.17-rc5] drm/i915/gen9: Add WaClearHIZ_WM_CHICKEN3 for bxt and glk

On 5/15/2018 11:17 AM, Jani Nikula wrote: On Tue, 15 May 2018, Michel Thierry <michel.thie...@intel.com> wrote: On 5/15/2018 10:13 AM, Jani Nikula wrote: On Mon, 14 May 2018, Michel Thierry <michel.thie...@intel.com> wrote: Factor in clear values wherever required while updating

Re: [Intel-gfx] [BACKPORT v4.17-rc5] drm/i915/gen9: Add WaClearHIZ_WM_CHICKEN3 for bxt and glk

On 5/15/2018 10:13 AM, Jani Nikula wrote: On Mon, 14 May 2018, Michel Thierry <michel.thie...@intel.com> wrote: Factor in clear values wherever required while updating destination min/max. Hi Michel, please elaborate what the intention here is. Hi Jani, isn't the intention

[Intel-gfx] [BACKPORT v4.17-rc5] drm/i915/gen9: Add WaClearHIZ_WM_CHICKEN3 for bxt and glk

Factor in clear values wherever required while updating destination min/max. References: HSDES#160184 Signed-off-by: Michel Thierry <michel.thie...@intel.com> Cc: mesa-...@lists.freedesktop.org Cc: Mika Kuoppala <mika.kuopp...@linux.intel.com> Cc: Oscar Mateo <oscar.ma...@inte

Re: [Intel-gfx] [PATCH] drm/i915/gen9: Add WaClearHIZ_WM_CHICKEN3 for bxt and glk

On 5/11/2018 5:43 AM, Mika Kuoppala wrote: Chris Wilson <ch...@chris-wilson.co.uk> writes: Quoting Mika Kuoppala (2018-05-11 10:56:49) Michel Thierry <michel.thie...@intel.com> writes: Factor in clear values wherever required while updating destination min/max. References: HSDE

[Intel-gfx] [PATCH] drm/i915/gen9: Add WaClearHIZ_WM_CHICKEN3 for bxt and glk

Factor in clear values wherever required while updating destination min/max. References: HSDES#160184 Signed-off-by: Michel Thierry <michel.thie...@intel.com> Cc: mesa-...@lists.freedesktop.org Cc: Mika Kuoppala <mika.kuopp...@linux.intel.com> Cc: Oscar Mateo <oscar.

Re: [Intel-gfx] [PATCH] drm/i915/selftests: Create mock_engine() under struct_mutex

c: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Cc: Michel Thierry <michel.thie...@intel.com> Double checked that mock_ring (the other caller of i915_timeline_init) is covered by this same lock. Reviewed-by: Michel Thierry <michel.thie...@intel.com> --- drivers/gpu/drm/i915/selftest

Re: [Intel-gfx] [PATCH] drm/i915: Annotate timeline lock nesting

eline into individual timelines") Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursu...@intel.com> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Tested-by: Michel Thierry <mic

Re: [Intel-gfx] [PATCH 2/2] Revert "drm/i915/cnl: Use mmio access to context status buffer"

@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuopp...@linux.intel.com> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Cc: Tvrtko Ursulin <tvrtko.ursu...@intel.com> Cc: Michał Winiarski <michal.winiar...@intel.com> Cc: Rafael Antognolli <rafael.antogno...@intel.

Re: [Intel-gfx] [PATCH 1/2] drm/i915/execlists: Use rmb() to order CSB reads

Cc: Tvrtko Ursulin <tvrtko.ursu...@intel.com> Cc: Michał Winiarski <michal.winiar...@intel.com> Cc: Rafael Antognolli <rafael.antogno...@intel.com> Cc: Michel Thierry <michel.thie...@intel.com> Cc: Timo Aaltonen <tjaal...@ubuntu.com> Tested-by: Timo Aaltonen <tjaal...@

Re: [Intel-gfx] [PATCH] drm/i915/execlists: Drop preemption arbitrations points along the ring

the breadcrumb; switching contexts at this point is futile so don't. Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Michał Winiarski <michal.winiar...@intel.com> Cc: Michel Thierry <michel.thie...@intel.com> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Rev

Re: [Intel-gfx] [PATCH] drm/i915/guc: Assert we have the doorbell before setting it up

On 05/02/2018 02:11 AM, Chris Wilson wrote: Quoting Michel Thierry (2018-05-01 15:21:53) On 5/1/2018 12:52 AM, Chris Wilson wrote: As our early doorbell is split between early allocation and a late setup after we have a channel to the GuC, it may happen due to a lapse of programmer judgement

Re: [Intel-gfx] [PATCH] drm/i915/guc: Assert we have the doorbell before setting it up

.@intel.com> Cc: Michał Winiarski <michal.winiar...@intel.com> Cc: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Michel Thierry <michel.thie...@intel.com> --- drivers/gpu/drm/i915/intel_guc_submission.c | 22 +++-- 1 file changed, 12 insertions(+), 10 deleti

Re: [Intel-gfx] [PATCH v4] drm/i915/lrc: Scrub the GPU state of the guilty hanging request

EIO) This is identical to v2. Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuopp...@linux.intel.com> Cc: Michał Winiarski <michal.winiar...@intel.com> Cc: Michel Thierry <michel.thie...@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursu...@intel.co

Re: [Intel-gfx] [PATCH v2] drm/i915/lrc: Scrub the GPU state of the guilty hanging request

On 4/27/2018 1:35 PM, Chris Wilson wrote: Quoting Michel Thierry (2018-04-27 21:27:46) On 4/27/2018 1:24 PM, Chris Wilson wrote: Previously, we just reset the ring register in the context image such that we could skip over the broken batch and emit the closing breadcrumb. However, on resume

Re: [Intel-gfx] [PATCH v2] drm/i915/lrc: Scrub the GPU state of the guilty hanging request

-by-one from including the ppHSWP in with the register state. Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuopp...@linux.intel.com> Cc: Michał Winiarski <michal.winiar...@intel.com> Cc: Michel Thierry <michel.thie...@intel.com> Cc: Tvr

Re: [Intel-gfx] [PATCH] drm/i915/lrc: Scrub the GPU state of the guilty hanging request

-by: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuopp...@linux.intel.com> Cc: Michał Winiarski <michal.winiar...@intel.com> Cc: Michel Thierry <michel.thie...@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursu...@intel.com> --- drivers

Re: [Intel-gfx] [PATCH libdrm] intel: add support for ICL 11

t. v3: Fix double definition of PCI IDs, update IDs according to bspec and keep them in the same order and rebase (Lucas) Cc: Michel Thierry <michel.thie...@intel.com> Signed-off-by: Paulo Zanoni <paulo.r.zan...@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.v...@intel.com> Si

Re: [Intel-gfx] [PATCH] drm/i915/icl: Correctly clear lost ctx-switch interrupts across reset for Gen11

to the style currently in upstream Suggested-by: Michel Thierry <michel.thie...@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.v...@intel.com> Signed-off-by: Michel Thierry <michel.thie...@intel.com> Signed-off-by: Oscar Mateo <oscar.ma...@intel.com> Cc: Tvrtko Ursulin <t

Re: [Intel-gfx] [PATCH 2/2] drm/i915: Pass the set of guilty engines to i915_reset()

gt; Cc: Michel Thierry <michel.thie...@intel.com> Cc: Jeff McGee <jeff.mc...@intel.com> Cc: Mika Kuoppala <mika.kuopp...@linux.intel.com> --- drivers/gpu/drm/i915/i915_drv.c | 13 ++ drivers/gpu/drm/i915/i915_drv.h | 10 +--- drivers

Re: [Intel-gfx] [PATCH] drm/i915: Treat i915_reset_engine() as guilty until proven innocent

On 4/6/2018 2:30 PM, Chris Wilson wrote: Quoting Michel Thierry (2018-04-06 22:23:21) And I thought we believed in presumption of innocence... On 4/6/2018 2:00 PM, Chris Wilson wrote: If we are resetting just one engine, we know it has stalled. So we can pass the stalled parameter directly

Re: [Intel-gfx] [PATCH] drm/i915: Treat i915_reset_engine() as guilty until proven innocent

...@chris-wilson.co.uk> Cc: Michel Thierry <michel.thie...@intel.com> Cc: Jeff McGee <jeff.mc...@intel.com> Cc: Mika Kuoppala <mika.kuopp...@linux.intel.com> --- drivers/gpu/drm/i915/i915_drv.c | 2 +- drivers/gpu/drm/i915/i915_drv.h | 3 +- d

Re: [Intel-gfx] [PATCH 5/5] drm/i915/icl: Enable RC6 and RPS in Gen11

: Sagar Arun Kamble <sagar.a.kam...@intel.com> Cc: Paulo Zanoni <paulo.r.zan...@intel.com> Signed-off-by: Oscar Mateo <oscar.ma...@intel.com> If it's true that it's the same as Gen10, Reviewed-by: Michel Thierry <michel.thie...@intel.com> --- drivers/gpu/drm/i915/i915

Re: [Intel-gfx] [PATCH 3/5] drm/i915/icl: Handle RPS interrupts correctly for Gen11

4 #define MAX_ENGINE_CLASS 4 +#define OTHER_GTPM_INSTANCE 1 I don't know if this is the right place to define GTPM_INSTANCE, but the other possible place I would think of (intel_ringbuffer.h, were other instances exist) would be also odd since this is not really an engine. May

Re: [Intel-gfx] [PATCH 4/5] drm/i915/icl: Deal with GT INT DW correctly

ogic to call gen11_gt_bank_handler and omit continue, i.e.: + for (bank = 0; bank < 2; bank++) { + if (master_ctl & GEN11_GT_DW_IRQ(bank)) + gen11_gt_bank_handler(i915, bank); + } + + spin_unlock(>irq_lock); } static irqreturn_t gen11_irq_handler(int irq, vo

Re: [Intel-gfx] [PATCH 2/5] drm/i915/icl: Use hw engine class, instance to find irq handler

sulin <tvrtko.ursu...@intel.com> Cc: Michel Thierry <michel.thie...@intel.com> Signed-off-by: Mika Kuoppala <mika.kuopp...@linux.intel.com> ---   drivers/gpu/drm/i915/i915_irq.c | 102 ++--   drivers/gpu/drm/i915/i915_reg.h |   4 +-   2 files cha

Re: [Intel-gfx] [PATCH i-g-t] tests/perf_pmu: Fix usage of for_each_engine_class_instance

ed-off-by: Tvrtko Ursulin <tvrtko.ursu...@intel.com> Reported-by: Michel Thierry <michel.thie...@intel.com> Cc: Michel Thierry <michel.thie...@intel.com> Thanks, Reviewed-by: Michel Thierry <michel.thie...@intel.com> --- lib/igt_gt.h | 12 ++

Re: [Intel-gfx] [PATCH 10/15] drm/i915: Avoid sleeping inside per-engine reset

On 28/03/18 14:52, Chris Wilson wrote: Quoting Michel Thierry (2018-03-28 22:47:55) On 28/03/18 14:18, Chris Wilson wrote: @@ -2094,7 +2095,7 @@ int intel_gpu_reset(struct drm_i915_private *dev_priv, unsigned engine_mask) int retry; int ret; - might_sleep

Re: [Intel-gfx] [PATCH 10/15] drm/i915: Avoid sleeping inside per-engine reset

gen (pre-gen8) have been left as they are only used in full device reset mode. Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuopp...@linux.intel.com> Cc: Michał Winiarski <michal.winiar...@intel.com> CC: Michel Thierry <michel.thie...@inte

[Intel-gfx] [PATCH] drm/i915: warn only once about ddi translation table missing

It's not like it will magically appear or disappear ;) Signed-off-by: Michel Thierry <michel.thie...@intel.com> Cc: Ville Syrjälä <ville.syrj...@linux.intel.com> --- drivers/gpu/drm/i915/intel_ddi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/

[Intel-gfx] [CI 1/2] drm/i915/guc: enable guc interrupts unconditionally in uc_resume

Probably lost while rebasing commit eacd8391f977 ("drm/i915/guc: Keep GuC interrupts enabled when using GuC"). Not really needed since i915_gem_init_hw is called before uc_resume, but it brings symmetry to uc_suspend. Signed-off-by: Michel Thierry <michel.thie...@intel.com> Cc:

[Intel-gfx] [CI 2/2] HAX enable GuC submission for CI

From: Michal Wajdeczko Stolen from... Signed-off-by: Michal Wajdeczko --- drivers/gpu/drm/i915/i915_params.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_params.h

Re: [Intel-gfx] [PATCH v7 10/12] drm/i915/guc: Handle default action received over CT

communication, so some code reuse is still possible. v2: filter disabled messages (Daniele) Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Oscar Mateo <oscar.ma...@intel.com> Reviewed-by: Michel Thierry <michel.thie...@intel.com> #1 ^ still applies for v2

Re: [Intel-gfx] [PATCH v5 00/12] drm/i915/guc: Support for Guc responses and requests

On 3/26/2018 12:48 PM, Michal Wajdeczko wrote: With this series we will be able to receive more data from the Guc. New Guc firmwares will be required to actually use that feature. v4: respin series after 1/2 year break v5: updated after review comments Michal Wajdeczko (12): drm/i915/guc:

Re: [Intel-gfx] [PATCH v5 09/12] drm/i915/guc: Prepare to process incoming requests from CT

) v3: rebased v4: don't name it 'dispatch' (Michel) and fix checkpatch add some documentation (Michal) Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Oscar Mateo <oscar.ma...@intel.com> Cc: Michel Thierry <michel.thie...@intel.com> Cc: Dani

Re: [Intel-gfx] [PATCH v5 10/12] drm/i915/guc: Handle default action received over CT

of the scratch register used in MMIO based communication, so some code reuse is still possible. Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Oscar Mateo <oscar.ma...@intel.com> Reviewed-by: Michel Thierry <michel.thie...@intel.com> ---   drivers/gpu/drm/i915/

Re: [Intel-gfx] [PATCH 5/8] drm/i915/icl: Add reset control register changes

On 3/16/2018 1:28 PM, Daniele Ceraolo Spurio wrote: On 16/03/18 05:14, Mika Kuoppala wrote: From: Michel Thierry <michel.thie...@intel.com> The bits used to reset the different engines/domains have changed in GEN11, this patch maps the reset engine mask bits with the new bits in the

Re: [Intel-gfx] [PATCH v4 11/13] drm/i915/guc: Handle default action received over CT

<oscar.ma...@intel.com> --- Reviewed-by: Michel Thierry <michel.thie...@intel.com> drivers/gpu/drm/i915/intel_guc.c| 5 + drivers/gpu/drm/i915/intel_guc.h| 1 + drivers/gpu/drm/i915/intel_guc_ct.c | 9 + 3 files changed, 15 insertions(+) diff --git a/drivers/gpu/d

Re: [Intel-gfx] [PATCH v4 09/13] drm/i915/guc: Prepare to process incoming requests from CT

) v3: rebased Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Oscar Mateo <oscar.ma...@intel.com> Cc: Michel Thierry <michel.thie...@intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com> --- drivers/gpu/drm/

Re: [Intel-gfx] [PATCH v4 10/13] drm/i915/guc: Enable GuC interrupts when using CT

Mateo <oscar.ma...@intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com> Cc: Michel Thierry <michel.thie...@intel.com> Acked-by: Oscar Mateo <oscar.ma...@intel.com> --- drivers/gpu/drm/i915/intel_uc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) dif

Re: [Intel-gfx] [PATCH v4 08/13] drm/i915/guc: Implement response handling in send_ct()

will WARN if response from GuC does not match caller expectation. v2: fix timeout and checkpatch warnings (Michal) Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Oscar Mateo <oscar.ma...@intel.com> Cc: Michel Thierry <michel.thie...@intel.com> Cc: Dani

Re: [Intel-gfx] [PATCH v4 06/13] drm/i915/guc: Prepare to handle messages from CT RECV buffer

placeholders for actual response/request handlers. v2: misc improvements (Michal) v3: change response detection (Michal) invalid status is protocol error (Michal) v4: rebase Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Oscar Mateo <oscar.ma...@intel.com> Cc: Mi

Re: [Intel-gfx] [PATCH v4 07/13] drm/i915/guc: Use better name for helper wait function

lready. With or without that, Reviewed-by: Michel Thierry <michel.thie...@intel.com> + u32 fence, + u32 *status) { int err; @@ -395,7 +402,7 @@ static int ctch_send(struct intel_guc *guc, intel_guc_notify(guc);

Re: [Intel-gfx] [PATCH v4 05/13] drm/i915/guc: Make event handler a virtual function

_uc.c | 2 ++ 3 files changed, 19 insertions(+), 1 deletion(-) I've gotten used to 'receive', but 'handler' makes sense too. Reviewed-by: Michel Thierry <michel.thie...@intel.com> diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c index 9ce01e5..118db8

Re: [Intel-gfx] [PATCH v4 04/13] drm/i915/guc: Implement response handling in send_mmio()

message Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com> Cc: Oscar Mateo <oscar.ma...@intel.com> Reviewed-by: Michel Thierry <michel.thie...@intel.com> #2 --- drivers/gpu/drm/i915/intel_guc.c | 15

Re: [Intel-gfx] [PATCH v4 03/13] drm/i915/guc: Prepare send() function to accept bigger response

Wajdeczko <michal.wajdec...@intel.com> Cc: Oscar Mateo <oscar.ma...@intel.com> Cc: Michel Thierry <michel.thie...@intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com> Reviewed-by: Michel Thierry <michel.thie...@intel.com> #1 r-b still applies to v3

Re: [Intel-gfx] [PATCH v4 02/13] drm/i915/guc: Add support for data reporting in GuC responses

space after '~' (Michel) update commit message (Daniele) v3: rebase Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Oscar Mateo <oscar.ma...@intel.com> Cc: Michel Thierry <michel.thie...@intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com

Re: [Intel-gfx] [PATCH v4 01/13] drm/i915/guc: Add documentation for MMIO based communication

e we want to keep the same names, looking at intel_guc_fwif.h vs the 'original', we've managed to change the name of almost every single item. Reviewed-by: Michel Thierry <michel.thie...@intel.com> + * The following message **types** are supported: + * + * - **REQUEST**, indicates Host-to-GuC

Re: [Intel-gfx] [PATCH] drm/i915/execlists: Use a locked clear_bit() for synchronisation with interrupt

errupt and leave a context-switch unprocessed, hanging the GPU. Fixes: 767a983ab255 ("drm/i915/execlists: Read the context-status HEAD from the HWSP") Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Michel Thierry <michel.thie...@intel.com> Cc: Tvrtko Ursulin <tv

Re: [Intel-gfx] [PATCH 2/2] drm/i915: Add control flags to i915_handle_error()

@chris-wilson.co.uk> Cc: Jeff McGee <jeff.mc...@intel.com> Cc: Mika Kuoppala <mika.kuopp...@intel.com> Cc: Michel Thierry <michel.thie...@intel.com> Reviewed-by: Michel Thierry <michel.thie...@intel.com> --- drivers/gpu/drm/i915/i915_debugfs.c | 4 +-

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Specify which engines to reset following semaphore/event lockups

t;. Fixes: 14b730fcb8d9 ("drm/i915/tdr: Prepare error handler to accept mask of hung engines") Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuopp...@intel.com> Cc: Michel Thierry <michel.thie...@intel.com> Reviewed-by: Mi

[Intel-gfx] [PATCH] drm/i915/guc: enable guc interrupts unconditionally in uc_resume

Probably lost while rebasing commit eacd8391f977 ("drm/i915/guc: Keep GuC interrupts enabled when using GuC"). Not really needed since i915_gem_init_hw is called before uc_resume, but it brings symmetry to uc_suspend. Signed-off-by: Michel Thierry <michel.thie...@intel.com> Cc:

Re: [Intel-gfx] [PATCH 1/5] drm/i915: Add control flags to i915_handle_error()

On 3/19/2018 5:44 PM, Chris Wilson wrote: Quoting Michel Thierry (2018-03-20 00:39:35) On 3/19/2018 5:18 PM, Chris Wilson wrote: Not all callers want the GPU error to handled in the same way, so expose a control parameter. In the first instance, some callers do not want the heavyweight error

Re: [Intel-gfx] [PATCH 1/5] drm/i915: Add control flags to i915_handle_error()

to i915_reset/i915_reset_engine so that we include the reason for the reset in the dev_notice(), superseding the earlier option to not print that notice. Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Jeff McGee <jeff.mc...@intel.com> Cc: Mika Kuoppala <mika.kuopp...@intel.

Re: [Intel-gfx] [PATCH 2/3] drm/i915: Add control flags to i915_handle_error()

On 16/03/18 14:50, Chris Wilson wrote: Not all callers want the GPU error to handled in the same way, so expose a control parameter. In the first instance, some callers do not want the heavyweight error capture so add a bit to request the state to be captured and saved. Signed-off-by: Chris

Re: [Intel-gfx] [PATCH 1/3] drm/i915: Trim error mask to known engines

: Michał Winiarski <michal.winiar...@intel.com> Please? It papers over the issue in gem_exec_capture... -Chris Reviewed-by: Michel Thierry <michel.thie...@intel.com> --- drivers/gpu/drm/i915/i915_irq.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/d

Re: [Intel-gfx] [PATCH 8/8] drm/i915/icl: Use hw engine class, instance to find irq handler

) Suggested-by: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursu...@intel.com> Cc: Michel Thierry <michel.thie...@intel.com>

Re: [Intel-gfx] [PATCH] drm/i915/huc: Check HuC status in dedicated function

On 14/03/18 15:23, Michal Wajdeczko wrote: On Wed, 14 Mar 2018 21:17:29 +0100, Michel Thierry <michel.thie...@intel.com> wrote: On 14/03/18 13:04, Michal Wajdeczko wrote: We try to keep all HuC related code in dedicated file. There is no need to peek HuC register directly during ha

Re: [Intel-gfx] [PATCH] drm/i915/huc: Check HuC status in dedicated function

On 14/03/18 13:04, Michal Wajdeczko wrote: We try to keep all HuC related code in dedicated file. There is no need to peek HuC register directly during handling getparam ioctl. Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Michel Thierry <michel.thie...@intel.com>

Re: [Intel-gfx] [PATCH] drm/i915/icl: Use hw engine class, instance to find irq handler

Hi, On 3/12/2018 7:41 AM, Mika Kuoppala wrote: Interrupt identity register we already read from hardware contains engine class and instance fields. Leverage these fields to find correct engine to handle the interrupt. add/remove: 0/0 grow/shrink: 0/1 up/down: 0/-160 (-160) Function

Re: [Intel-gfx] [PATCH v2 2/3] drm/i915/error: standardize function style in error capture

tions that don't perform register reads. v2: take i915 from error->i915 (Michal), s/dev_priv/i915, update commit message Cc: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospu..

Re: [Intel-gfx] [PATCH v2] drm/i915/guc: Remove GUC_CTL_DEVICE_INFO parameter

gt; Cc: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Michel Thierry <michel.thie...@intel.com> --- drivers/gpu/drm/i915/intel_guc.c | 24 drivers/gpu/drm/i915/intel_guc_fwif.h | 7 --- 2 files changed,

Re: [Intel-gfx] [PATCH] drm/i915/icl: local_clock returns an u64

On 3/1/2018 10:07 AM, Michel Thierry wrote: So change timeout_ts and use time_after64 in gen11_gt_engine_intr. I just read Chris' original comment about this, so ignore the patch, "The squash should be made, but time_after64 is no more correct since the native 32b/64b wrapped arith

[Intel-gfx] [PATCH] drm/i915/icl: local_clock returns an u64

So change timeout_ts and use time_after64 in gen11_gt_engine_intr. Fixes: 51951ae7ed00 ("drm/i915/icl: Interrupt handling"). Suggested-by: Tvrtko Ursulin <tvrtko.ursu...@intel.com> (long time ago) Signed-off-by: Michel Thierry <michel.thie...@intel.com> Cc:

Re: [Intel-gfx] [PATCH] drm/i915/guc: Removed unused GuC parameters.

On 28/02/18 12:26, Michel Thierry wrote: On 28/02/18 10:42, Piotr Piórkowski wrote: In the i915 driver, there is a function, intel_guc_init_params(), which initializes the GuC parameter block which is passed into the GuC. There is parameter GUC_CTL_DEVICE_INFO with values GfxGtType

Re: [Intel-gfx] [PATCH] drm/i915/guc: Removed unused GuC parameters.

On 28/02/18 10:42, Piotr Piórkowski wrote: In the i915 driver, there is a function, intel_guc_init_params(), which initializes the GuC parameter block which is passed into the GuC. There is parameter GUC_CTL_DEVICE_INFO with values GfxGtType and GfxCoreFamily unused by GuC. This patch remove

Re: [Intel-gfx] [PATCH] drm/i915: Wedged engine mask makes more sense in hex

On 28/02/18 09:18, Tvrtko Ursulin wrote: From: Tvrtko Ursulin <tvrtko.ursu...@intel.com> In decimal its just a weird big number, while in hex can actually log which engines were requested to be wedged. And IGT is not reading the hang reason in this case, so Reviewed-by: Michel T

Re: [Intel-gfx] [PATCH] drm/i915/uc: Start preparing GuC/HuC for reset

On 22/02/18 13:21, Michal Wajdeczko wrote: On Thu, 22 Feb 2018 21:52:39 +0100, Michel Thierry <michel.thie...@intel.com> wrote: On 22/02/18 10:45, Michal Wajdeczko wrote: Right after GPU reset there will be a small window of time during which some of GuC/HuC fields will still show

Re: [Intel-gfx] [PATCH] drm/i915/uc: Start preparing GuC/HuC for reset

On 22/02/18 10:45, Michal Wajdeczko wrote: Right after GPU reset there will be a small window of time during which some of GuC/HuC fields will still show state before reset. Let's start to fix that by sanitizing firmware status as we will use it shortly. Suggested-by: Daniele Ceraolo Spurio

[Intel-gfx] [PATCH] drm/i915: Update missing parts after the rename to i915_request

Mostly doc/print messages that were not updated after commit e61e0f51ba79 ("drm/i915: Rename drm_i915_gem_request to i915_request"). Signed-off-by: Michel Thierry <michel.thie...@intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> --- drivers/gpu/drm/i915/i915_gem_

Re: [Intel-gfx] [PATCH] drm/i915/execlists: Remove the ring advancement under preemption

iarski <michal.winiar...@intel.com> Cc: Michel Thierry <michel.thie...@intel.com> Cc: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursu...@intel.com> Cc: Mika Kuoppala <mika.kuopp...@intel.com> Reviewed-by: Michel Thierry <michel.thie...@

Re: [Intel-gfx] [PATCH 17/20] drm/i915/icl: Add configuring MOCS in new Icelake engines

ngine_id engine_id, int index) return GEN9_VEBOX_MOCS(index); case VCS2: return GEN9_MFX1_MOCS(index); + case VCS3: + return GEN11_MFX2_MOCS(index); default: MISSING_CASE(engine_id); return INVALID_MMIO_REG; --

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