On Wed, May 06, 2020 at 04:32:02PM +0100, Chris Wilson wrote:
> Quoting Mika Kuoppala (2020-05-06 16:20:22)
> > Chris Wilson writes:
> >
> > > Quoting Mika Kuoppala (2020-05-06 15:47:34)
> > >> Aux table invalidation can fail on update. So
> > >> next access may cause memory access to be into
pec: 52890
FYI, this patch fixes some corruption I was seeing.
Tested-by: Rafael Antognolli
> Signed-off-by: Swathi Dhanavanthri
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 11 +--
> 1 file changed, 5 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm
On Wed, Mar 04, 2020 at 04:24:13PM +, Tvrtko Ursulin wrote:
>
> On 04/03/2020 16:02, Rafael Antognolli wrote:
> > On Wed, Mar 04, 2020 at 03:31:44PM +, Tvrtko Ursulin wrote:
> > > From: Tvrtko Ursulin
> > >
> > > Enable FtrPerCtxtPreemptionG
gned-off-by: Tvrtko Ursulin
> Cc: Michał Winiarski
> Cc: Joonas Lahtinen
> Cc: piotr.zdunow...@intel.com
> Cc: michal.mro...@intel.com
> Cc: Tony Ye
> Cc: Rafael Antognolli
Thanks for CC'ing me. I also saw a reply from Jason yesterday, but I
don't see it in the list now (though
On Fri, Feb 28, 2020 at 02:10:50PM -0800, Souza, Jose wrote:
> Can you guys help in this one? Check Matt comment bellow.
>
> On Fri, 2020-02-28 at 14:07 -0800, Matt Roper wrote:
> > On Thu, Feb 27, 2020 at 02:01:01PM -0800, José Roberto de Souza
> > wrote:
> > > This will fix a memory coherence
On Tue, Feb 18, 2020 at 03:44:49PM -0800, Rafael Antognolli wrote:
> On Tue, Feb 18, 2020 at 02:47:10PM -0500, Matt Atwood wrote:
> > Disable Push Constant buffer addition for A0, which can cause FIFO
> > underruns.
> >
> > Fix a minor white space issue while we're
On Tue, Feb 18, 2020 at 02:47:10PM -0500, Matt Atwood wrote:
> Disable Push Constant buffer addition for A0, which can cause FIFO
> underruns.
>
> Fix a minor white space issue while we're here.
>
> Bspec: 52890
> Cc: Rafael Antognolli
> Signed-off-by: Matt Atwood
>
On Fri, Feb 14, 2020 at 09:10:38AM -0800, Matt Roper wrote:
> On Wed, Feb 12, 2020 at 11:17:28AM -0800, Rafael Antognolli wrote:
> > It's not clear whether this workaround is final yet, but the BSpec
> > indicates that userspace needs to set bit 9 of this register on demand:
> &
BugLink: https://gitlab.freedesktop.org/mesa/mesa/issues/2501
Signed-off-by: Rafael Antognolli
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
inde
just yet but would be good to easily
enable it in the future.
Acked-by: Rafael Antognolli
> Signed-off-by: Michał Winiarski
> Cc: Anuj Phogat
> Cc: Joonas Lahtinen
> Cc: Matt Roper
> Cc: Rafael Antognolli
> Cc: Chris Wilson
> ---
> drivers/gpu/drm/i915/intel_workaroun
n thread group level.
Acked-by: Rafael Antognolli
> Signed-off-by: Michał Winiarski
> Cc: Anuj Phogat
> Cc: Joonas Lahtinen
> Cc: Matt Roper
> Cc: Rafael Antognolli
> Tested-by: Anuj Phogat
> Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/intel_workaround
On Tue, Jan 08, 2019 at 12:32:05PM -0800, Kenneth Graunke wrote:
> On Tuesday, January 8, 2019 7:53:05 AM PST Joonas Lahtinen wrote:
> > + Ken/Jason for Mesa
> > Quoting Matt Roper (2019-01-07 21:19:31)
> > > On Mon, Jan 07, 2019 at 01:23:50PM +0100, Michał Winiarski wrote:
> > > > On Mon, Jan 07,
Matches bspec.
Reviewed-by: Rafael Antognolli <rafael.antogno...@intel.com>
On Wed, Mar 07, 2018 at 02:09:12PM -0800, Rodrigo Vivi wrote:
> "Clock gating bug in GWL may not clear barrier state when an EOT
> is received, causing a hang the next time that barrier is used."
On Mon, Mar 05, 2018 at 05:20:00PM -0800, Rodrigo Vivi wrote:
> No functional change. WA is already properly applied.
> but in different databases it has different names.
> Let's document all of them to avoid future confusion.
Works for me.
Reviewed-by: Rafael Antognolli <ra
changelog and comments.
v3: Explain that PIPE_CONTROL is actually 6 dwords, and that we advance
10 more dwords because of that.
Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
Cc: Chris Wilson <ch...@chris-wilson.co.uk>
Acked-by: Chris Wilson <ch...@chris-wilson.co.u
On Fri, Jan 26, 2018 at 11:17:01PM +, Chris Wilson wrote:
> Quoting Rafael Antognolli (2018-01-26 23:05:24)
> > This workaround should prevent a bug that can be hit on a context
> > restore. To avoid the issue, we must emit a PIPE_CONTROL with CS stall
> > (0x7a04
to programming 3DSTATE_SAMPLE_PATTERN.
References: HSD#1939868
v2:
- More descriptive changelog and comments.
- Fix math when counting dwords.
Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
Cc: Chris Wilson <ch...@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/inte
On Fri, Jan 26, 2018 at 09:55:58AM -0800, Rafael Antognolli wrote:
> On Fri, Jan 26, 2018 at 08:23:13AM +, Chris Wilson wrote:
> > Quoting Rafael Antognolli (2018-01-26 01:26:34)
> > > Write a PIPE_CONTROL with CS stall followed by 14 dwords of 0 in the
> >
On Fri, Jan 26, 2018 at 08:23:13AM +, Chris Wilson wrote:
> Quoting Rafael Antognolli (2018-01-26 01:26:34)
> > Write a PIPE_CONTROL with CS stall followed by 14 dwords of 0 in the
> > indirect context wa bb.
>
> 14 MI_NOOPS following? That isn't what you wrote in the
Write a PIPE_CONTROL with CS stall followed by 14 dwords of 0 in the
indirect context wa bb.
References: HSD#1939868
Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
---
drivers/gpu/drm/i915/intel_lrc.c | 23 ++-
1 file changed, 22 insertions(+), 1 de
This workaround supposedly fixes some hangs in the VF unit.
Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demar...@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_pm.c | 5 +
2 files changed,
There seems to be another clock gating issue which the workaround is
described as:
"WA: Set 0xE4F0[1] = 1 to disable Early EOT of thread."
Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demar...@intel.com>
---
There seems to be another clock gating issue which the workaround is
described as:
"WA: Set 0xE4F0[1] = 1 to disable Early EOT of thread."
Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h| 1 +
drivers/gpu/drm/i915/i
This workaround supposedly fixes some hangs in the VF unit.
Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_pm.c | 5 +
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_r
the value is lost entirely is more worrying though -- but it
> clearly suggests that it is not a masked register in the context image,
> so unify both w/a to use the original rmw.
Thanks for fixing this.
Reviewed-by: Rafael Antognolli <rafael.antogno...@intel.com>
> Fixes:
On Fri, Nov 10, 2017 at 09:21:51PM +, Chris Wilson wrote:
> Quoting Rafael Antognolli (2017-11-03 18:30:27)
> > The workaround for this is described as:
> >
> > "if RenderSurfaceState.Num_Multisamples > 1, disable RCC clock gating if
> > RenderSurfaceState.N
This patch, along with the respective ones for Mesa, does fix the gl
timestamp query piglit failures on CNL. So it is
Tested-by: Rafael Antognolli <rafael.antogno...@intel.com>
On Thu, Nov 02, 2017 at 04:29:46PM +, Lionel Landwerlin wrote:
> We use to have this fixed per g
ble RCC clock gating.
Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h| 1 +
drivers/gpu/drm/i915/intel_engine_cs.c | 3 +++
2 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i9
On Wed, Nov 01, 2017 at 02:11:05PM -0700, Rodrigo Vivi wrote:
> On Wed, Nov 01, 2017 at 04:32:35PM +0000, Rafael Antognolli wrote:
> > The workaround for this is described as:
> >
> > "if RenderSurfaceState.Num_Multisamples > 1, disable RCC clock gating if
> >
ge (specially the GEN10_READ_HIT_WRITEONLY_DISABLE bit)
improves CNL stability by avoiding some of the hangs seen in the
platform.
Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h| 2 ++
drivers/gpu/drm/i915/intel_engine_cs.c | 5 +
2 files changed, 7
I can confirm this fixes my CNL issues, and it's what we could
understand from the sparse documentation.
Tested-by: Rafael Antognolli <rafael.antogno...@intel.com>
On Thu, Oct 05, 2017 at 03:26:40PM -0700, Rodrigo Vivi wrote:
> WaSendPushConstantsFromMMIO: "If not using RS, we
Patch is
Reviewed-by: Rafael Antognolli <rafael.antogno...@intel.com>
On Fri, Mar 24, 2017 at 04:45:01PM -0700, Jason Ekstrand wrote:
> A gem handle of 0 can be used to check for whether or not 48-bit
> addressing is available. This keeps aubdump from failing on you if
> you try
Hi Mario, please see below...
On Wed, Jan 25, 2017 at 04:43:58PM +, mario.limoncie...@dell.com wrote:
> Thanks for your comments. Some nested below.
>
> > -Original Message-
> > From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
> > Sent: Wednesday, January 25, 2017 9:57 AM
/wip-fence
So in case it helps, you can add a
Tested-by: Rafael Antognolli <rafael.antogno...@intel.com>
PS: I can test it with this last series and everything more up to date,
if it will help to get this patch landed sooner.
Cheers,
Rafael
On Mon, Nov 14, 2016 at 08:57:03AM +, Chris
Hi Chris,
On Thu, Aug 25, 2016 at 10:08:33AM +0100, Chris Wilson wrote:
> Allow the caller to pass in an fd to an array of fences to control
> serialisation of the execbuf in the kernel and on the GPU, and in return
> allow creation of a fence fd for signaling the completion (and flushing)
> of
a kernel panick will follow.
Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
---
tests/sw_sync.c | 28
1 file changed, 28 insertions(+)
diff --git a/tests/sw_sync.c b/tests/sw_sync.c
index 4336659..31cde50 100644
--- a/tests/sw_sync.c
+++ b/tests/sw_
it.
This patch fixes a kernel panic that can be triggered by creating a fence that
is expired (or increasing the timeline until it expires), then creating a
merged fence out of it, and deleting the merged fence. This will make the
original expired fence's refcount go to zero.
Signed-off-by: Rafael
rate and max lane count
- check seek position after reading
- merge all subtests into a single one.
Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
---
tests/Makefile.sources | 1 +
tests/kms_dp_aux_dev.c | 190 +
2 files c
, to confirm 0 is returned
- seek one more byte and confirm that EINVAL is returned
- try to read 64 bytes when at 8 bytes from the end of the
address space
- try to read 64 bytes at the address 0.
So far, no write checks are done.
Signed-off-by: Rafael Antognolli
On Fri, Feb 12, 2016 at 02:01:11PM +0200, Ville Syrjälä wrote:
> On Fri, Jan 22, 2016 at 09:15:31AM -, Patchwork wrote:
> > == Summary ==
> >
> > Built on 8fe9e785ae04fa7c37f7935cff12d62e38054b60 drm-intel-nightly:
> > 2016y-01m-21d-11h-02m-42s UTC integration manifest
> >
> > Test
amdgpu calls drm_dp_aux_unregister()
before drm_connector_unregister().)
Cc: Rafael Antognolli <rafael.antogno...@intel.com>
Cc: Ville Syrjälä <ville.syrj...@linux.intel.com>
Cc: Alex Deucher <alexander.deuc...@amd.com>
Signed-off-by: Lukas Wunner <lu...@wunner.de>
---
drivers
The module_init and module_exit functions will start here, and call the
subsequent init's and exit's.
v10:
- Keep __init on drm_fb_helper init function.
- Move MODULE_* macros to the common file.
Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
---
drivers/gpu/drm/Ma
This series implement support to a drm_dp_aux chardev that allows reading and
writing an arbitrary amount of bytes to arbitrary dpcd register addresses using
regular read, write and lseek operations.
Lukas Wunner (1):
drm/radeon: Fix WARN_ON if DRM_DP_AUX_CHARDEV is enabled
Rafael Antognolli
ther minor suggestions from Ville
v7:
- style fixes
- error handling fixes
v8:
- more error handling fixes
v9:
- remove module_init and module_exit, and add drm_dp_aux_dev_init/exit
to drm_kms_helper_init/exit.
Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
---
drivers
of the drm_connector device now. Calling
drm_dp_aux_unregister() before prevents them from being destroyed
twice.
v10:
- move aux_fini() to connector_unregister(), instead of moving
drm_dp_aux_unregister() outside of connector_register().
Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.
u, Dec 03, 2015 at 02:54:02PM -0800, Rafael Antognolli wrote:
> > So far, the i915 driver and some other drivers set it to the drm_device,
> > which doesn't allow one to know which DP a given aux channel is related
> > to. Changing this to be the drm_connector provides proper nest
of the drm_connector device now. Calling
drm_dp_aux_unregister() before prevents them from being destroyed
twice.
Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
---
drivers/gpu/drm/i915/intel_dp.c | 22 --
1 file changed, 4 insertions(+), 18 deletions(-)
diff
This series implement support to a drm_dp_aux chardev that allows reading and
writing an arbitrary amount of bytes to arbitrary dpcd register addresses using
regular read, write and lseek operations.
Rafael Antognolli (3):
drm/kms_helper: Add a common place to call init and exit functions
ther minor suggestions from Ville
v7:
- style fixes
- error handling fixes
v8:
- more error handling fixes
v9:
- remove module_init and module_exit, and add drm_dp_aux_dev_init/exit
to drm_kms_helper_init/exit.
Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
---
drivers
The module_init and module_exit functions will start here, and call the
subsequent init's and exit's.
Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
---
drivers/gpu/drm/Makefile| 4 ++-
drivers/gpu/drm/drm_fb_helper.c | 9 +++
drivers/g
On Tue, Nov 24, 2015 at 10:31:41PM +0200, Ville Syrjälä wrote:
> On Mon, Nov 02, 2015 at 12:33:48PM -0800, Rafael Antognolli wrote:
> > So far, the i915 driver and some other drivers set it to the drm_device,
> > which doesn't allow one to know which DP a given aux cha
it
to the drm_connector.
This also removes the need to add a sysfs link for the i2c device under
the connector, as it will already be there.
Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
---
drivers/gpu/drm/i915/intel_dp.c | 19 ++-
1 file changed, 2 insertions(
ther minor suggestions from Ville
v7:
- style fixes
- error handling fixes
v8:
- more error handling fixes
Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
---
drivers/gpu/drm/Kconfig | 8 +
drivers/gpu/drm/Makefile | 1 +
drivers/gpu/drm/drm_dp
This series implement support to a drm_dp_aux chardev that allows reading and
writing an arbitrary amount of bytes to arbitrary dpcd register addresses using
regular read, write and lseek operations.
Rafael Antognolli (2):
drm/dp: Add a drm_aux-dev module for reading/writing dpcd registers
On Fri, Oct 30, 2015 at 12:04:17PM +0200, Ville Syrjälä wrote:
> On Thu, Oct 29, 2015 at 04:23:45PM -0700, Rafael Antognolli wrote:
> > This module is heavily based on i2c-dev. Once loaded, it provides one
> > dev node per DP AUX channel, named drm_dp_auxN, where N is an integer
ther minor suggestions from Ville
v7:
- style fixes
- error handling fixes
Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
---
drivers/gpu/drm/Kconfig | 8 +
drivers/gpu/drm/Makefile | 1 +
drivers/gpu/drm/drm_dp_aux_dev.c | 374
it
to the drm_connector.
This also removes the need to add a sysfs link for the i2c device under
the connector, as it will already be there.
Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
---
drivers/gpu/drm/i915/intel_dp.c | 19 ++-
1 file changed, 2 insertions(
This series implement support to a drm_dp_aux chardev that allows reading and
writing an arbitrary amount of bytes to arbitrary dpcd register addresses using
regular read, write and lseek operations.
Rafael Antognolli (2):
drm/dp: Add a drm_aux-dev module for reading/writing dpcd registers
, if
the connector device pointer was correctly set in the aux helper struct.
Two main operations are provided on the registers read and write. The
address of the register to be read or written is given using lseek. The
seek position is updated upon read or write.
Signed-off-by: Rafael Antognolli <rafael.anto
it
to the drm_connector.
This also removes the need to add a sysfs link for the i2c device under
the connector, as it will already be there.
Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
---
drivers/gpu/drm/i915/intel_dp.c | 19 ++-
1 file changed, 2 insertions(
"connector" attribute
- set aux.dev to the connector drm_connector device, instead of
drm_device
v6:
- Use atomic_t for usage count
- Use a mutex instead of spinlock for idr lock
- Destroy chardev immediately on unregister
- other minor suggestions from Ville
Rafael Antognolli (2)
s Wunner wrote:
> > > > On Mon, Sep 28, 2015 at 04:45:35PM -0700, Rafael Antognolli wrote:
> > > > > This is useful to determine which connector owns this AUX channel.
> > > >
> > > > WTF? I posted a patch in August which does exactly that
"connector" attribute
- set aux.dev to the connector drm_connector device, instead of
drm_device
Rafael Antognolli (2):
drm/dp: Add a drm_aux-dev module for reading/writing dpcd registers.
drm/dp: Set aux.dev to the drm_connector device, instead of
drm_device.
drivers/gpu/d
it
to the drm_connector.
This also removes the need to add a sysfs link for the i2c device under
the connector, as it will already be there.
Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
---
drivers/gpu/drm/i915/intel_dp.c | 19 ++-
1 file changed, 2 insertions(
, if
the connector device pointer was correctly set in the aux helper struct.
Two main operations are provided on the registers read and write. The
address of the register to be read or written is given using lseek. The
seek position is updated upon read or write.
Signed-off-by: Rafael Antognolli <rafael.anto
On Tue, Sep 29, 2015 at 02:49:20PM +0200, Lukas Wunner wrote:
> Hi Rafael,
>
> On Mon, Sep 28, 2015 at 04:45:35PM -0700, Rafael Antognolli wrote:
> > This is useful to determine which connector owns this AUX channel.
>
> WTF? I posted a patch in August which does
Thanks Ville for the review, I'm addressing all the issues but have some
questions on the ones mentioned below:
On Tue, Sep 29, 2015 at 05:09:23PM +0300, Ville Syrjälä wrote:
> On Mon, Sep 28, 2015 at 04:45:36PM -0700, Rafael Antognolli wrote:
> > This module is heavily based on i2c-
, if
the connector device pointer was correctly set in the aux helper struct.
Two main operations are provided on the registers read and write. The
address of the register to be read or written is given using lseek. The
seek position is updated upon read or write.
Signed-off-by: Rafael Antognolli <rafael.anto
This is useful to determine which connector owns this AUX channel.
Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
---
drivers/gpu/drm/i915/intel_dp.c | 1 +
include/drm/drm_dp_helper.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_
is now a boolean
- add inline stub functions to avoid breakage when this option is disabled
v4:
- fix build system changes - actually disable this module when not selected.
Rafael Antognolli (2):
drm/dp: Store the drm_connector device pointer on the helper.
drm/dp: Add a drm_aux-dev module
, to confirm 0 is returned
- seek one more byte and confirm that EINVAL is returned
- try to read 64 bytes when at 8 bytes from the end of the
address space
- try to read 64 bytes at the address 0.
So far, no write checks are done.
Signed-off-by: Rafael Antognolli
On Wed, Jul 29, 2015 at 10:26:53AM +0200, Daniel Vetter wrote:
On Tue, Jul 28, 2015 at 10:05:21PM +, Vivi, Rodrigo wrote:
On Tue, 2015-07-28 at 13:25 -0700, Rafael Antognolli wrote:
On Thu, Jul 23, 2015 at 04:35:50PM -0700, Rodrigo Vivi wrote:
By Vesa DP 1.2 spec TEST_CRC_COUNT
earlier, this is required.
Reviewed-by: Rafael Antognolli rafael.antogno...@intel.com
---
drivers/gpu/drm/i915/intel_dp.c | 89
+++--
1 file changed, 50 insertions(+), 39 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915
stoped.
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
Reviewed-by: Rafael Antognolli rafael.antogno...@intel.com
---
drivers/gpu/drm/i915/intel_dp.c | 22 +++---
drivers/gpu/drm/i915/intel_drv.h | 1 +
2 files changed, 20 insertions(+), 3 deletions(-)
diff --git
On Thu, Jul 23, 2015 at 04:35:50PM -0700, Rodrigo Vivi wrote:
By Vesa DP 1.2 spec TEST_CRC_COUNT is a 4 bit wrap counter which
increments each time the TEST_CRC_x_x are updated.
However if we are trying to verify the screen hasn't changed we get
same (count, crc) pair twice. Without this
that the crc count really restarted,
became 0 and then 1 again. So I think this workaround is needed.
Reviewed-by: Rafael Antognolli rafael.antogno...@intel.com
---
drivers/gpu/drm/i915/intel_dp.c | 42
+---
drivers/gpu/drm/i915/intel_drv.h | 8 +++-
2 files
:
if (drm_dp_dpcd_readb(intel_dp-aux, DP_TEST_SINK, buf) 0) {
ret = -EIO;
goto out;
Nice cleanup on exit.
Reviewed-by: Rafael Antognolli rafael.antogno...@intel.com
--
Rafael
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http
.
Not sure if this is a problem though, since the patches are submitted
together. If not, then
Reviewed-by: Rafael Antognolli rafael.antogno...@intel.com
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
drivers/gpu/drm/i915/intel_dp.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions
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