On Wed, Mar 04, 2020 at 03:31:44PM +0000, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursu...@intel.com>
>
> Enable FtrPerCtxtPreemptionGranularityControl bit and select thread-
> group as the default preemption level.
>
> v2:
> * Remove register whitelisting (Rafael, Tony).
>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursu...@intel.com>
> Cc: Michał Winiarski <michal.winiar...@intel.com>
> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com>
> Cc: piotr.zdunow...@intel.com
> Cc: michal.mro...@intel.com
> Cc: Tony Ye <tony...@intel.com>
> Cc: Rafael Antognolli <rafael.antogno...@intel.com>
Thanks for CC'ing me. I also saw a reply from Jason yesterday, but I
don't see it in the list now (though my mail client a mess lately).
But he asked whether it's possible for Media and OpenCL drivers to
also disable mid-thread preemption through the
INTERFACE_DESCRIPTOR_DATA, instead of from the kernel side, so we could
try to experiment with it in the future.
Also, do you have an idea of how broken it is? Or is it just not tested
because no driver is currently implementing it? And do you know if the
windows 3D drivers implement it at all? I see code in the driver that
seems to me that it's only disabled in certain cases...
To summarize, I think we should either:
1) Disable mid-thread preemption from the kernel and not whitelist
the register (just like you do in this patch); or
2) Not do anything at all from the kernel, and let userspace disable
it if needed.
I think 2) is better, if it's not an issue to the other userspace
drivers (OpenCL and Media).
--
Rafael
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 9 +++++++--
> 1 file changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index cb7d85c42f13..7be71a1a5719 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -601,6 +601,11 @@ static void tgl_ctx_workarounds_init(struct
> intel_engine_cs *engine,
> */
> wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK,
> FF_MODE2_TDS_TIMER_128, 0);
> +
> + /* WaDisableGPGPUMidThreadPreemption:tgl */
> + WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1,
> + GEN9_PREEMPT_GPGPU_LEVEL_MASK,
> + GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL);
> }
>
> static void
> @@ -1475,8 +1480,8 @@ rcs_engine_wa_init(struct intel_engine_cs *engine,
> struct i915_wa_list *wal)
> PSDUNIT_CLKGATE_DIS);
> }
>
> - if (IS_GEN_RANGE(i915, 9, 11)) {
> - /*
> FtrPerCtxtPreemptionGranularityControl:skl,bxt,kbl,cfl,cnl,icl */
> + if (IS_GEN_RANGE(i915, 9, 12)) {
> + /*
> FtrPerCtxtPreemptionGranularityControl:skl,bxt,kbl,cfl,cnl,icl,tgl */
> wa_masked_en(wal,
> GEN7_FF_SLICE_CS_CHICKEN1,
> GEN9_FFSC_PERCTX_PREEMPT_CTRL);
> --
> 2.20.1
>
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