next.
Is it OK if we just cherry-pick that into drm-intel-fixes? Dave / Daniel?
--
Ville Syrjälä
Intel
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
t; > > + setlocale(LC_ALL, oldlocale);
> > Why we are first setting "C" locale and then restoring it? Is there a moment
> > during mesurement when it is changed?
>
> No, but it may be set in the environment for pretty-printing of outpu
ds the framebuffer and out-fence for a writeback connector. As
> @@ -995,6 +1038,12 @@ struct drm_connector {
> struct drm_property *content_protection_property;
>
> /**
> + * @colorspace_property: Connector property to set the suitable
> + * colorspace supported by the
orspace(struct hdmi_avi_infoframe *frame,
> + const struct drm_connector_state *conn_state);
> +
> void
> drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
> struct drm_connector *connector,
> --
> 1.9.1
>
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
on displays side.
>
> No functional change and no manual interaction to generate
> this patch.
>
> It is only:
>
> sed -si -e 's/has_gmch_display/has_gmch/g' \
> -e 's/HAS_GMCH_DISPLAY/HAS_GMCH/g' drivers/gpu/drm/i915/*{c,h}
>
> Cc: José R
On Tue, Feb 05, 2019 at 05:32:16PM +, Shankar, Uma wrote:
>
>
> >-Original Message-----
> >From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
> >Sent: Tuesday, February 5, 2019 10:02 PM
> >To: Shankar, Uma
> >Cc: intel-gfx@lists.freedesktop.
On Tue, Feb 05, 2019 at 03:49:42PM +0100, Maarten Lankhorst wrote:
> Op 05-02-2019 om 14:39 schreef Ville Syrjälä:
> > On Tue, Feb 05, 2019 at 12:21:19PM +0100, Maarten Lankhorst wrote:
> >> Op 04-02-2019 om 21:22 schreef Ville Syrjala:
> >>> From: Ville Syrjälä
>
On Mon, Feb 04, 2019 at 09:33:08PM +, Chris Wilson wrote:
> Quoting Ville Syrjala (2019-02-04 21:16:44)
> > From: Ville Syrjälä
> >
> > We generally omit register polling from the i915_reg_rw tracepoint.
> > Understandable since polling could generate a lot of
ase));
>
> - crtc_state->scaler_state = scaler_state;
> - crtc_state->shared_dpll = shared_dpll;
> - crtc_state->dpll_hw_state = dpll_hw_state;
> - crtc_state->pch_pfit.force_thru = force_thru;
> - crtc_state->ips_force_disable = ips_force_disable
ify the most significant bits of the color after performing readout.
>
> At boot time the pipe color is already sanitized to full black as
> required by ABI, so the new readout here won't break that requirement.
>
> Suggested-by: Ville Syrjälä
> Cc: Ville Syrjälä
> S
On Tue, Feb 05, 2019 at 07:29:21PM -0800, Kevin Strasser wrote:
> Change the api in order to enable callers that can't supply a valid
> intel_plane pointer, as would be the case prior to calling
> drm_universal_plane_init.
>
> Cc: Uma Shankar
> Cc: Shashank Sharma
&g
ted
> * Color Keying not supported
>
> v2:
> - Drop handling pixel normalize register
> - Don't use icl_is_hdr_plane too early
>
> v3:
> - Use refactored icl_is_hdr_plane (Ville)
> - Use u32 instead of uint32_t (Ville)
>
> Cc: Uma Shankar
> Cc: Shasha
On Wed, Feb 06, 2019 at 01:04:19AM +, Souza, Jose wrote:
> On Tue, 2019-02-05 at 22:50 +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > The unused bits on PLANE_WM & co. are hardwired to zero. So no
> > need to worry about reading the extra bit on
_kms_helper_hotplug_event()
That of course requires that no one is hanging on to the
kref(s). The lifetime of the references isn't really clear
to me, but I'll take your word that it works.
Reviewed-by: Ville Syrjälä
> + }
> }
> }
> --
> 2.20.1
>
ude Paul
> Cc: Imre Deak
> Cc: Daniel Vetter
Reviewed-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/intel_dp.c | 6 ++
> 1 file changed, 2 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index c2399
On Thu, Feb 07, 2019 at 04:49:47PM +0100, Maarten Lankhorst wrote:
> Op 05-02-2019 om 17:08 schreef Ville Syrjala:
> > From: Ville Syrjälä
> >
> > On pre-HSW gamma mode is configured via PIPECONF. The bits are
> > the same except shifted up, so we can reuse just s
On Thu, Feb 07, 2019 at 04:58:22PM +0100, Maarten Lankhorst wrote:
> Op 05-02-2019 om 17:08 schreef Ville Syrjala:
> > From: Ville Syrjälä
> >
> > On g4x+ we depend on the primary plane DSPCNTR gamma/csc enable
> > bits for the pipe bottom color. To guarantee that th
On Thu, Feb 07, 2019 at 06:27:19PM +0200, Ville Syrjälä wrote:
> On Thu, Feb 07, 2019 at 04:49:47PM +0100, Maarten Lankhorst wrote:
> > Op 05-02-2019 om 17:08 schreef Ville Syrjala:
> > > From: Ville Syrjälä
> > >
> > > On pre-HSW gamma mode is configured via P
On Tue, Feb 05, 2019 at 07:22:32PM +, Shankar, Uma wrote:
>
>
> >-Original Message-
> >From: dri-devel [mailto:dri-devel-boun...@lists.freedesktop.org] On Behalf Of
> >Ville Syrjälä
> >Sent: Tuesday, February 5, 2019 11:43 PM
> &g
On Thu, Feb 07, 2019 at 04:46:54PM +0100, Maarten Lankhorst wrote:
> Hey,
>
> Op 05-02-2019 om 17:08 schreef Ville Syrjala:
> > From: Ville Syrjälä
> >
> > The LUTs are single buffered so we should program them after
> > the double buffered pipe updates have
anongit.freedesktop.org/xorg/app/intel-gpu-tools
> Patchwork_12171: 649cf2d353ecd5b115d958c61f53000cf1cbd4c6 @
> git://anongit.freedesktop.org/gfx-ci/linux
>
>
> == Linux commits ==
>
> 649cf2d353ec drm/i915: Update DSPCNTR gamma/csc bits during crtc_enable()
> fed3bc8c
On Thu, Feb 07, 2019 at 03:11:59PM -0800, Lucas De Marchi wrote:
> On Thu, Feb 7, 2019 at 9:33 AM Ville Syrjala
> wrote:
> >
> > From: Ville Syrjälä
> >
> > Rather than try to maintain some magic relationship between the link
> > rates and the index into the
On Fri, Feb 08, 2019 at 12:36:25PM +, Sharma, Shashank wrote:
> Regards
> Shashank
>
> > -Original Message-
> > From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf
> > Of
> > Shankar, Uma
> > Sent: Friday, February 8, 201
On Fri, Feb 08, 2019 at 06:36:39PM +0530, Sharma, Shashank wrote:
> Regards
>
> Shashank
>
> On 2/8/2019 6:22 PM, Ville Syrjälä wrote:
> > On Fri, Feb 08, 2019 at 12:36:25PM +, Sharma, Shashank wrote:
> >> Regards
> >> Shashank
> >>
> &
On Fri, Feb 08, 2019 at 07:36:24PM +0530, Sharma, Shashank wrote:
> Regards
>
> Shashank
>
> On 2/8/2019 7:00 PM, Ville Syrjälä wrote:
> > On Fri, Feb 08, 2019 at 06:36:39PM +0530, Sharma, Shashank wrote:
> >> Regards
> >>
> >> Shashank
&g
On Fri, Feb 08, 2019 at 03:03:34PM +, Shankar, Uma wrote:
>
>
> >-Original Message-----
> >From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
> >Sent: Friday, February 8, 2019 8:08 PM
> >To: Sharma, Shashank
> >Cc: Shankar, Uma ; intel-g
.
> >
> > Fixes: 04ebaadb9f2d ("drm/i915/opregion: handle VBT sizes bigger than 6 KB")
> > Cc: Ville Syrjälä
> > Cc: Imre Deak
> > Signed-off-by: Jani Nikula
> > ---
> > drivers/gpu/drm/i915/intel_opregion.c | 11 +--
> &g
On Fri, Feb 08, 2019 at 05:57:53PM +0200, Ville Syrjälä wrote:
> On Fri, Feb 08, 2019 at 05:09:51PM +0200, Jani Nikula wrote:
> > On Fri, 08 Feb 2019, Jani Nikula wrote:
> > > The u32 version field encodes major version in the high word. We've been
> >
ndle VBT sizes bigger than 6 KB")
> Cc: Ville Syrjälä
> Cc: Imre Deak
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/intel_opregion.c | 11 +--
> 1 file changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_opregion.c
&g
relative vs. absolute conditional on the opregion version,
> bumped for the purpose. Turned out there are machines relying on
> absolute RVDA in the wild.
>
> v3: Fix the version checks
>
> Fixes: 04ebaadb9f2d ("drm/i915/opregion: handle VBT sizes bigger than 6 KB")
>
On Fri, Feb 08, 2019 at 09:00:59PM +0200, Jani Nikula wrote:
> On Fri, 08 Feb 2019, Ville Syrjälä wrote:
> > On Fri, Feb 08, 2019 at 08:42:53PM +0200, Jani Nikula wrote:
> >> Starting from opregion version 2.1 (roughly corresponding to ICL+) the
> >> RVDA field is rel
current
> hardware behaves. We can create a separate task and work within team to come
> up with different ideas
> to test these in CI.
At least one problem is that the uapi doesn't allow us to say 1.0
which is what we need for all the interpolated gamma modes. Not sure
if the tes
intel_attach_force_audio_property(connector);
> intel_attach_broadcast_rgb_property(connector);
> intel_attach_aspect_ratio_property(connector);
> +
> + /*
> + * Attach Colorspace property for Non LSPCON based device
> + * ToDo: This needs to be extended for LS
e);
> +
> +void
> +drm_hdmi_avi_infoframe_colorspace(struct hdmi_avi_infoframe *frame,
> + const struct drm_connector_state *conn_state);
> +
> void
> drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
> struct drm_connector *connector,
> --
> 1.9.1
>
> ___
> dri-devel mailing list
> dri-de...@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
--
Ville Syrjälä
Intel
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
On Tue, Feb 12, 2019 at 09:30:50PM +, Shankar, Uma wrote:
>
>
> >-Original Message-----
> >From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
> >Sent: Tuesday, February 12, 2019 10:35 PM
> >To: Shankar, Uma
> >Cc: intel-gfx@lists.freedesktop.
-
> include/uapi/drm/drm_fourcc.h| 11 ++
> 6 files changed, 112 insertions(+), 15 deletions(-)
>
> --
> 2.7.4
--
Ville Syrjälä
Intel
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
orresponding boost to the evasion window.
We should have exited PSR before the evasion. Is that code not working?
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105870
> Signed-off-by: Chris Wilson
> Cc: Jani Nikula
> Cc: Ville Syrjälä
> Cc: Paulo Zanon
On Wed, Feb 13, 2019 at 11:44:44AM -0800, Clinton Taylor wrote:
>
> On 2/13/19 8:54 AM, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > We'll need to poke at the "ignore lines" bit in the skl+
> > watermark registers for a w/a. Include that b
On Thu, Feb 14, 2019 at 12:38:22PM -0800, Rodrigo Vivi wrote:
> On Thu, Feb 14, 2019 at 09:22:18PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > DP CRCs don't really work on g4x. If you want any CRCs on DP you must
> > select the CRC source before th
On Thu, Feb 14, 2019 at 12:47:23PM -0800, Rodrigo Vivi wrote:
> On Thu, Feb 14, 2019 at 09:22:19PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > On skl the crc registers were extended to provide plane crcs
> > for up to 7 planes. Add the new crc sources
On Thu, Feb 14, 2019 at 05:45:31PM -0800, Dhinakaran Pandiyan wrote:
> On Thu, 2019-02-14 at 17:32 -0800, Dhinakaran Pandiyan wrote:
> > On Thu, 2019-02-14 at 21:22 +0200, Ville Syrjala wrote:
> > > From: Ville Syrjälä
> > >
> > > The "pipe" a
On Thu, Feb 14, 2019 at 06:26:29PM -0800, Dhinakaran Pandiyan wrote:
> On Thu, 2019-02-14 at 21:22 +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > DP CRCs don't really work on g4x. If you want any CRCs on DP you must
> > select the CRC source before th
On Fri, Feb 15, 2019 at 01:06:32PM -0800, Dhinakaran Pandiyan wrote:
> On Fri, 2019-02-15 at 14:47 +0200, Ville Syrjälä wrote:
> > On Thu, Feb 14, 2019 at 06:26:29PM -0800, Dhinakaran Pandiyan wrote:
> > > On Thu, 2019-02-14 at 21:22 +0200, Ville Syrjala wrote:
> >
s generating from resuming the rings.
> The simple solution to both is to pull the interrupt reenabling from
> afterwards to around the device reset.
>
> Signed-off-by: Chris Wilson
> Cc: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/i915_reset.c| 6 ++
> drivers/gpu/
On Fri, Feb 15, 2019 at 09:43:37PM +, Pandiyan, Dhinakaran wrote:
> On Fri, 2019-02-15 at 23:34 +0200, Ville Syrjälä wrote:
> > On Fri, Feb 15, 2019 at 01:06:32PM -0800, Dhinakaran Pandiyan wrote:
> > > On Fri, 2019-02-15 at 14:47 +0200, Ville Syrjälä wrote:
> > > &
COLORIMETRY_OPYCC_601] = HDMI_COLORIMETRY_OPYCC_601,
> + [DRM_MODE_COLORIMETRY_OPRGB] = HDMI_COLORIMETRY_OPRGB,
> + [DRM_MODE_COLORIMETRY_BT2020_CYCC] = HDMI_COLORIMETRY_BT2020_CYCC,
> + [DRM_MODE_COLORIMETRY_BT2020_RGB] = HDMI_COLORIMETRY_BT2020_RGB,
> + [DRM_MODE_COLORIMETRY_BT2
; + prop = drm_property_create_enum(dev, DRM_MODE_PROP_ENUM,
> + "Colorspace", dp_colorspaces,
> + ARRAY_SIZE(dp_colorspaces));
> +
ut CSC and not the pipe CSC, there's
> no need to set crtc_state->csc_enable, so let's also not consider the
> output format when setting csc_enable on gen11+ platforms.
>
> Fixes: a91de580541c ("drm/i915/icl: Enable pipe output csc")
> Cc: Uma Shankar
> Cc: M
/bugs.freedesktop.org/show_bug.cgi?id=109315
> [fdo#109350]: https://bugs.freedesktop.org/show_bug.cgi?id=109350
> [fdo#109369]: https://bugs.freedesktop.org/show_bug.cgi?id=109369
> [fdo#109373]: https://bugs.freedesktop.org/show_bug.cgi?id=109373
>
On Tue, Feb 19, 2019 at 12:21:51PM +, Chris Wilson wrote:
> The stack usage exceeded 1024 bytes prompting warnings on conservative
> setups, so move the temporary allocation for HW readback onto the heap.
>
> Signed-off-by: Chris Wilson
> Cc: Ville Syrjälä
Reviewed-by
On Tue, Feb 19, 2019 at 03:09:00PM +, Shankar, Uma wrote:
>
>
> >-Original Message-
> >From: dri-devel [mailto:dri-devel-boun...@lists.freedesktop.org] On Behalf
> >Of Ville
> >Syrjälä
> >Sent: Tuesday, February 19, 2019 1:37 AM
&
(0 << 0)
> #define GAMMA_MODE_MODE_10BIT (1 << 0)
> #define GAMMA_MODE_MODE_12BIT (2 << 0)
> --
> 1.9.1
>
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.
On Thu, Feb 14, 2019 at 06:07:05PM -0800, Dhinakaran Pandiyan wrote:
> On Thu, 2019-02-14 at 21:22 +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > On skl the crc registers were extended to provide plane crcs
> > for up to 7 planes. Add the new crc sources
9) {
> u32 tmp = I915_READ(SKL_BOTTOM_COLOR(crtc->pipe));
> --
> 1.9.1
>
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
onnector)
> {
> struct intel_hdcp *hdcp = &connector->hdcp;
> struct drm_i915_private *dev_priv = connector->base.dev->dev_private;
> --
> 2.20.1
>
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedeskt
When looking at failures I seem to end up patching
the crc checks out most of the time and relying on the tracepoints
to get me the data I need. This knob could save me a step.
So
Reviewed-by: Ville Syrjälä
> -Daniel
>
> > ---
> > lib/igt_core.c| 7 +++
> >
ie. also move the 420_only check into the function itself.
> +
> pipe_config->has_drrs = false;
> if (IS_G4X(dev_priv) || port == PORT_A)
> pipe_config->has_audio = false;
> --
> 2.20.1
>
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
etup_vsc(struct intel_dp
> *intel_dp,
>* 011b = 12bpc.
>* 100b = 16bpc.
>*/
> - vsc_sdp.DB17 = 0x1;
> + switch (crtc_state->pipe_bpp) {
> + case 12: /* 8bpc */
> + vsc_sdp.DB17 = 0x1;
> + break;
> +
On Thu, Feb 21, 2019 at 01:33:51PM -0800, Rodrigo Vivi wrote:
> No functional change. Just a reorg to match the preferred
> behavior.
>
> Cc: Ville Syrjälä
> Cc: Lucas De Marchi
> Signed-off-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/intel_hdmi.c | 12 ++---
On Thu, Feb 21, 2019 at 01:44:30PM -0800, Rodrigo Vivi wrote:
> No functional change. Just a reorg to match the preferred
> behavior.
>
> v2: missing else (Ville)
>
> Cc: Ville Syrjälä
> Cc: Lucas De Marchi
> Signed-off-by: Rodrigo Vivi
Looks correct enough.
Re
On Mon, Feb 25, 2019 at 03:14:52PM +0200, Jani Nikula wrote:
> On Fri, 22 Feb 2019, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Use the newly introduced intel_apply_pci_quirks() to clean up
> > the way we apply the ilk+ watermark quirks.
> >
On Mon, Feb 25, 2019 at 03:28:18PM +0200, Jani Nikula wrote:
> On Mon, 25 Feb 2019, Jani Nikula wrote:
> > On Fri, 22 Feb 2019, Ville Syrjala wrote:
> >> From: Ville Syrjälä
> >>
> >> Add support for multiple independent pci quirk tables.
> >> I wa
On Fri, Feb 22, 2019 at 05:52:51PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> The only machine we know for sure to require the LP3+ disable
> is the Lenovo Thinkpad X220 tablet. Originally in commit
> 03981c6ebec4 ("drm/i915: Disable LP3 watermarks on all SNB
>
On Mon, Feb 25, 2019 at 05:45:38PM +0200, Ville Syrjälä wrote:
> On Fri, Feb 22, 2019 at 05:52:51PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > The only machine we know for sure to require the LP3+ disable
> > is the Lenovo Thinkpad X220 t
undle this time and hoping there's no other
> missing places.
>
> Cc: Ville Syrjälä
> Cc: Chris Wilson
> Cc: Lucas De Marchi
> Signed-off-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/i915_drv.c | 24 -
> drivers/gpu/drm/i915/i915_perf.c | 5
ase
> for CNL_WITH_PORT_F is separate from the generic gen >= 11.
>
> Cc: Ville Syrjälä
> Cc: Jose Souza
> Signed-off-by: Lucas De Marchi
> ---
> drivers/gpu/drm/i915/i915_irq.c | 34 +++--
> 1 file changed, 20 insertions(+), 14 deletions(-)
&g
OL)
> --
> 2.20.0
>
> _______
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
(PP_ON | PP_SEQUENCE_MASK | 0
> | 0)
> #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0
> | 0)
> --
> 2.20.0
>
> ___
> Intel-gfx mailing list
> Intel-
> Signed-off-by: Lucas De Marchi
There's quite a bit more cleanup to be done in this area. As a start
https://patchwork.freedesktop.org/series/56354/ ;)
This patch looks good to me. It'll conflict with my series though, but
no biggie.
Reviewed-by: Ville Syrjälä
> ---
> drivers
rm/i915/intel_dpll_mgr.h
> b/drivers/gpu/drm/i915/intel_dpll_mgr.h
> index b1fdce1be942..12ffe83598aa 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.h
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.h
> @@ -352,6 +352,5 @@ int icl_calc_dp_combo_pll_link(struct drm_i915_private
> *dev_priv,
> u32 pll_id);
> int cnl_hdmi_pll_ref_clock(struct drm_i915_private *dev_priv);
> enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port);
> -bool intel_dpll_is_combophy(enum intel_dpll_id id);
>
> #endif /* _INTEL_DPLL_MGR_H_ */
> --
> 2.20.0
>
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
On Mon, Feb 25, 2019 at 08:35:08PM +, Chris Wilson wrote:
> Quoting Ville Syrjala (2019-02-25 20:29:00)
> > From: Ville Syrjälä
> >
> > The BXT DUNIT register tells us the size of each DRAM device
> > in Gb. We want to report the size of the whole DIMM in GB, so
On Mon, Feb 25, 2019 at 08:57:45PM +, Chris Wilson wrote:
> Quoting Ville Syrjälä (2019-02-25 20:48:10)
> > On Mon, Feb 25, 2019 at 08:35:08PM +, Chris Wilson wrote:
> > > Quoting Ville Syrjala (2019-02-25 20:29:00)
> > > > From: Ville Syrjälä
> > >
On Mon, Feb 25, 2019 at 01:54:16PM -0800, Lucas De Marchi wrote:
> On Mon, Feb 25, 2019 at 09:28:06PM +0200, Ville Syrjälä wrote:
> >On Fri, Feb 22, 2019 at 04:34:48PM -0800, Lucas De Marchi wrote:
> >> No change in behavior. Just removing the unused bits since it makes it
>
On Mon, Feb 25, 2019 at 04:03:05PM -0800, Lucas De Marchi wrote:
> On Mon, Feb 25, 2019 at 10:42:12PM +0200, Ville Syrjälä wrote:
> >On Fri, Feb 22, 2019 at 03:23:22PM -0800, Lucas De Marchi wrote:
> >> Let the MG plls have their own hooks since it shares very little with
&g
On Mon, Feb 25, 2019 at 01:28:23PM -0800, Lucas De Marchi wrote:
> On Mon, Feb 25, 2019 at 10:45:34PM +0200, Ville Syrjälä wrote:
> >On Fri, Feb 22, 2019 at 03:23:24PM -0800, Lucas De Marchi wrote:
> >> Use the first 3 bits of dpll_info.platform_flags to mark the type of the
&
On Tue, Feb 26, 2019 at 11:15:44AM -0800, Lucas De Marchi wrote:
> On Tue, Feb 26, 2019 at 04:21:01PM +0200, Ville Syrjälä wrote:
> >On Mon, Feb 25, 2019 at 04:03:05PM -0800, Lucas De Marchi wrote:
> >> On Mon, Feb 25, 2019 at 10:42:12PM +0200, Ville Syrjälä wrote:
> >>
On Tue, Feb 26, 2019 at 11:02:58AM -0800, Lucas De Marchi wrote:
> On Tue, Feb 26, 2019 at 04:48:23PM +0200, Ville Syrjälä wrote:
> >> >This seems a rather roundabout way of doing things when we already have
> >> >the vfuncs.
> >> >
> >
On Wed, Feb 27, 2019 at 03:23:01PM -0500, Adam Jackson wrote:
> On Wed, 2019-02-27 at 19:14 +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Some monitors apparently forget to mark any mode as preferred in the
> > EDID. In this particular case we hav
ssion. But with this, we can ensure the mask
> is non-zero, power of 2, fits u32, and the value fits the mask (when the
> value is a constant expression).
I might like a debug knob to make that into a runtime check for
non-const expressions. But that can be considered later.
--
.
>
> I'll get used to the hi,lo convention eventually.
The nice thing is that it matches the spec.
The hard part is running out of fingers for wide bitfields :P
--
Ville Syrjälä
Intel
___
Intel-gfx mailing list
Intel-gfx@lists.freedes
On Wed, Feb 27, 2019 at 03:04:07PM -0800, José Roberto de Souza wrote:
> Atomic state needs to be put even if the commit was successful.
>
> Fixes: dba14b27dd3c ("drm/i915: Reinitialize sink scrambling/TMDS clock ratio
> on HPD")
> Cc: Ville Syrjälä
> Cc: Lyude
On Wed, Feb 27, 2019 at 03:04:08PM -0800, José Roberto de Souza wrote:
> drm_atomic_commit() call chain already takes care of adding
> connectors and planes, so lets no add then manually if not changing
> their states.
The specific callgraph would make review easier.
>
> Cc: Vill
/* Mark mode as changed to trigger a pipe->update() */
> crtc_state->mode_changed = true;
> --
> 2.21.0
>
> _______
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http
any code patch that duplicates the
> actual(with color features already enabled) state and only mark
> mode_changed as true.
>
> Cc: Ville Syrjälä
> Cc: Maarten Lankhorst
> Signed-off-by: José Roberto de Souza
Reviewed-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/i
onfig() will take care of all the checks removed
> from here.
>
> Cc: Dhinakaran Pandiyan
> Cc: Ville Syrjälä
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/i915/intel_display.c | 10 +--
> drivers/gpu/drm/i915/intel_drv.h | 3 +-
> dri
>
> v3: Reusing intel_crtc_crc_prepare() and crc_enabled
>
> v2: Changed commit description to describe that PSR2 inhibit CRC
> calculations.
>
> Cc: Dhinakaran Pandiyan
> Cc: Ville Syrjälä
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/i915/intel_pipe_c
On Thu, Feb 28, 2019 at 06:56:48PM +0200, Ville Syrjälä wrote:
> On Wed, Feb 27, 2019 at 05:32:57PM -0800, José Roberto de Souza wrote:
> > Other features like PSR2 also needs to be disabled while getting CRC
> > so lets rename ips_force_disable to crc_enabled, drop all this checks
On Thu, Feb 28, 2019 at 11:26:57PM +, Souza, Jose wrote:
> On Thu, 2019-02-28 at 18:56 +0200, Ville Syrjälä wrote:
> > On Wed, Feb 27, 2019 at 05:32:57PM -0800, José Roberto de Souza
> > wrote:
> > > Other features like PSR2 also needs to be disabled while getting
On Thu, Feb 28, 2019 at 09:27:48PM +, Souza, Jose wrote:
> On Thu, 2019-02-28 at 13:37 +0200, Ville Syrjälä wrote:
> > On Wed, Feb 27, 2019 at 03:04:08PM -0800, José Roberto de Souza
> > wrote:
> > > drm_atomic_commit() call chain already takes care of adding
> &g
> v2: Changed commit description to describe that PSR2 inhibit CRC
> calculations.
>
> Cc: Dhinakaran Pandiyan
> Cc: Ville Syrjälä
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/i915/intel_pipe_crc.c | 1 +
> drivers/gpu/drm/i915/intel_ps
On Mon, Mar 04, 2019 at 04:45:28PM +0200, Imre Deak wrote:
> On Mon, Mar 04, 2019 at 03:12:17PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > The plane used to scan out NV12 luma on ICL is logically
> > off but actually on. Fix the state checker to ac
On Mon, Mar 04, 2019 at 03:52:30PM +, Chris Wilson wrote:
> Quoting Ville Syrjala (2019-03-04 13:41:13)
> > From: Ville Syrjälä
> >
> > Let's just always enable the DVO 2x clock on i830. This way we don't
> > have to track if DVO is being used or not
On Mon, Mar 04, 2019 at 06:17:50PM +0200, Jani Nikula wrote:
> On Mon, 25 Feb 2019, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Life will be easier later if we have the ranks stored
> > as a bare number.
> >
> > Signed-off-by: Ville Syrjälä
>
actually, so setting connectors_changed instead that will cause
> modeset as desired.
>
> Cc: Ville Syrjälä
> Signed-off-by: José Roberto de Souza
Reviewed-by: Ville Syrjälä
The two other questionable places seem to be:
* intel_digital_connector_atomic_check()
Looks like this i
On Mon, Mar 04, 2019 at 06:32:25PM +0200, Jani Nikula wrote:
> On Mon, 25 Feb 2019, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Make the code less repetitive by extracting a few small helpers.
> >
> > Signed-off-by: Ville Syrjälä
> > ---
&g
gt; @@ -7675,6 +7684,7 @@ static void cherryview_init_gt_powersave(struct
> drm_i915_private *dev_priv)
>
> cherryview_setup_pctx(dev_priv);
>
> + vlv_update_czclk(dev_priv);
> vlv_init_gpll_ref_freq(dev_priv);
>
> mutex_lock(&dev_priv->sb_lock)
On Mon, Mar 04, 2019 at 06:57:15PM +0200, Ville Syrjälä wrote:
> On Fri, Mar 01, 2019 at 04:49:31PM -0800, José Roberto de Souza wrote:
> > Moving VLV/CHV/BYT czclk to intel_pm as it is a core clock used as
> > base by several other GPU blocks including GT.
> >
> > BSpe
ience fancy races otherwise.
> - */
> - intel_irq_uninstall(dev_priv);
> -
> /*
>* Due to the hpd irq storm handling the hotplug work can re-arm the
>* poll handlers. Hence disable polling after hpd handling is shut down.
> --
> 2.21.0
>
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
On Fri, Mar 01, 2019 at 05:14:04PM -0800, Lucas De Marchi wrote:
> According to the spec PP_SEQUENCE_STATE_ON_S1_1 is the correct name, so
> just rename it.
>
> Signed-off-by: Lucas De Marchi
Reviewed-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/i915_reg.h | 2 +-
&g
undant. Just nuke the whole thing?
> +
> #define _PP_CONTROL 0x61204
> #define PP_CONTROL(pps_idx) _MMIO_PPS(pps_idx, _PP_CONTROL)
> #define PANEL_UNLOCK_REGS (0xabcd << 16)
> --
> 2.20.1
--
Ville Syrjälä
Intel
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
801 - 900 of 10902 matches
Mail list logo
