[Intel-gfx] [PATCH V3] drm/i915/dg2: add Wa_14014947963

From: Clint Taylor BSPEC: 46123 v2: Address review feedback [MattR] v3: move register definition to gt_regs [MattR] Cc: Matt Roper Signed-off-by: Clint Taylor --- drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 +++ drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 + 2 files changed, 8

[Intel-gfx] [PATCH v2] drm/i915/dg2: add Wa_14014947963

From: Clint Taylor BSPEC: 46123 v2: Address review feedback [MattR] Cc: Matt Roper Signed-off-by: Clint Taylor --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 + drivers/gpu/drm/i915/i915_reg.h | 2 ++ 2 files changed, 7 insertions(+) diff --git

[Intel-gfx] [PATCH] drm/i915/dg2: add Wa_14015023722

From: Clint Taylor BSPEC: 46123 Cc: Matt Roper Signed-off-by: Clint Taylor --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 + drivers/gpu/drm/i915/i915_reg.h | 4 2 files changed, 9 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c

[Intel-gfx] [PATCH] drm/i915/snps: vswing value refined for SNPS phys

From: Clint Taylor Updated new values from BSPEC. BSPEC: 53920 Cc: Jani Nikula Cc: José Roberto de Souza Cc: Imre Deak Signed-off-by: Clint Taylor --- .../drm/i915/display/intel_ddi_buf_trans.c| 42 +-- 1 file changed, 21 insertions(+), 21 deletions(-) diff --git

[Intel-gfx] [PATCH v2] drm/i915/adlp: Remove require_force_probe protection

From: Clint Taylor Remove force probe protection from ADL_P platform. Did not obsevre warnings, errors, flickering or any visual defects while doing ordinary tasks like browsing and editing documents in a two monitor setup. For more info drm-tip idle run results :

[Intel-gfx] [PATCH] drm/i915/adlp: Remove require_force_probe protection

From: Clint Taylor drm/i915/adlp: Remove require_force_probe protection Removing force probe protection from ADL_P platform. Did not observe warnings, errors, flickering or any visual defects while doing ordinary tasks like browsing and editing documents in a two monitor

[Intel-gfx] [PATCH v2] drm/i915/adl_p: Add initial ADL_P Workarounds

From: Clint Taylor Most of the context WA are already implemented. Adding adl_p platform tag to reflect so. v2: adjust comments for clarity (MattR) BSpec: 54369 Cc: Matt Roper Cc: Aditya Swarup Reviewed-by: Matt Roper Signed-off-by: Radhakrishna Sripada Signed-off-by: Anusha Srivatsa

[Intel-gfx] [PATCH] drm/i915/adl_p: Add initial ADL_P Workarounds

From: Clint Taylor Most of the context WA are already implemented. Adding adl_p platform tag to reflect so. BSpec: 54369 Cc: Matt Roper Cc: Aditya Swarup Signed-off-by: Radhakrishna Sripada Signed-off-by: Anusha Srivatsa Signed-off-by: Madhumitha Tolakanahalli Pradeep Signed-off-by: José

[Intel-gfx] [PATCH] drm/i915/display: support ddr5 mem types

From: Clint Taylor Add DDR5 and LPDDR5 return values from punit fw. BSPEC: 54023 Cc: Matt Roper Cc: José Roberto de Souza Signed-off-by: Clint Taylor --- drivers/gpu/drm/i915/display/intel_bw.c | 12 +++- drivers/gpu/drm/i915/i915_drv.h | 4 +++-

[Intel-gfx] [PATCH v4] drm/i915/gt: Implement WA_1406941453

From: Clint Taylor Enable HW Default flip for small PL. bspec: 52890 bspec: 53508 bspec: 53273 v2: rebase to drm-tip v3: move from ctx to gt workarounds. Remove whitelist. v4: move to rcs WA init Cc: Matt Atwood Cc: Matt Roper Cc: José Roberto de Souza Signed-off-by: Clint Taylor ---

[Intel-gfx] [PATCH v3] drm/i915/gt: Implement WA_1406941453

From: Clint Taylor Enable HW Default flip for small PL. bspec: 52890 bspec: 53508 bspec: 53273 v2: rebase to drm-tip v3: move from ctx to gt workarounds. Remove whitelist. Cc: Matt Atwood Cc: Matt Roper Cc: José Roberto de Souza Signed-off-by: Clint Taylor ---

[Intel-gfx] [PATCH v2] drm/i915/gt: Implement WA_1406941453

From: Clint Taylor Enable HW Default flip for small PL. bspec: 52890 bspec: 53508 bspec: 53273 v2: rebase to drm-tip Reviewed-by: Matt Atwood Signed-off-by: Clint Taylor --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++ drivers/gpu/drm/i915/i915_reg.h | 1 + 2 files

[Intel-gfx] [PATCH] drm/i915/gt: Implement WA_1406941453

From: Clint Taylor Enable HW Default flip for small PL. bspec: 52890 bspec: 53508 bspec: 53273 Signed-off-by: Clint Taylor --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++ drivers/gpu/drm/i915/i915_reg.h | 1 + 2 files changed, 7 insertions(+) diff --git

[Intel-gfx] [PATCH v2] drm/i915/tgl: Implement WA_16011163337

From: Clint Taylor Set GS Timer to 224. Combine with Wa_1604555607 due to register FF_MODE2 not being able to be read. V2: Math issue fixed Cc: Chris Wilson Cc: Caz Yokoyama Cc: Matt Atwood Signed-off-by: Clint Taylor --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 8

[Intel-gfx] [PATCH] drm/i915/tgl: Implement WA_16011163337

From: Clint Taylor Set GS Timer to 224. Combine with Wa_1604555607 due to register FF_MODE2 not being able to be read. Cc: Caz Yokoyama Cc: Matt Atwood Signed-off-by: Clint Taylor --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 8 drivers/gpu/drm/i915/i915_reg.h | 2

[Intel-gfx] [PATCH v3] drm/i915: Disable display interrupts during display IRQ handler

From: Clint Taylor During the Display Interrupt Service routine the Display Interrupt Enable bit must be disabled, The interrupts handled, then the Display Interrupt Enable bit must be set to prevent possible missed interrupts. Bspec: 49212 V2: Change Title to remove SDE reference. V3: Fix TAB

[Intel-gfx] [PATCH] drm/i915: Disable display interrupts during display IRQ handler

From: Clint Taylor During the Display Interrupt Service routine the Display Interrupt Enable bit must be disabled, The interrupts handled, then the Display Interrupt Enable bit must be set to prevent possible missed interrupts. Bspec: 49212 Cc: Lucas De Marchi Cc: Aditya Swarup Reviewed-by:

[Intel-gfx] [PATCH] drm/i915: Disable display interrupts during SDE IRQ handler

From: Clint Taylor During the Display Interrupt Service routine the Display Interrupt Enable bit must be disabled, The interrupts handled, then the Display Interrupt Enable bit must be set to prevent possible missed interrupts. Bspec: 49212 Cc: Lucas De Marchi Cc: Aditya Swarup Signed-off-by:

[Intel-gfx] [PATCH] drm/i915/ehl: Add port_cl_dw10 to combo phy vswing sequence

From: Clint Taylor Elkhart Lake has additional bits in port_cl_dw10 that should be set during vswing programming. According to BSPEC these bits should be set based on OEM selection. Since VBT does not contain a definition for these bits we will currently clear them until VBT is updated to give

[Intel-gfx] [PATCH] drm/i915/icl: Prevent possibe de-reference in skl_check_pipe_max_pixel_clock.

From: Clint Taylor Add protections to prevent NULL de-reference for a couple variables used in skl_check_pipe_max_pixel_clock to prevent GP exception from occurring during some IGT tests. References: https://bugs.freedesktop.org/show_bug.cgi?id=109084 Cc: Rodrigo Vivi Cc: Martin Peres

[Intel-gfx] [PATCH v5] drm/i915/icl: combo port vswing programming changes per BSPEC

From: Clint Taylor In August 2018 the BSPEC changed the ICL port programming sequence to closely resemble earlier gen programming sequence. Restrict combo phy to HBR max rate unless eDP panel is connected to port. v2: remove debug code that Imre found v3: simplify translation table if-else v4:

[Intel-gfx] [PATCH] drm/i915/dsi: Add PORT_TX_DW7 programming to DSI vswing sequence

From: Clint Taylor Program PORT_TX_DW7 to the value specified in the DDI Buffer section of the BSPEC. BSEPC: 21257 Cc: Madhav Chauhan Cc: Jani Nikula Cc: Imre Deak Signed-off-by: Clint Taylor --- drivers/gpu/drm/i915/icl_dsi.c | 10 ++ 1 file changed, 10 insertions(+) diff --git

[Intel-gfx] [PATCH v4] drm/i915/icl: combo port vswing programming changes per BSPEC

From: Clint Taylor In August 2018 the BSPEC changed the ICL port programming sequence to closely resemble earlier gen programming sequence. Restrict combo phy to HBR max rate unless eDP panel is connected to port. v2: remove debug code that Imre found v3: simplify translation table if-else v4:

[Intel-gfx] [PATCH v3] /drm/i915/hdmi: SCDC Scrambling enable without CTS mode

From: Clint Taylor Setting the SCDC scrambling CTS mode causes HDMI Link Layer protocol tests HF1-12 and HF1-13 to fail. V2: Removed "Source Shall" entries to a new patch V3: Rebase to drm-tip Cc: Ville Syrjälä Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107895 Bugzilla:

[Intel-gfx] [PATCH v3] drm/i915/icl: combo port vswing programming changes per BSPEC

From: Clint Taylor In August 2018 the BSPEC changed the ICL port programming sequence to closely resemble earlier gen programming sequence. v2: remove debug code that Imre found v3: simplify translation table if-else BSpec: 21257 Cc: Ville Syrjälä Cc: Imre Deak Cc: Rodrigo Vivi

[Intel-gfx] [PATCH v2] drm/i915/icl: combo port vswing programming changes per BSPEC

From: Clint Taylor In August 2018 the BSPEC changed the ICL port programming sequence to closely resemble earlier gen programming sequence. v2: remove debug code that Imre found BSpec: 21257 Cc: Ville Syrjälä Cc: Imre Deak Cc: Rodrigo Vivi Signed-off-by: Clint Taylor ---

[Intel-gfx] [PATCH] drm/i915/icl: combo port vswing programming changes per BSPEC

From: Clint Taylor In August 2018 the BSPEC changed the ICL port programming sequence to closely resemble earlier gen programming sequence. BSpec: 21257 Cc: Ville Syrjälä Cc: Imre Deak Cc: Rodrigo Vivi Signed-off-by: Clint Taylor --- drivers/gpu/drm/i915/i915_reg.h | 4 +

[Intel-gfx] [PATCH] drm/i915/glk: Use cached RCOMP value when re-enabling DPIO Phy

From: Clint Taylor The calibration RCOMP value in PORT_TX_DW6 in stored in dev_priv during driver init. Use this value instead of reading the register again as the power well for PORTA RCOMP register may not be enabled and will return 0x instead of the computed value. Cc: Ville Syrjälä

[Intel-gfx] [PATCH v3] drm/i915/hdmi: Reorder structure to match specification

From: Clint Taylor reorder structure of 297, 594 N values to group Audio Sample Frequencies together to make updating from HDMI specification easier. V2: Match patch 1/2 version V3: Arrange by sample freq, then pixel clock. Cc: Jani Nikula Signed-off-by: Clint Taylor ---

[Intel-gfx] [PATCH v2 2/2] drm/i915/hdmi: Reorder structure to match specification

From: Clint Taylor reorder structure of 297, 594 N values to group Audio Sample Frequencies together to make updating from HDMI specification easier. V2: Match patch 1/2 version Cc: Jani Nikula Cc: sta...@vger.kernel.org Signed-off-by: Clint Taylor --- drivers/gpu/drm/i915/intel_audio.c |

[Intel-gfx] [PATCH 0/2] HDMI 2.0 clock recovery values

From: Clint Taylor Added HDMI 2.0 N and CTS values for 594 Pixel clock modes. Reorganized structure to group by Audio Sample Frequency Clint Taylor (2): drm/i915/hdmi: Add HDMI 2.0 audio clock recovery N values drm/i915/hdmi: Reorder structure to match specification

[Intel-gfx] [PATCH v2 1/2] drm/i915/hdmi: Add HDMI 2.0 audio clock recovery N values

From: Clint Taylor HDMI 2.0 594Mhz modes were incorrectly selecting 25.200Mhz Automatic N value mode instead of HDMI specification values. V2: Fix 88.2 Hz N value Cc: Jani Nikula Cc: sta...@vger.kernel.org Signed-off-by: Clint Taylor --- drivers/gpu/drm/i915/intel_audio.c | 17

[Intel-gfx] [PATCH v2] drm/i915/hdmi: Detect HDMI 2.0 monitors using multiple EDID capabilities

From: Clint Taylor HDMI 2.0 monitors may not support SCDC and still be able to accept VICs above 63. Use multiple EDID capbilities to determine if the SINK is actually an HDMI 2.0 device. The QD980B HDMI 2.0 Analyzer generates unique EDIDs during CTS tests that don't contain a HDMI Forum VSDB if

[Intel-gfx] [PATCH] drm/i915/hdmi: Detect HDMI 2.0 monitors using multiple EDID capabilities

From: Clint Taylor HDMI 2.0 monitors may not support SCDC and still be able to accept VICs above 63. Use multiple EDID capbilities to determine if the SINK is actually an HDMI 2.0 device. The QD980B HDMI 2.0 Analyzer generates unique EDIDs during CTS tests that don't contain a HDMI Forum VSDB if

[Intel-gfx] [PATCH] drm/i915/hdmi: Initialize SCDC registers according to spec

From: Clint Taylor Initialize SCDC Source Version and TDMS_Config_0 registers to nominal values during intel_hdmi_detect(). The i915 driver currently doesn't implement features that require polling of the status update bits. Once FRL, DSC, or Source Test is enabled in the driver the status flags

[Intel-gfx] [PATCH v2] /drm/i915/hdmi: SCDC Scrambling enable without CTS mode

From: Clint Taylor Setting the SCDC scrambling CTS mode causes HDMI Link Layer protocol tests HF1-12 and HF1-13 to fail. V2: Removed "Source Shall" entries to a new patch Cc: Ville Syrjälä Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107895 Bugzilla:

[Intel-gfx] [PATCH] drm/i915/hdmi: Add HDMI 2.0 audio clock recovery N values

From: Clint Taylor HDMI 2.0 594Mhz modes were incorrectly selecting 25.200Mhz Automatic N value mode instead of HDMI specification values. Signed-off-by: Clint Taylor --- drivers/gpu/drm/i915/intel_audio.c | 16 1 file changed, 16 insertions(+) diff --git

[Intel-gfx] [PATCH] /drm/i915/hdmi: SCDC Scrambling enable without CTS mode

From: Clint Taylor Setting the SCDC scrambling CTS mode causes HDMI Link Layer protocol tests HF1-12 and HF1-13 to fail. Added "Source Shall" entries from SCDC section before enabling scrambling. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107895 Bugzilla:

[Intel-gfx] [PATCH v4] drm/i915/glk: Add Quirk for GLK NUC HDMI port issues.

From: Clint Taylor On GLK NUC platforms the HDMI retiming buffer needs additional disabled time to correctly sync to a faster incoming signal. When measured on a scope the highspeed lines of the HDMI clock turn off for ~400uS during a normal resolution change. The HDMI retimer on the GLK NUC

[Intel-gfx] [PATCH v3] drm/i915/glk: Add Quirk for GLK NUC HDMI port issues.

From: Clint Taylor On GLK NUC platforms the HDMI retiming buffer needs additional disabled time to correctly sync to a faster incoming signal. When measured on a scope the highspeed lines of the HDMI clock turn off for ~400uS during a normal resolution change. The HDMI retimer on the GLK NUC

[Intel-gfx] [PATCH V2] drm/i915/glk: Add Quirk for GLK NUC HDMI port issues.

From: Clint Taylor On GLK NUC platforms the HDMI retiming buffer needs additional disabled time to correctly sync to a faster incoming signal. When measured on a scope the highspeed lines of the HDMI clock turn off for ~400uS during a normal resolution change. The HDMI retimer on the GLK NUC

[Intel-gfx] [PATCH] drm/i915/glk: Add Quirk for GLK NUC HDMI port issues.

From: Clint Taylor On GLK NUC platforms the HDMI retiming buffer needs additional disabled time to correctly sync to a faster incoming signal. When measured on a scope the highspeed lines of the HDMI clock turn off for ~400uS during a normal resolution change. The HDMI retimer on the GLK NUC

[Intel-gfx] [PATCH V3] drn/i915/edp: Only use alternate fixed mode when requested

From: Clint Taylor In commit dc911f5bd8aa ("drm/i915/edp: Allow alternate fixed mode for eDP if available."), the patch was always selecting the alternate refresh rate even though user space was asking for the higher rate. This patch confirms the alt mode setup time

[Intel-gfx] [PATCH] drm/i915/edp: Only use alternate fixed mode when requested

From: Clint Taylor In commit dc911f5bd8aa ("drm/i915/edp: Allow alternate fixed mode for eDP if available."), the patch was always selecting the alternate refresh rate even though user space was asking for the higher rate. This patch adds a check for vrefresh rate as

[Intel-gfx] [PATCH] drm/i915/edp: Only use alternate fixed mode when requested

From: Clint Taylor In commit dc911f5bd8aa ("drm/i915/edp: Allow alternate fixed mode for eDP if available."), the patch was always selecting the alternate refresh rate even though user space was asking for the higher rate. This patch adds a check for vrefresh rate as

[Intel-gfx] [PATCH] drm/i915: Register definitions for DP Phy compiance

From: Clint Taylor DisplayPort Phy compliance test patterns register definitions. Signed-off-by: Clint Taylor --- drivers/gpu/drm/i915/i915_reg.h | 18 ++ 1 file changed, 18 insertions(+) diff --git

[Intel-gfx] [PATCH v4 i-g-t] tests/kms: increase max threshold time for edid read

From: Clint Taylor Current 50ms max threshold timing for an EDID read is very close to the actual time for a 2 block HDMI EDID read. Adjust the timings base on connector type as DP reads are at 1 MBit and HDMI at 100K bit. If an LSPcon is connected to device under

[Intel-gfx] [PATCH v3 i-g-t] tests/kms: increase max threshold time for edid read

From: Clint Taylor Current 50ms max threshold timing for an EDID read is very close to the actual time for a 2 block HDMI EDID read. Adjust the timings base on connector type as DP reads are at 1 MBit and HDMI at 100K bit. If an LSPcon is connected to device under

[Intel-gfx] [PATCH v2 i-g-t] tests/kms: increase max threshold time for edid read

From: Clint Taylor Current 50ms max threshold timing for an EDID read is very close to the actual time for a 2 block HDMI EDID read. Adjust the timings base on connector type as DP reads are at 1 MBit and HDMI at 100K bit. If an LSPcon is connected to device under

[Intel-gfx] [PATCH i-g-t] tests/kms: increase max threshold time for edid read

From: Clint Taylor Current 50ms max threshold timing for an EDID read is very close to the actual time for a 2 block HDMI EDID read of 48ms. Any delay like a clock stretch by the EDID eeprom will cause this test to fail. A 4 block HDMI EDID read takes approximately

[Intel-gfx] [PATCH] drm/i915/cnl: DDIA Lane capability bit not set in clone mode

From: Clint Taylor DDIA Lane capability control 4 lane bit is not being set by firmware during clone mode boot. This occurs when multiple monitors are connected during boot. The driver will configure the port for 2 lane maximum width if this bit is not set. Once

[Intel-gfx] [PATCH] drm/i915/glk: RGB565 planes now allow 90/270 rotation

From: Clint Taylor RGB565 Pixel format planes can now be rotated at 90 and 270 degrees Signed-off-by: Clint Taylor --- drivers/gpu/drm/i915/intel_atomic_plane.c | 11 --- 1 file changed, 4 insertions(+), 7 deletions(-) diff

[Intel-gfx] [PATCH] drm/i915: Detect USB-C specific dongles before reducing M and N

From: Clint Taylor The Analogix 7737 DP to HDMI converter requires reduced N and M values when to operate correctly at HBR2. Detect this IC by its OUI value of 0x0022B9. Cc: Jani Nikula Cc: Dhinakaran Pandiyan

[Intel-gfx] [PATCH v8 1/3] drm_fourcc: Add new P010, P016 video format

From: Clint Taylor P010 is a planar 4:2:0 YUV with interleaved UV plane, 10 bits per channel video format. P012 is a planar 4:2:0 YUV 12 bits per channel P016 is a planar 4:2:0 YUV with interleaved UV plane, 16 bits per channel video format. V3: Added P012 and

[Intel-gfx] [PATCH v2] drm/i915: Reduce Data Link N value for 1 lane DP->hdmi converters

From: Clint Taylor Several major vendor USB-C->HDMI converters fail to recover a 5.4 GHz 1 lane signal if the Data Link N is greater than 0x8. Patch detects when 1 lane 5.4 GHz signal is being used and makes the maximum value 20 bit instead of the maximum

[Intel-gfx] [PATCH] drm/i915: Reduce Data Link N value for 1 lane DP->hdmi converters

From: Clint Taylor Several major vendor USB-C->HDMI converters fail to recover a 5.4 GHz 1 lane signal if the Data Link N is greater than 0x8. Patch detects when 1 lane 5.4 GHz signal is being used and makes the maximum value 20 bit instead of the maximum

[Intel-gfx] [PATCH v2] drm/i915: prevent crash with .disable_display parameter

From: Clint Taylor The .disable_display parameter was causing a fatal crash when fbdev was dereferenced during driver init. V1: protection in i915_drv.c V2: Moved protection to intel_fbdev.c Cc: Chris Wilson Signed-off-by: Clint Taylor

[Intel-gfx] [PATCH] drm/i915: prevent crash with .disable_display parameter

From: Clint Taylor The .disable_display parameter was causing a fatal crash when fbdev was dereferenced during driver init. Signed-off-by: Clint Taylor --- drivers/gpu/drm/i915/i915_drv.c |4 +++- 1 file changed, 3 insertions(+), 1

[Intel-gfx] [PATCH i-g-t] tools/intel_reg: enable quiet option for mmio

From: Clint Taylor Skip decode options and formatting when the quiet option is used during mmio reads. Makes intel_reg usable by scripts to return MMIO values. Signed-off-by: Clint Taylor --- tools/intel_reg.c | 7 ++- 1 file

[Intel-gfx] [PATCH v2] drm/i915/bxt: Enable PSR platform support for BXT

From: Clint Taylor Add IS_BROXTON() to the HAS_PSR() MACRO. Tested with a Sharp 2560x1440 panel that claims PSR is enable and in progress. v2:rebase to latest nightly CC: Imre Deak Signed-off-by: Clint Taylor ---

[Intel-gfx] [PATCH] drm/i915/bxt: Enable PSR platform support for BXT

From: Clint Taylor Add IS_BROXTON() to the HAS_PSR() MACRO. Tested with a Sharp 2560x1440 panel that claims PSR is enable and in progress. Signed-off-by: Clint Taylor --- drivers/gpu/drm/i915/i915_drv.h |3 ++- 1 file changed, 2

[Intel-gfx] [PATCH V11] drm/i915/skl: SKL CDCLK change on modeset tracking VCO

From: Clint Taylor WARNING: Using ChromeOS with an eDP panel and a 4K@60 DP monitor connected to DDI1 the system will hard hang during a cold boot. Occurs when DDI1 is enabled when the cdclk is less then required. DP connected to DDI2 and HPD on either port works

[Intel-gfx] [PATCH V10] drm/i915/skl: SKL CDCLK change on modeset tracking VCO

From: Clint Taylor WARNING: Using ChromeOS with an eDP panel and a 4K@60 DP monitor connected to DDI1 the system will hard hang during a cold boot. Occurs when DDI1 is enabled when the cdclk is less then required. DP connected to DDI2 and HPD on either port works

[Intel-gfx] [PATCH V9] drm/i915/skl: SKL CDCLK change on modeset tracking VCO

From: Clint Taylor WARNING: Using ChromeOS with an eDP panel and a 4K@60 DP monitor connected to DDI1 the system will hard hang during a cold boot. Occurs when DDI1 is enabled when the cdclk is less then required. DP connected to DDI2 and HPD on either port works

[Intel-gfx] [PATCH V8] drm/i915/skl: SKL CDCLK change on modeset tracking VCO

From: Clint Taylor WARNING: Using ChromeOS with an eDP panel and a 4K@60 DP monitor connected to DDI1 the system will hard hang during a cold boot. Occurs when DDI1 is enabled when the cdclk is less then required. DP connected to DDI2 and HPD on either port works

[Intel-gfx] [PATCH V7] drm/i915/skl: SKL CDCLK change on modeset tracking VCO

From: Clint Taylor Set cdclk based on the max required pixel clock based on VCO selected. Track boot vco instead of boot cdclk. The vco is now tracked at the atomic level and all CRTCs updated if the required vco is changed. Not tested with eDP v1.4 panels that

[Intel-gfx] [PATCH V6] drm/i915/skl: SKL CDCLK change on modeset tracking VCO

From: Clint Taylor Set cdclk based on the max required pixel clock based on VCO selected. Track boot vco instead of boot cdclk. The vco is now tracked at the atomic level and all CRTCs updated if the required vco is changed. Not tested with eDP v1.4 panels that

[Intel-gfx] [PATCH V5] drm/i915/skl: SKL CDCLK change on modeset tracking VCO

From: Clint Taylor Set cdclk based on the max required pixel clock based on VCO selected. Track boot vco instead of boot cdclk. The vco is now tracked at the atomic level and all CRTCs updated if the required vco is changed. Not tested with eDP v1.4 panels that

[Intel-gfx] [PATCH V4] drm/i915/skl: SKL CDCLK change on modeset tracking VCO

From: Clint Taylor Track VCO frequency of SKL instead of the boot CDCLK and allow modeset to set cdclk based on the max required pixel clock based on VCO selected. The vco should be tracked at the atomic level and all CRTCs updated if the required vco is changed. At

[Intel-gfx] [PATCH V3] drm/i915/skl: SKL CDCLK change on modeset tracking VCO

From: Clint Taylor Track VCO frequency of SKL instead of the boot CDCLK and allow modeset to set cdclk based on the max required pixel clock based on VCO selected. The vco should be tracked at the atomic level and all CRTCs updated if the required vco is changed. At

[Intel-gfx] [PATCH] drm/i915: reboot notifier delay for eDP panels

From: Clint Taylor Add reboot notifier for all platforms. This guarantees T12 delay compliance during reboot cycles when pre-os enables the panel within 500ms. Signed-off-by: Clint Taylor --- drivers/gpu/drm/i915/intel_dp.c | 11

[Intel-gfx] [PATCH] drm/i915/skl: SKL CDCLK change on modeset tracking VCO

From: Clint Taylor Track VCO frequency of SKL instead of the boot CDCLK and allow modeset to set cdclk based on the max required pixel clock based on VCO selected. Signed-off-by: Clint Taylor --- drivers/gpu/drm/i915/i915_drv.h |

[Intel-gfx] [PATCH] drm/i915/skl: CDCLK change during modeset based on VCO in use.

From: Clint Taylor Add SKL and KBL cdclk changes during modeset. Taking into account new linkrates available using 8640 VCO. Signed-off-by: Clint Taylor --- drivers/gpu/drm/i915/intel_display.c | 68 ++

[Intel-gfx] [PATCH] drm/i915: 4K audio N value incorrect at 29.97 and 23.98 refresh rate

From: Clint Taylor The TMDS_296M define was computing as 296704 but the mode->clock is 296700 as defined by EDID. Adjusted define to allow correct detection of the need to program the correct N value for 29.97 and 23.98 refresh rate. Signed-off-by: Clint Taylor

[Intel-gfx] [PATCH] drm/i915: Allow minimum brightness upon backlight enable

From: Clint Taylor backlight minimum is a valid value so you don't need to set maximum. Signed-off-by: Clint Taylor --- drivers/gpu/drm/i915/intel_panel.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git

[Intel-gfx] [PATCH] drm/i915: eDP HPD connected check to reduce T3 time

From: Clint Taylor To reduce eDP T3 time check for digital port connected instead of msleep. Maintain VBT time if HPD is not asserted on the port. Current eDP T3 time is an msleep for the panel_power_up time specified in VBT. The eDP specification allows maximum T3

[Intel-gfx] [PATCH] drm/i915/chv: Remove DPIO force latency causing interpair skew issue

From: Clint Taylor clinton.a.tay...@intel.com Latest version of the CHV DPIO programming notes no longer requires writes to TX DW 11 to fix a +2UI interpair skew issue. The current code from April 2014 was actually causing additional skew issues between all TMDS pairs. Signed-off-by: Clint

[Intel-gfx] [PATCH v2] drm/i915/chv: Remove DPIO force latency causing interpair skew issue

From: Clint Taylor clinton.a.tay...@intel.com Latest version of the CHV DPIO programming notes no longer requires writes to TX DW 11 to fix a +2UI interpair skew issue. The current code from April 2014 was actually causing additional skew issues between all TMDS pairs. ver2: added same treatment

[Intel-gfx] [PATCH] drm/i915/chv: Enable HDMI Clock recovery for Pipe C

From: Clint Taylor clinton.a.tay...@intel.com Added PIPE C register support for CHV audio programming. Signed-off-by: Clint Taylor clinton.a.tay...@intel.com --- drivers/gpu/drm/i915/i915_reg.h | 18 -- 1 file changed, 12 insertions(+), 6 deletions(-) diff --git

[Intel-gfx] [PATCH] drm/i915/chv: Enable AVI, SPD and HDMI infoframes for CHV.

From: Clint Taylor clinton.a.tay...@intel.com CHV infoframes were not being enabled. Signed-off-by: Clint Taylor clinton.a.tay...@intel.com --- drivers/gpu/drm/i915/intel_hdmi.c |7 +++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_hdmi.c

[Intel-gfx] [PATCH v4] drm/i915: Enable pixel replicated modes on BDW and HSW.

From: Clint Taylor clinton.a.tay...@intel.com Haswell and later silicon has added a new pixel replication register to the pipe timings for each transcoder. Now in addition to the DPLL_A_MD register for the pixel clock double, we also need to write to the TRANS_MULT_n (0x6002c) register to double

[Intel-gfx] [PATCH] drm/edid: Add missing interlaced flag to 576i@100 modes.

From: Clint Taylor clinton.a.tay...@intel.com CEA VICs 44 and 45 were missing DRM_MODE_FLAG_INTERLACE. Signed-off-by: Clint Taylor clinton.a.tay...@intel.com --- drivers/gpu/drm/drm_edid.c |4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/drm_edid.c

[Intel-gfx] [PATCH v2] drm/i915: Audio N value computed for pixel doubled modes

From: Clint Taylor clinton.a.tay...@intel.com HDMI audio clock config was incorrectly choosing the default for pixel doubled interlaced modes. The table was missing pixel clock values 13.500 (27.000) and 13.513 (27.027). Luckily the default N value for 25.200 is the same N value for both 27MHz

[Intel-gfx] [PATCH v3] drm/i915: Enable pixel replicated modes on BDW and HSW.

From: Clint Taylor clinton.a.tay...@intel.com Haswell and later silicon has added a new pixel replication register to the pipe timings for each transcoder. Now in addition to the DPLL_A_MD register for the pixel clock double, we also need to write to the TRANS_MULT_n (0x6002c) register to double

[Intel-gfx] [PATCH] drm/i915: Audio N value computed for pixel doubled modes

From: Clint Taylor clinton.a.tay...@intel.com HDMI audio clock config was incorrectly choosing the default for pixel doubled interlaced modes. The table was missing pixel clock values 13.500 (27.000) and 13.513 (27.027). Luckily the default N value for 25.200 is the same N value for both 27MHz

[Intel-gfx] [PATCH] drm/i915/hdmi: Compute port_clock for 27.027 pixel replicated modes

From: Clint Taylor clinton.a.tay...@intel.com port_clock was being incorrectly computed and WRPLL was incorrectly programmed for pixel doubled modes using a 27.027MHz pixel clock. port_clock was set to 27.026 resulting in an output pixel clock matching 27.000MHz. Since there is no way to

[Intel-gfx] [PATCH v2] drm/i915: Enable pixel replicated modes on BDW and HSW.

From: Clint Taylor clinton.a.tay...@intel.com Haswell and later silicon has added a new pixel replication register to the pipe timings for each transcoder. Now in addition to the DPLL_A_MD register for the pixel clock double, we also need to write to the TRANS_MULT_n (0x6002c) register to double

[Intel-gfx] [PATCH] drm/i915: Enable pixel replicated modes on BDW and HSW.

From: Clint Taylor clinton.a.tay...@intel.com Haswell and later silicon has added a new pixel replication register to the pipe timings for each transcoder. Now in addition to the DPLL_A_MD register for the pixel clock double, we also need to write to the TRANS_MULT_n (0x6002c) register to double

[Intel-gfx] [PATCH 2/2] drm/i915/hdmi: Enable pipe pixel replication for SD interlaced modes

From: Clint Taylor clinton.a.tay...@intel.com Enable 2x pixel replication for modes the mode flag DBLCLK to double horizontal timings and pixel clock across TMDS. Signed-off-by: Clint Taylor clinton.a.tay...@intel.com Cc: Daniel Vetter daniel.vet...@ffwll.ch Cc: Ville Syrjälä

[Intel-gfx] [PATCH 0/2] drm/edid: Reduce horizontal timings for pixel

From: Clint Taylor clinton.a.tay...@intel.com Split original drm_edid.c changes and intel_hdmi.c HDMI pixel replciation changes into separate patches. Clint Taylor (2): drm/edid: Reduce horizontal timings for pixel replicated modes drm/i915/hdmi: Enable pipe pixel replication for SD

[Intel-gfx] [PATCH 1/2] drm/edid: Reduce horizontal timings for pixel replicated modes

From: Clint Taylor clinton.a.tay...@intel.com Pixel replicated modes should be non-2x horizontal timings and pixel replicated by the HW across the HDMI cable at 2X pixel clock. Current horizontal resolution of 1440 does not allow pixel duplication to occur and scaling artifacts occur on the TV.

[Intel-gfx] [PATCH] drm/edid: Reduce horizontal timings for pixel replicated modes

From: Clint Taylor clinton.a.tay...@intel.com Pixel replicated modes should be 720 horizontal pixel and pixel replicated by the HW across the HDMI cable at 2X pixel clock. Current horizontal resolution of 1440 does not allow pixel duplication to occur and scaling artifacts occur on the TV. HDMI

[Intel-gfx] [PATCH] drm/i915/dp: Backlight PWM enable before BL Enable assert

From: Clint Taylor clinton.a.tay...@intel.com Backlight on delay uses PWM enable time to seperate PWM to backlight enable assert. Previous time difference used timing from VDD enable which occur several seconds before resulting in PWM starting 5ms after backlight enable. Changes to backlight

[Intel-gfx] [PATCH] drm/edid: Reduce horizontal timings for pixel replicated modes

From: Clint Taylor clinton.a.tay...@intel.com Pixel replicated modes should be 720 horizontal pixel and pixel replicated by the HW across the HDMI cable at 2X pixel clock. Current horizontal resolution of 1440 does not allow pixel duplication to occur and scaling artifacts occur on the TV. HDMI

[Intel-gfx] [PATCH] drm/edid: Reduce horizontal timings for pixel replicated modes

From: Clint Taylor clinton.a.tay...@intel.com Pixel replicated modes should be 720 horizontal pixel and pixel replicated by the HW across the HDMI cable at 2X pixel clock. Current horizontal resolution of 1440 does not allow pixel duplication to occur and scaling artifacts occur on the TV. HDMI

[Intel-gfx] [PATCH] drm/i915/dp: Backlight PWM enable before BL Enable assert

From: Clint Taylor clinton.a.tay...@intel.com Backlight on delay uses PWM enable time to seperate PWM to backlight enable assert. Previous time difference used timing from VDD enable which occur several seconds before resulting in PWM starting 5ms after backlight enable. Changes to backlight

[Intel-gfx] [PATCH] drm/i915: remove pixel doubled HDMI modes from valid modes list

From: Clint Taylor clinton.a.tay...@intel.com Intel HDMI does not correctly configure pixel replicated HDMI modes 480i and 576i. Remove support for these modes until DRM has been changed to correctly identify SD interlaced modes by reporting there true horizontal resolution 720 instead of the

[Intel-gfx] [PATCH] drm: HDMI pixel replication modes now hactive of 720 for pixel replication

From: Clint Taylor clinton.a.tay...@intel.com CEA SD interlaced modes use a horizontal 720 pixels that are pixel replicated to 1440. The current driver reports 1440 pixel to the OS and does not set pixel replicated modes. Signed-off-by: Clint Taylor clinton.a.tay...@intel.com ---

[Intel-gfx] [PATCH 01/11] CHROMIUM: drm/i915: add backlight assertion funcs for PWM status

From: Jesse Barnes jbar...@virtuousgeek.org Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org Signed-off-by: Wayne Boyer wayne.bo...@intel.com Change-Id: I0838b7c84f1913e1026ad98b8b2e79eb133d17e3 Reviewed-on: https://chromium-review.googlesource.com/192468 Reviewed-by: Stéphane Marchesin

[Intel-gfx] [PATCH 00/11] drm/i915: backlight scaling and timing changes from chromium.

From: Clint Taylor clinton.a.tay...@intel.com Upstreaming Chromium backlight related patches which including minimum duty cycle and 0..max_brightness scaling of the sysfs requested brightness level. Ben Widawsky (5): CHROMIUM: drm/i915/vlv: Initialize pipe B backlight to A's value

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