[Intel-gfx] ✓ Ro.CI.BAT: success for drm/i915: Give crtcs and planes actual names (v5)

== Series Details == Series: drm/i915: Give crtcs and planes actual names (v5) URL : https://patchwork.freedesktop.org/series/7905/ State : success == Summary == Series 7905v1 drm/i915: Give crtcs and planes actual names (v5)

Re: [Intel-gfx] [PATCH 06/23] drm/i915/kbl: Add WaEnableGapsTsvCreditFix

On 26/05/2016 20:59, Mika Kuoppala wrote: We need this crucial workaround from skl also to all kbl revisions. Lack of it was causing system hangs on skl enabling so this is a must have. References: HSD#2126660 Signed-off-by: Mika Kuoppala ---

Re: [Intel-gfx] [v4.6-10530-g28165ec7a99b] i915: *ERROR* "CPU pipe/PCH transcoder" A FIFO underrun

On 25 May 2016 at 08:31, Sedat Dilek wrote: > Hi Daniel, > > with latest Linus Git I see this with my Intel SandyBridge GPU... > > [ 17.629014] [drm:intel_cpu_fifo_underrun_irq_handler [i915]] > *ERROR* CPU pipe A FIFO underrun > [ 17.630652]

Re: [Intel-gfx] [PATCH 09/23] drm/i915/edp: Add WaKVMNotificationOnConfigChange:bdw, skl

Mika Kuoppala writes: > [ text/plain ] > According to bspec this workaround helps to reduce lag and improve > performance on edp. > Bspec says this is for bdw,skl. wa database says this is for bdw and all gen9. If we write to 0x42090 on kbl,skl it doesn't hold

Re: [Intel-gfx] [PATCH 08/12] drm/i915: Allow calling intel_adjust_tile_offset() multiple times

On Tue, May 03, 2016 at 06:39:57PM +0300, ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä > > Minimize the resulting X coordinate after intel_adjust_tile_offset() is > done with it's offset adjustment. This allows calling > intel_adjust_tile_offset()

[Intel-gfx] drm/i915 4.5/4.6 stable backport request for CHV

From: Ville Syrjälä Several nasty i915 regressions affecting CHV slipped through to 4.5 and 4.6. The first fix we want in 4.5 and 4.6 is commit caed361d83b2 ("drm/i915: Fix watermarks for VLV/CHV") It won't cherry-pick cleanly to either one, so I've included

[Intel-gfx] [PATCH for v4.6] drm/i915: Fix watermarks for VLV/CHV

From: Ville Syrjälä commit caed361d83b2 upstream commit 92826fcdfc14 ("drm/i915: Calculate watermark related members in the crtc_state, v4.") broke thigns by removing the pre vs. post wm update distinction. We also lost the pre plane wm update entirely for

[Intel-gfx] [PATCH for v4.5] drm/i915: Fix watermarks for VLV/CHV

From: Ville Syrjälä commit caed361d83b2 upstream commit 92826fcdfc14 ("drm/i915: Calculate watermark related members in the crtc_state, v4.") broke thigns by removing the pre vs. post wm update distinction. We also lost the pre plane wm update entirely for

[Intel-gfx] ✗ Ro.CI.BAT: failure for drm/i915: Fix watermarks for VLV/CHV

== Series Details == Series: drm/i915: Fix watermarks for VLV/CHV URL : https://patchwork.freedesktop.org/series/7867/ State : failure == Summary == Applying: drm/i915: Fix watermarks for VLV/CHV Patch failed at 0001 drm/i915: Fix watermarks for VLV/CHV The copy of the patch that failed is

Re: [Intel-gfx] ✗ Ro.CI.BAT: failure for series starting with [v2,1/2] drm/i915/gen9: Assume CDCLK PLL is off if it's not locked

On ti, 2016-05-24 at 16:18 +0300, Imre Deak wrote: > On ti, 2016-05-24 at 13:02 +, Patchwork wrote: > > == Series Details == > > > > Series: series starting with [v2,1/2] drm/i915/gen9: Assume CDCLK PLL > > is off if it's not locked > > URL   : https://patchwork.freedesktop.org/series/7631/ >

[Intel-gfx] [PATCH i-g-t 1/8] tests/gem_exec_flush: Tune down BAT timeout to ~1sec.

Signed-off-by: Marius Vlad --- tests/gem_exec_flush.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/gem_exec_flush.c b/tests/gem_exec_flush.c index d08b843..b608060 100644 --- a/tests/gem_exec_flush.c +++ b/tests/gem_exec_flush.c @@ -523,7

[Intel-gfx] [PATCH i-g-t 4/8] tests/gem_close_race: Tune down for BAT ~1s.

Signed-off-by: Marius Vlad --- tests/gem_close_race.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/gem_close_race.c b/tests/gem_close_race.c index 94fb905..45aa2cc 100644 --- a/tests/gem_close_race.c +++ b/tests/gem_close_race.c @@ -232,7

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Handle fb->offsets[] and rewrite fb rotation handling to be more generic (v4)

On Fri, May 27, 2016 at 02:43:32PM +0300, Ville Syrjälä wrote: > On Tue, May 03, 2016 at 04:25:20PM -, Patchwork wrote: > > == Series Details == > > > > Series: drm/i915: Handle fb->offsets[] and rewrite fb rotation handling to > > be more generic (v4) > > URL :

Re: [Intel-gfx] [PATCH i-g-t 4/8] tests/gem_close_race: Tune down for BAT ~1s.

On 27/05/16 13:16, Chris Wilson wrote: On Fri, May 27, 2016 at 01:10:07PM +0100, Tvrtko Ursulin wrote: On 27/05/16 12:58, Chris Wilson wrote: On Fri, May 27, 2016 at 02:50:34PM +0300, Marius Vlad wrote: Signed-off-by: Marius Vlad Nak. It's a race detector. Please

Re: [Intel-gfx] [PATCH i-g-t 4/8] tests/gem_close_race: Tune down for BAT ~1s.

On Fri, May 27, 2016 at 01:31:10PM +0100, Tvrtko Ursulin wrote: > > On 27/05/16 13:16, Chris Wilson wrote: > >On Fri, May 27, 2016 at 01:10:07PM +0100, Tvrtko Ursulin wrote: > >> > >>On 27/05/16 12:58, Chris Wilson wrote: > >>>On Fri, May 27, 2016 at 02:50:34PM +0300, Marius Vlad wrote: >

[Intel-gfx] [PATCH 01/11] drm: Export drm_dev_init() for subclassing

In order to allow drivers to pack their privates and drm_device into one struct (e.g. for subclassing), export the initialisation routines for struct drm_device. Signed-off-by: Chris Wilson Cc: Daniel Vetter Cc: dri-de...@lists.freedesktop.org

[Intel-gfx] [PATCH 01/24] drm/i915/kbl: Init gen9 workarounds

Kabylake is part of gen9 family so init the generic gen9 workarounds for it. Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/intel_ringbuffer.c | 48 ++--- 1 file changed, 32 insertions(+), 16 deletions(-) diff --git

[Intel-gfx] [PATCH 03/24] drm/i915/kbl: Add WaSkipStolenMemoryFirstPage for A0

We need this for kbl a0 boards. Note that this should be also for bxt A0 but we omit that on purpose as bxt A0's are out of fashion already. References: HSD#1912158, HSD#4393097 Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/i915_gem_stolen.c | 6 -- 1 file

[Intel-gfx] [PATCH 02/24] drm/i915/kbl: Add REVID macro

Add REVID macro for kbl to limit wa applicability to particular revision range. Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/i915_drv.h | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h

[Intel-gfx] [PATCH 10/11] drm/i915: Split out the PCI driver interface to i915_pci.c

To reclaim a bit of space from i915_drv.c, we can move the routines that just hook us into the PCI device tree into i915_pci.c Signed-off-by: Chris Wilson Cc: Daniel Vetter --- drivers/gpu/drm/i915/Makefile | 1 +

[Intel-gfx] [PATCH 05/11] drm/i915: Register debugfs interface last

Currently debugfs files are created before the driver is even loads. This gives the opportunity for userspace to open that interface and poke around before the backing data structures are initialised - with the possibility of oopsing or worse. Move the creation of the debugfs files to our

[Intel-gfx] [PATCH 04/11] drm/i915: Move connector registration to driver registration phase

Don't try and present the connectors to userspace (via sysfs and other devices) before the driver is ready. Correspondingly, be sure to make the userspace interfaces disappear first. Signed-off-by: Chris Wilson Cc: Daniel Vetter Cc: Ville

[Intel-gfx] [PATCH 06/11] drm/i915: Demidlayer driver loading

Take control over allocating, loading and registering the driver from the DRM midlayer by performing it manually from i915_pci_probe. This allows us to carefully control the order of when we setup the hardware vs when it becomes visible to third parties (including userspace). The current ordering

[Intel-gfx] [PATCH 07/11] drm/i915: Demidlayer driver unloading

To complete the transition to manual control of load/unload, we need to take over unloading from i915_pci_remove(). This allows us to correctly order our unregister vs shutdown phases, which currently are inverted due to the midlayer. However, the unload sequence is still invalid as we shutdown

[Intel-gfx] [PATCH 08/11] drm/i915: Start exploiting drm_device subclassing

Baby step, update to_i915() conversion from drm_device to drm_i915_private: textdata bss dec hex filename 1108812 23207 416 1132435 114793 i915.ko (before) 1104999 23207 416 1128622 1138ae i915.ko (after) Signed-off-by: Chris Wilson Cc:

[Intel-gfx] Reordering debugfs registration vs driver loading

What started out as a simple patch turned into a midlayer minefield, thanks Daniel. The result though should be something much, much safer for asynchronous loading - please review kindly! -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org

[Intel-gfx] [PATCH 02/11] drm: Add a callback from connector registering

If a driver wants to more precisely control its initialisation and in particular, defer registering its interfaces with userspace until after everything is setup, it also needs to defer registering the connectors. As some devices need more work during registration, add a callback so that drivers

[Intel-gfx] [PATCH 11/11] drm/i915: Move module init/exit to i915_pci.c

The module init/exit routines are a wrapper around the PCI device init/exit, so move them across. Signed-off-by: Chris Wilson Cc: Daniel Vetter --- drivers/gpu/drm/i915/i915_drv.c | 51 +++--

[Intel-gfx] [PATCH 03/11] drm/i915: Perform async fbdev initialisation much later

Setting up fbdev requires everything ready and registered (in particular the connectors). In the next patch, we defer registration of the KMS objects and unless we defer setting off fbdev, it may run before they are registered and oops. Signed-off-by: Chris Wilson ---

Re: [Intel-gfx] [PATCH 08/11] drm/i915: Start exploiting drm_device subclassing

On 27/05/16 15:00, Chris Wilson wrote: Baby step, update to_i915() conversion from drm_device to drm_i915_private: text data bss dec hex filename 1108812 23207 416 1132435 114793 i915.ko (before) 1104999 23207 416 1128622 1138ae i915.ko (after) This

Re: [Intel-gfx] [PATCH i-g-t 4/8] tests/gem_close_race: Tune down for BAT ~1s.

On Fri, May 27, 2016 at 03:44:20PM +0300, Mika Kuoppala wrote: > Tvrtko Ursulin writes: > > > [ text/plain ] > > > > On 27/05/16 13:16, Chris Wilson wrote: > >> On Fri, May 27, 2016 at 01:10:07PM +0100, Tvrtko Ursulin wrote: > >>> > >>> On 27/05/16 12:58, Chris

Re: [Intel-gfx] [PATCH i-g-t 4/8] tests/gem_close_race: Tune down for BAT ~1s.

On Fri, May 27, 2016 at 01:16:06PM +0100, Chris Wilson wrote: > On Fri, May 27, 2016 at 01:10:07PM +0100, Tvrtko Ursulin wrote: > > > > On 27/05/16 12:58, Chris Wilson wrote: > > >On Fri, May 27, 2016 at 02:50:34PM +0300, Marius Vlad wrote: > > >>Signed-off-by: Marius Vlad

[Intel-gfx] [PATCH 09/24] drm/i915/edp: Add WaKVMNotificationOnConfigChange:bdw

According to bspec this workaround helps to reduce lag and improve performance on edp. Documentation suggests this for bdw and all gen9. However evidence shows that this register is missing on gen9 and causing unclaimed mmio access if we access it. So apply to bdw only where the reg exists and

[Intel-gfx] [PATCH 11/24] drm/i915/gen9: Enable must set chicken bits in config0 reg

The bspec states that these must be set in CONFIG0 for all gen9. v2: rebase References: HSD#2134995 Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/i915_reg.h | 3 +++ drivers/gpu/drm/i915/intel_pm.c | 24 ++-- 2 files changed, 17

[Intel-gfx] [PATCH 05/24] drm/i915: Mimic skl with WaForceEnableNonCoherent

Past evidence with system hangs and hsds tie WaForceEnableNonCoherent and WaDisableHDCInvalidation to WaForceContextSaveRestoreNonCoherent. Documentation states that WaForceContextSaveRestoreNonCoherent would not be needed on skl past E0 but evidence proved otherwise. See commit <510650e8b2ab>

[Intel-gfx] [PATCH 18/24] drm/i915: Add WaDisableGafsUnitClkGating for skl and kbl

We need this gafs bit to be enabled for hw fix to take effect. References: HSD#2227156, HSD#2227050 Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_ringbuffer.c | 6 ++ 2 files changed, 7 insertions(+) diff

[Intel-gfx] [PATCH] drm/i915: Remove drm_i915_private->dev backpointer

Now that drm_i915_private contains drm_device, we can directly go to the drm_device as required: textdata bss dec hex filename 1105153 23207 416 1128776 113948 i915.ko (before) 1102849 23207 416 1126472 113048 i915.ko (after) s/dev_priv->dev->/dev_priv->drm./

[Intel-gfx] [PATCH 17/24] drm/i915/kbl: Add WaForGAMHang

Add this workaround for A0 and B0 revisions References: HSD#2226935 Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/intel_lrc.c | 36 ++-- 1 file changed, 34 insertions(+), 2 deletions(-) diff --git

[Intel-gfx] [PATCH 07/24] drm/i915/kbl: Add WaDisableFenceDestinationToSLM for A0

Add this workaround for kbl revid A0 only. v2: rebase References: HSD#1911714 Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/intel_lrc.c| 16 drivers/gpu/drm/i915/intel_ringbuffer.c | 5 + 2 files changed, 21 insertions(+) diff

[Intel-gfx] [PATCH 06/24] drm/i915/kbl: Add WaEnableGapsTsvCreditFix

We need this crucial workaround from skl also to all kbl revisions. Lack of it was causing system hangs on skl enabling so this is a must have. v2: Don't add revid checks to gen9 init workarounds (Arun) References: HSD#2126660 Cc: Arun Siluvery Signed-off-by: Mika

[Intel-gfx] [PATCH 10/24] drm/i915/kbl: Add WaDisableLSQCROPERFforOCL

Extend the scope of this workaround, already used in skl, to also take effect in kbl. References: HSD#2132677 Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/i915_drv.h | 3 +++ drivers/gpu/drm/i915/intel_lrc.c| 5 +++--

[Intel-gfx] [PATCH 20/24] drm/i915/gen9: Add WaEnableChickenDCPR

Workaround for display underrun issues with Y & Yf Tiling. Set this on all gen9 as stated by bspec. v2: proper workaround name References: HSD#2136383, BSID#857 Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/i915_reg.h | 3 +++ drivers/gpu/drm/i915/intel_pm.c | 4

Re: [Intel-gfx] [PATCH 21/24] drm/i915/gen9: Add WaFbcTurnOffFbcWatermark

On Fri, May 27, 2016 at 05:27:01PM +0300, Mika Kuoppala wrote: > According to bspec this prevents screen corruption when fbc is > used. > > v2: This workaround has a name, use it (Ville) > > References: HSD#213, HSD#2137270, BSID#562 > Cc: Paulo Zanoni >

Re: [Intel-gfx] [PATCH i-g-t 4/8] tests/gem_close_race: Tune down for BAT ~1s.

On Fri, May 27, 2016 at 01:10:07PM +0100, Tvrtko Ursulin wrote: > > On 27/05/16 12:58, Chris Wilson wrote: > >On Fri, May 27, 2016 at 02:50:34PM +0300, Marius Vlad wrote: > >>Signed-off-by: Marius Vlad > > > >Nak. It's a race detector. Please suggest how to increase

[Intel-gfx] [PATCH 04/24] drm/i915/gen9: Always apply WaForceContextSaveRestoreNonCoherent

The revision id range for this workaround has changed. So apply it to all revids on all gen9. References: HSD#2134449 Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/intel_ringbuffer.c | 11 --- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git

[Intel-gfx] [PATCH 08/24] drm/i915/kbl: Add WaDisableSDEUnitClockGating

Add this workaround until upto kbl revid B0. References: HSD#1802092 Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/intel_pm.c | 18 -- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c

[Intel-gfx] [PATCH 00/24] kbl and gen9 workarounds v2

WaKVMNotificationOnConfigChange was not for skl/bxt even tho the documentation claims so. Addressed Arun's comment about littering the generic gen workaround function with revid checks. Fbc ones have a names also as Ville pointed out. Added one patch to extend one skl workaround. -Mika Mika

[Intel-gfx] [PATCH 15/24] drm/i915/gen9: Add WaDisableSkipCaching

Make sure that we never enable skip caching on gen9 by accident. References: HSD#2134698 Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/intel_mocs.c | 10 ++ 1 file changed, 10 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_mocs.c

[Intel-gfx] [PATCH 21/24] drm/i915/gen9: Add WaFbcTurnOffFbcWatermark

According to bspec this prevents screen corruption when fbc is used. v2: This workaround has a name, use it (Ville) References: HSD#213, HSD#2137270, BSID#562 Cc: Paulo Zanoni Signed-off-by: Mika Kuoppala ---

[Intel-gfx] [PATCH 19/24] drm/i915/kbl: Add WaDisableSbeCacheDispatchPortSharing

This is needed for all kbl revision. v2: Don't add revid checks to generic gen9 init (Arun) References: HSD#2135593 Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/intel_ringbuffer.c | 5 + 1 file changed, 5 insertions(+) diff --git

[Intel-gfx] [PATCH 14/24] drm/i915: Add WaInsertDummyPushConstP for bxt and kbl

Add this workaround for both bxt and kbl up to until rev B0. References: HSD#2136703 Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_ringbuffer.c | 10 ++ 2 files changed, 11 insertions(+) diff --git

[Intel-gfx] [PATCH 23/24] drm/i195/fbc: Add WaFbcNukeOnHostModify

Bspec states that we need to set nuke on modify all to prevent screen corruption with fbc on skl and kbl. v2: proper workaround name References: HSD#2227109, HSDES#1404569388 Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/i915_reg.h | 1 +

[Intel-gfx] [PATCH 13/24] drm/i915/kbl: Add WaDisableDynamicCreditSharing

Bspec states that we need to turn off dynamic credit sharing on kbl revid a0 and b0. This happens by writing bit 28 on 0x4ab8. References: HSD#2225601, HSD#2226938, HSD#2225763 Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/i915_reg.h | 2 ++

[Intel-gfx] [PATCH 22/24] drm/i915/gen9: Add WaFbcWakeMemOn

Set bit 8 in 0x43224 to prevent screen corruption and system hangs on high memory bandwidth conditions. The same wa also suggest setting bit 31 on ARB_CTL. According to another workaround we gain better idle power savings when FBC is enabled. v2: use correct workaround name References:

[Intel-gfx] [PATCH 24/24] drm/i915/skl: Extend WaDisableChickenBitTSGBarrierAckForFFSliceCS

There is ambiguity in the documentation between D0 and E0. Extend this workaround to E0. References: BSID#779 Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/intel_ringbuffer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git

[Intel-gfx] [PATCH 12/24] drm/i915/kbl: Add WaDisableGamClockGating

According to bspec we need to disable gam unit clock gating on on kbl revids A0 and B0. References: HSD#2226858, HSD#1944358 Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_pm.c | 5 + 2 files changed, 6

[Intel-gfx] [PATCH 16/24] drm/i915/skl: Add WAC6entrylatency

This workaround is for fbc working with rc6 on skylake. Bspec states that setting this bit needs to be coordinated with uncore but offers no further details. v2: rebase References: HSD#4712857 Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/i915_reg.h | 3 +++

Re: [Intel-gfx] [PATCH 18/24] drm/i915: Add WaDisableGafsUnitClkGating for skl and kbl

On Fri, May 27, 2016 at 05:26:58PM +0300, Mika Kuoppala wrote: > We need this gafs bit to be enabled for hw fix to > take effect. > > References: HSD#2227156, HSD#2227050 > Signed-off-by: Mika Kuoppala > --- > drivers/gpu/drm/i915/i915_reg.h | 1 + >

Re: [Intel-gfx] Wrt golden MMIO/CFG snaphot in GVT-g

Curious why leaking BIOS configuration to VM is a security problem... Can someone elaborate this view? From: Wang, Zhi A Sent: Friday, May 27, 2016 6:05 PM To: intel-gfx@lists.freedesktop.org Cc: joonas.lahti...@linux.intel.com; Chris Wilson; Vetter, Daniel; tvrtko.ursu...@linux.intel.com;

Re: [Intel-gfx] FW: Wrt golden MMIO/CFG snaphot in GVT-g

On pe, 2016-05-27 at 10:05 +, Wang, Zhi A wrote: > For me I think maybe i915 could save the snapshot for GVT, then GVT-g > patch the snapshot itself, then there won’t be leaking happened I > think. Even we wrote a dedicated little program, we would do the same > thing. >   > From: Wang, Zhi A 

[Intel-gfx] [PATCH i-g-t 3/8] tests/gem_exec_nop: Tune down timeout for BAT ~1s.

Signed-off-by: Marius Vlad --- tests/gem_exec_nop.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/gem_exec_nop.c b/tests/gem_exec_nop.c index e90d5eb..1b2d144 100644 --- a/tests/gem_exec_nop.c +++ b/tests/gem_exec_nop.c @@ -213,7 +213,7 @@

[Intel-gfx] [PATCH i-g-t 8/8] tests/gem_exec_suspend: Remove hibernate test from BAT.

Signed-off-by: Marius Vlad --- tests/gem_exec_suspend.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/gem_exec_suspend.c b/tests/gem_exec_suspend.c index cd133cc..3d529bd 100644 --- a/tests/gem_exec_suspend.c +++ b/tests/gem_exec_suspend.c @@

[Intel-gfx] [PATCH i-g-t 5/8] tests/gem_sync: Tune down for BAT to ~1s for basic-each and ~2s for basic-all.

Signed-off-by: Marius Vlad --- tests/gem_sync.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tests/gem_sync.c b/tests/gem_sync.c index 320bce3..f824d1e 100644 --- a/tests/gem_sync.c +++ b/tests/gem_sync.c @@ -126,7 +126,7 @@ sync_ring(int fd,

[Intel-gfx] [PATCH i-g-t 7/8] tests/gem_tiled_pread_basic: Rename test and BATify.

Add a extended subtest and reduce the number of iteration to qualify for BAT. Renamed to test to gem_tiled_pread. Signed-off-by: Marius Vlad --- tests/Makefile.sources| 2 +- tests/gem_tiled_pread.c | 231 ++

[Intel-gfx] [PATCH i-g-t 6/8] tests/gem_exec_fault: Decrease the counts to lower the time for BAT.

Signed-off-by: Marius Vlad --- tests/gem_storedw_loop.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/gem_storedw_loop.c b/tests/gem_storedw_loop.c index 317b8c6..89f0182 100644 --- a/tests/gem_storedw_loop.c +++ b/tests/gem_storedw_loop.c @@

Re: [Intel-gfx] [PATCH] drm/i915: Reject modeset if the dotclock is too high

On Wed, May 25, 2016 at 11:15:35AM +0300, Jani Nikula wrote: > On Tue, 24 May 2016, ville.syrj...@linux.intel.com wrote: > > From: Ville Syrjälä > > > > Reject the modeset if the requested dotclock exceeds the maximum allowed > > by the hardware. So far we've only

Re: [Intel-gfx] [PATCH i-g-t 7/8] tests/gem_tiled_pread_basic: Rename test and BATify.

On Fri, May 27, 2016 at 02:50:37PM +0300, Marius Vlad wrote: > Add a extended subtest and reduce the number of iteration to qualify > for BAT. Renamed to test to gem_tiled_pread. No. This doesn't increase coverage. -Chris -- Chris Wilson, Intel Open Source Technology Centre

Re: [Intel-gfx] [PATCH i-g-t 6/8] tests/gem_exec_fault: Decrease the counts to lower the time for BAT.

On Fri, May 27, 2016 at 02:50:36PM +0300, Marius Vlad wrote: > Signed-off-by: Marius Vlad Summary and patch do not match. But you could remove gem_storedw_loop as everything BAT about it is tested elsewhere. -Chris -- Chris Wilson, Intel Open Source Technology Centre

Re: [Intel-gfx] [PATCH i-g-t 4/8] tests/gem_close_race: Tune down for BAT ~1s.

On Fri, May 27, 2016 at 01:10:07PM +0100, Tvrtko Ursulin wrote: > > On 27/05/16 12:58, Chris Wilson wrote: > >On Fri, May 27, 2016 at 02:50:34PM +0300, Marius Vlad wrote: > >>Signed-off-by: Marius Vlad > > > >Nak. It's a race detector. Please suggest how to increase

Re: [Intel-gfx] [PATCH i-g-t 4/8] tests/gem_close_race: Tune down for BAT ~1s.

Tvrtko Ursulin writes: > [ text/plain ] > > On 27/05/16 13:16, Chris Wilson wrote: >> On Fri, May 27, 2016 at 01:10:07PM +0100, Tvrtko Ursulin wrote: >>> >>> On 27/05/16 12:58, Chris Wilson wrote: On Fri, May 27, 2016 at 02:50:34PM +0300, Marius Vlad wrote:

Re: [Intel-gfx] [PATCH i-g-t] tests/gem_{ctx, exec}_create: Adjust timeout values for BAT

On Fri, May 20, 2016 at 08:53:12PM +0100, Chris Wilson wrote: > On Fri, May 20, 2016 at 08:02:46PM +0300, Marius Vlad wrote: > > Tune down from 20s to 2s. Add the old timeout values under extended tests. > > Does it fail with the new timeout? If not, increase it. > > This test should be a fail

[Intel-gfx] [PATCH i-g-t 2/8] tests/gem_ctx_switch: Tune down for BAT ~1s.

Signed-off-by: Marius Vlad --- tests/gem_ctx_switch.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/tests/gem_ctx_switch.c b/tests/gem_ctx_switch.c index 7b27336..066a5fc 100644 --- a/tests/gem_ctx_switch.c +++ b/tests/gem_ctx_switch.c @@ -73,6

Re: [Intel-gfx] [PATCH i-g-t 2/8] tests/gem_ctx_switch: Tune down for BAT ~1s.

On Fri, May 27, 2016 at 02:50:32PM +0300, Marius Vlad wrote: > Signed-off-by: Marius Vlad Nak. Please suggest how to improve reliablity first. -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing

[Intel-gfx] [PATCH 4/4] drm/i915: Update kerneldoc for intel_dpll_mgr.c

The documentation for most of the non-static members and structs were missing. Fix that. v2: Fix typos (Durga) Cc: Daniel Vetter Signed-off-by: Ander Conselvan de Oliveira Reviewed-by: Durgadoss R ---

[Intel-gfx] [PATCH 1/4] drm/i915: Introduce intel_release_shared_dpll()

While the details of getting a shared dpll are wrapped by intel_get_shared_dpll(), the release was still hand rolled into the modeset code. Fix that by creating an entry point for releasing the pll and move that code there. v2: Take old_dpll from crtc->state instead of crtc_state. (CI)

[Intel-gfx] [PATCH 2/4] drm/i915: Rename intel_shared_dpll_commit() to _swap_state()

The function intel_shared_dpll_commit() performs the equivalent of drm_atomic_helper_swap_state() for the shared dpll state, which is not handled by the helpers. So rename it for consistency. v2: Fix typo in the commit message. (Durga) Signed-off-by: Ander Conselvan de Oliveira

[Intel-gfx] [PATCH 3/4] drm/i915: Rename intel_shared_dpll->mode_set() to prepare()

The hook is called from intel_prepare_shared_dpll(). The name doesn't make sense after all the changes to modeset code. So just call it prepare. Signed-off-by: Ander Conselvan de Oliveira Reviewed-by: Durgadoss R ---

Re: [Intel-gfx] [PATCH i-g-t] igt_core: Search "." as final fallback for igt_fopen_data()

Pushed. On Thu, May 26, 2016 at 04:02:05PM -0700, Matt Roper wrote: > Some validation teams seem to run tests out of source directories that > have been nfs mounted or rsync'd to different locations on the target > machine. This causes the igt_srcdir that the tests were built with to > be

Re: [Intel-gfx] [PATCH i-g-t 1/8] tests/gem_exec_flush: Tune down BAT timeout to ~1sec.

On Fri, May 27, 2016 at 02:50:31PM +0300, Marius Vlad wrote: > Signed-off-by: Marius Vlad Nak. Please suggest how to make this test reliable first. At the moment, we need to increase the time. -Chris -- Chris Wilson, Intel Open Source Technology Centre

[Intel-gfx] ✗ Ro.CI.BAT: failure for series starting with [1/4] drm/i915: Introduce intel_release_shared_dpll()

== Series Details == Series: series starting with [1/4] drm/i915: Introduce intel_release_shared_dpll() URL : https://patchwork.freedesktop.org/series/7872/ State : failure == Summary == Series 7872v1 Series without cover letter

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Handle fb->offsets[] and rewrite fb rotation handling to be more generic (v4)

On Tue, May 03, 2016 at 04:25:20PM -, Patchwork wrote: > == Series Details == > > Series: drm/i915: Handle fb->offsets[] and rewrite fb rotation handling to be > more generic (v4) > URL : https://patchwork.freedesktop.org/series/6688/ > State : failure > > == Summary == > > Series 6688v1

Re: [Intel-gfx] [PATCH i-g-t 4/8] tests/gem_close_race: Tune down for BAT ~1s.

On Fri, May 27, 2016 at 02:50:34PM +0300, Marius Vlad wrote: > Signed-off-by: Marius Vlad Nak. It's a race detector. Please suggest how to increase detection rates. -Chris -- Chris Wilson, Intel Open Source Technology Centre

Re: [Intel-gfx] [PATCH i-g-t 5/8] tests/gem_sync: Tune down for BAT to ~1s for basic-each and ~2s for basic-all.

On Fri, May 27, 2016 at 02:50:35PM +0300, Marius Vlad wrote: > Signed-off-by: Marius Vlad NAK. gem_sync is not reliable enough, please suggest how to improve detection rates for *existing* issues. -Chris -- Chris Wilson, Intel Open Source Technology Centre

Re: [Intel-gfx] [PATCH] drm/i915: Reject modeset if the dotclock is too high

On Wed, May 25, 2016 at 11:15:35AM +0300, Jani Nikula wrote: > On Tue, 24 May 2016, ville.syrj...@linux.intel.com wrote: > > From: Ville Syrjälä > > > > Reject the modeset if the requested dotclock exceeds the maximum allowed > > by the hardware. So far we've only

[Intel-gfx] FW: Wrt golden MMIO/CFG snaphot in GVT-g

For me I think maybe i915 could save the snapshot for GVT, then GVT-g patch the snapshot itself, then there won't be leaking happened I think. Even we wrote a dedicated little program, we would do the same thing. From: Wang, Zhi A Sent: Friday, May 27, 2016 12:59 PM To:

Re: [Intel-gfx] ✗ Ro.CI.BAT: warning for drm/i915: Reject modeset if the dotclock is too high

On Wed, May 25, 2016 at 05:22:21AM -, Patchwork wrote: > == Series Details == > > Series: drm/i915: Reject modeset if the dotclock is too high > URL : https://patchwork.freedesktop.org/series/7653/ > State : warning > > == Summary == > > Series 7653v1 drm/i915: Reject modeset if the

Re: [Intel-gfx] [PATCH i-g-t 3/8] tests/gem_exec_nop: Tune down timeout for BAT ~1s.

On Fri, May 27, 2016 at 02:50:33PM +0300, Marius Vlad wrote: You need some explanation here to explain how you believe that all the corner-cases from this minimal stress test are covered elsewhere. -Chris -- Chris Wilson, Intel Open Source Technology Centre

Re: [Intel-gfx] ✗ Ro.CI.BAT: failure for drm/i915: Refresh cached DP port register value on resume

On Fri, May 13, 2016 at 11:13:19PM -, Patchwork wrote: > == Series Details == > > Series: drm/i915: Refresh cached DP port register value on resume > URL : https://patchwork.freedesktop.org/series/7163/ > State : failure > > == Summary == > > Series 7163v1 drm/i915: Refresh cached DP port

Re: [Intel-gfx] [PATCH i-g-t 8/8] tests/gem_exec_suspend: Remove hibernate test from BAT.

On Fri, May 27, 2016 at 02:50:38PM +0300, Marius Vlad wrote: > Signed-off-by: Marius Vlad Nak. Please suggest how to fix the broken machines first. -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx

Re: [Intel-gfx] Wrt golden MMIO/CFG snaphot in GVT-g

On pe, 2016-05-27 at 10:09 +, Tian, Kevin wrote: > Curious why leaking BIOS configuration to VM is a security problem… > Can someone elaborate this view? >   Hi, It is a potential vector in case we are blindly reading everything but blacklisted registers. Whitelisting would make it less so.

Re: [Intel-gfx] [PATCH i-g-t 4/8] tests/gem_close_race: Tune down for BAT ~1s.

On 27/05/16 12:58, Chris Wilson wrote: On Fri, May 27, 2016 at 02:50:34PM +0300, Marius Vlad wrote: Signed-off-by: Marius Vlad Nak. It's a race detector. Please suggest how to increase detection rates. As a more or less well know TV personality would say - "it's

[Intel-gfx] ✗ Ro.CI.BAT: failure for kbl and gen9 workarounds (rev6)

== Series Details == Series: kbl and gen9 workarounds (rev6) URL : https://patchwork.freedesktop.org/series/7824/ State : failure == Summary == Series 7824v6 kbl and gen9 workarounds http://patchwork.freedesktop.org/api/1.0/series/7824/revisions/6/mbox Test gem_exec_flush: Subgroup

[Intel-gfx] ✗ Ro.CI.BAT: failure for series starting with [01/11] drm: Export drm_dev_init() for subclassing (rev2)

== Series Details == Series: series starting with [01/11] drm: Export drm_dev_init() for subclassing (rev2) URL : https://patchwork.freedesktop.org/series/7890/ State : failure == Summary == Applying: drm: Export drm_dev_init() for subclassing Applying: drm: Add a callback from connector

Re: [Intel-gfx] Regression in i915 in kernel 4.6.0-git - bisected to f21a21983ef13a031

The latest mainline kernel (commit 3f59de0) shows a regression. The symptom is that as soon as the kernel is started, the display is blanked, and it is never turned on again. This problem was bisected to commit f21a21983ef13a031250c4c3f6018e29a549d0f1 ("drm/i915: Splitting intel_dp_detect").

Re: [Intel-gfx] [PATCH 07/24] drm/i915/kbl: Add WaDisableFenceDestinationToSLM for A0

On Fri, May 27, 2016 at 05:26:47PM +0300, Mika Kuoppala wrote: > Add this workaround for kbl revid A0 only. 2 w/a in one patch, WaClearSlmSpaceAtContextSwitch:kbl is not mentioned here. -Chris -- Chris Wilson, Intel Open Source Technology Centre ___

Re: [Intel-gfx] [PATCH 01/11] drm: Export drm_dev_init() for subclassing

Hi, Chris See comment below BR Nils On 27 May 2016 7:01 a.m., "Chris Wilson" wrote: > > In order to allow drivers to pack their privates and drm_device into one > struct (e.g. for subclassing), export the initialisation routines for > struct drm_device. > >

Re: [Intel-gfx] [PATCH 01/11] drm: Export drm_dev_init() for subclassing

On Fri, May 27, 2016 at 05:29:43PM +0200, Nils Wallménius wrote: >Hi, Chris > >See comment below > >>  err_setunique: >>         if (drm_core_check_feature(dev, DRIVER_GEM)) >> @@ -653,8 +650,46 @@ err_minors: >>         drm_fs_inode_free(dev->anon_inode); >>  

[Intel-gfx] [PATCH i-g-t v2 6/8] tests/gem_storedw_loop: Remove from BAT.

Signed-off-by: Marius Vlad --- tests/gem_storedw_loop.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/gem_storedw_loop.c b/tests/gem_storedw_loop.c index 317b8c6..a0c5af1 100644 --- a/tests/gem_storedw_loop.c +++ b/tests/gem_storedw_loop.c @@

[Intel-gfx] [PATCH i-g-t v2 2/8] tests/gem_ctx_switch: Remove test from BAT.

Signed-off-by: Marius Vlad --- tests/gem_ctx_switch.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/gem_ctx_switch.c b/tests/gem_ctx_switch.c index 7b27336..ce52365 100644 --- a/tests/gem_ctx_switch.c +++ b/tests/gem_ctx_switch.c @@ -157,7

[Intel-gfx] [PATCH i-g-t v2 1/8] tests/gem_exec_flush: Remove tests from BAT.

Signed-off-by: Marius Vlad --- tests/gem_exec_flush.c | 15 +-- 1 file changed, 5 insertions(+), 10 deletions(-) diff --git a/tests/gem_exec_flush.c b/tests/gem_exec_flush.c index d08b843..2f271bb 100644 --- a/tests/gem_exec_flush.c +++

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