In order to ensure that our system suspend and resume callbacks are
called in the correct order wrt. those of the HDA driver add a device
link to the HDA driver during audio component binding time. With i915 as
the supplier and HDA as the consumer the PM framework will guarantee
the HDA->i915
On Thu, Oct 18, 2018 at 01:51:31PM +0200, Maarten Lankhorst wrote:
> The first 3 planes (primary, sprite 0 and 1) have a dedicated chroma
> upsampler to upscale YUV420 to YUV444 and the scaler should only be
> used for upscaling. Because of this we shouldn't program the scalers
> in planar mode if
On Thu, Oct 18, 2018 at 01:51:26PM +0200, Maarten Lankhorst wrote:
> New version, with a lot of reworking to incorporate all the feedback.
>
> We currently don't set the plane input CSC correctly, so colors are a
> bit off. As a result I can't verify for 100% we program the chroma
> upsampler
On Thu, Oct 18, 2018 at 01:51:30PM +0200, Maarten Lankhorst wrote:
> Skylake style watermarks program the UV parameters into wm->uv_wm,
> and have a separate DDB allocation for UV blocks into the same plane.
>
> Gen11 watermarks have a separate plane for Y and UV, with separate
> mechanisms. The
On Fri, Oct 05, 2018 at 04:23:02PM -0700, Manasi Navare wrote:
> Display Stream Splitter registers need to be programmed to enable
> the joiner if two DSC engines are used and also to enable
> the left and the right DSC engines. This happens as part of
> the DSC enabling routine in the source in
On Thu, Oct 18, 2018 at 03:52:27PM +0100, Tvrtko Ursulin wrote:
>
> On 16/10/2018 16:04, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Replace the kvmalloc_array() with i915_gem_object_get_dma_address() when
> > populating rotated vmas. One random access mechanism ought to be enough
> >
On Tue, Oct 16, 2018 at 03:01:32PM -0700, Paulo Zanoni wrote:
> With this one here we can finally drop the intel state structures from
> the functions that compute watermark values: they all rely on struct
> skl_wm_params now. This should help the watermarks code be a little
> more clear on its
On Tue, Oct 16, 2018 at 03:01:33PM -0700, Paulo Zanoni wrote:
> Stop passing modeset state structures to functions that should work
> only with the skl_wm_params. The only use for cstate there was to
> reach dev_priv, so pass it directly.
>
> Signed-off-by: Paulo Zanoni
Reviewed-by: Ville
HI,
> -Original Message-
> From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
> Paulo Zanoni
> Sent: keskiviikko 17. lokakuuta 2018 1.53
> To: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for More watermarks improvements
>
>
On Thu, Oct 18, 2018 at 01:51:27PM +0200, Maarten Lankhorst wrote:
> On gen11, we can definitely smash the 32-bits barrier with just a
> when we enable all planes in the next patch.
>
> Signed-off-by: Maarten Lankhorst
> ---
> drivers/gpu/drm/i915/intel_pm.c | 47
On Thu, Oct 18, 2018 at 01:51:34PM +0200, Maarten Lankhorst wrote:
> Signed-off-by: Maarten Lankhorst
I guess the skl_has_planar() thing should be in this patch..
> ---
> drivers/gpu/drm/i915/intel_display.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git
On Thu, Oct 18, 2018 at 04:55:52PM +0300, Ville Syrjälä wrote:
> On Tue, Oct 16, 2018 at 03:01:30PM -0700, Paulo Zanoni wrote:
> > Print a more generic "failed to compute watermark levels" whenever any
> > of skl_compute_wm_levels() fail, and print only the specific error
> > message for the
Op 18-10-18 om 17:16 schreef Ville Syrjälä:
> On Thu, Oct 18, 2018 at 01:51:26PM +0200, Maarten Lankhorst wrote:
>> New version, with a lot of reworking to incorporate all the feedback.
>>
>> We currently don't set the plane input CSC correctly, so colors are a
>> bit off. As a result I can't
drm-misc-fixes-2018-10-18:
drm-misc-fixes for v4.19:
- Fix use of freed memory in drm_mode_setcrtc.
- Reject pixel format changing requests in fb helper.
- Add 6 bpc quirk for HP Pavilion 15-n233sl
- Fix VSDB yCBCr420 Deep Color mode bit definitions
The following changes since commit
== Series Details ==
Series: drm/i915: Ensure proper HDA suspend/resume ordering with a device link
URL : https://patchwork.freedesktop.org/series/51189/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5008 -> Patchwork_10504 =
== Summary - SUCCESS ==
No regressions
Hi Dave,
Here comes the final set of fixes under -next-fixes umbrella.
Next one will be then from -fixes, assuming a release next Sun.
Fixes for bunch of display related issues reported by users, then the
MST fixes that were dropped from Rodrigos PR + further Icelake fixes
and proactive
On Thu, Oct 18, 2018 at 11:57:06AM +0200, Daniel Vetter wrote:
> On Fri, Oct 12, 2018 at 11:45 PM Jeff McGee wrote:
> >
> > On Fri, Oct 12, 2018 at 02:33:26PM -0700, Jeff McGee wrote:
> > > On Fri, Oct 12, 2018 at 01:51:46PM -0700, Rodrigo Vivi wrote:
> > > > On Fri, Oct 12, 2018 at 01:24:30PM
On Thu, Oct 18, 2018 at 01:51:33PM +0200, Maarten Lankhorst wrote:
> The UV plane is the master plane that does all color correction etc.
> It needs to be programmed with the dimensions for color plane 1 (UV).
>
> The Y plane just feeds the Y pixels to it. Program the scaler from the
> master
From: Tvrtko Ursulin
A bunch of patches to trace.pl and gem_wsim which enable simulation and load
balancing analysis of the Virtual Engine work done separately by Chris Wilson.
Culmination is being able to simulate a so called frame split media workloads.
Example workload for this looks like
On Tue, Oct 16, 2018 at 03:01:30PM -0700, Paulo Zanoni wrote:
> Print a more generic "failed to compute watermark levels" whenever any
> of skl_compute_wm_levels() fail, and print only the specific error
> message for the specific cases. This allows us to stop passing pstate
> everywhere, making
On Thu, Oct 18, 2018 at 01:51:32PM +0200, Maarten Lankhorst wrote:
> We configure the chroma upsampler with the same chroma siting as
> used by the scaler for consistency, the chroma upsampler is used
> instead of the scaler for YUV 4:2:0 on ICL's HDR planes.
>
> Signed-off-by: Maarten Lankhorst
Pushed, because I need to get this cherry picked and included in PR.
Thanks for the review.
Regards, Joonas
Quoting Patchwork (2018-10-18 13:12:43)
> == Series Details ==
>
> Series: drm/i915: Drop rpm wakeref on error in debugfs/i915_drop_caches_set
> URL :
On 23/07/2018 13:14, Chris Wilson wrote:
Modernise the test to use igt's ioctl library as opposed to the
antiquated libdrm_intel.
Signed-off-by: Chris Wilson
---
tests/gem_tiled_fence_blits.c | 188 --
1 file changed, 110 insertions(+), 78 deletions(-)
diff
On Thu, 18 Oct 2018 16:25:58 +0200,
Imre Deak wrote:
>
> In order to ensure that our system suspend and resume callbacks are
> called in the correct order wrt. those of the HDA driver add a device
> link to the HDA driver during audio component binding time. With i915 as
> the supplier and HDA as
On Thu, Oct 18, 2018 at 01:51:29PM +0200, Maarten Lankhorst wrote:
> To make NV12 working on icl, we need to update 2 planes simultaneously.
> I've chosen to do this in the CRTC step after plane validation is done,
> so we know what planes are (in)visible. The linked Y plane will get
> updated in
On Tue, Oct 16, 2018 at 03:01:31PM -0700, Paulo Zanoni wrote:
> The function only really needs dev_priv to make its decision. If we
> ever need more, we can change it again. But then, in this case we
> should make needs_memory_bw_wa be a variable inside struct
> skl_wm_params so we won't need to
From: Tvrtko Ursulin
Sync with latest DRM uapi changes.
---
include/drm-uapi/amdgpu_drm.h | 52 +++-
include/drm-uapi/drm.h | 16 ++
include/drm-uapi/drm_fourcc.h | 224 +++
include/drm-uapi/drm_mode.h| 26 +-
include/drm-uapi/etnaviv_drm.h | 6 +
From: Tvrtko Ursulin
Parsing an integer workload descriptor field is a common pattern which we
can extract to a helper macro and by doing so further improve the
readability of the main parsing loop.
Signed-off-by: Tvrtko Ursulin
---
benchmarks/gem_wsim.c | 80
From: Tvrtko Ursulin
Support new i915 uAPI for configuring contexts with engine maps.
Please refer to the README file for more detailed explanation.
Signed-off-by: Tvrtko Ursulin
---
benchmarks/gem_wsim.c | 212 ++---
benchmarks/wsim/README | 17 +++-
2
From: Tvrtko Ursulin
We are moving towards bumping the uAPI headers more often instead of using
too much local struct/ioctl/param definitions since the latter are more
challenging for rebase and maintenance.
Signed-off-by: Tvrtko Ursulin
---
benchmarks/gem_wsim.c | 68
From: Tvrtko Ursulin
Use the 'completed?' tracepoint field to detect more robustly when a
request has been preempted and remove it from the engine database if so.
Otherwise the script can hit a scenario where the same global seqno will
be mentioned multiple times (on an engine seqno) which
From: Tvrtko Ursulin
Add virtual/queue timelines to both stdout and HTML output.
A new timeline is created for each queue/virtual engine to display
associated requests in queued and runnable states. Once requests are
submitted to a real engine for executing they show up on the physical
engine
From: Tvrtko Ursulin
We can improve the parsing loop readability a bit more by avoiding some
line breaks caused by explicit NULL checks.
Signed-off-by: Tvrtko Ursulin
---
benchmarks/gem_wsim.c | 39 +++
1 file changed, 15 insertions(+), 24 deletions(-)
From: Tvrtko Ursulin
A few more opportunities to compact the code by using the error logging
helper.
Signed-off-by: Tvrtko Ursulin
---
benchmarks/gem_wsim.c | 54 ---
1 file changed, 15 insertions(+), 39 deletions(-)
diff --git a/benchmarks/gem_wsim.c
From: Tvrtko Ursulin
Support i915 virtual engine from gem_wsim (-b i915) and media-bench.pl
Signed-off-by: Tvrtko Ursulin
---
benchmarks/gem_wsim.c | 289 ++---
scripts/media-bench.pl | 9 +-
2 files changed, 251 insertions(+), 47 deletions(-)
diff
From: Tvrtko Ursulin
There is a repeated pattern with error handling which can be moved to a
macro to for better readability in the command parsing loop.
Signed-off-by: Tvrtko Ursulin
---
benchmarks/gem_wsim.c | 244 +++---
1 file changed, 88 insertions(+),
From: Tvrtko Ursulin
Add support for submit fences in a way similar to how normal input fences
are handled. Eg:
1.RCS.500-1000.0.0
1.VCS1.3000.s-1.0
1.VCS2.3000.s-2.0
Submit fences are signalled when the originating request enters the
submission backend.
Signed-off-by: Tvrtko Ursulin
From: Tvrtko Ursulin
A few additional workloads useful for experimenting with scheduling.
Signed-off-by: Tvrtko Ursulin
---
benchmarks/wsim/frame-split-60fps.wsim | 16
benchmarks/wsim/high-composited-game.wsim | 11 +++
benchmarks/wsim/media-1080p-player.wsim
From: Tvrtko Ursulin
Signed-off-by: Tvrtko Ursulin
---
benchmarks/gem_wsim.c | 34 +-
1 file changed, 21 insertions(+), 13 deletions(-)
diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c
index a77a322ee309..17325d2ceaf6 100644
---
From: Tvrtko Ursulin
For simulating frame split workloads it is useful to express a batch which
ends at the same time as the parallel submission on the respective bonded
engine. For this we add support for infinite batch durations and the batch
terminate command ('T'). Syntax looks like this:
From: Tvrtko Ursulin
A new workload command for enabling a load balanced context map (aka
Virtual Engine). Example usage:
1.B
This turns on load balancing for context one, assuming it has already been
configured with an engine map. Only DEFAULT engine specifier can be used
with load balanced
From: Tvrtko Ursulin
Signed-off-by: Tvrtko Ursulin
---
benchmarks/gem_wsim.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c
index adfc2b1bc819..2561817622f6 100644
--- a/benchmarks/gem_wsim.c
+++ b/benchmarks/gem_wsim.c
@@ -1170,7 +1170,6 @@
From: Tvrtko Ursulin
Engine bonds are an i915 uAPI applicable to load balanced contexts with
engine map. They allow expression rules of engine selection between two
contexts when submissions are also tied with submit fences.
Please refer to the README for a more detailed description.
On 18/10/18 02:13, Chris Wilson wrote:
Quoting Michal Wajdeczko (2018-10-18 00:22:43)
On Thu, 18 Oct 2018 01:09:19 +0200, Daniele Ceraolo Spurio
wrote:
On 17/10/18 13:29, Chris Wilson wrote:
Propagate the timeout on transferring the fw back to the caller where it
may act upon it,
On 18/10/18 03:41, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Upcoming GuC code will need to read the fused off engine masks as well,
and will also want to have them as enabled instead of disabled masks.
To consolidate the read-out place we can store them in this fashion inside
INTEL_INFO
On 2018.10.18 13:40:31 +0800, Xiong Zhang wrote:
> Currently the guest couldn't boot up under GVT-g environment as the
> following call trace exists:
> [ 272.504762] BUG: unable to handle kernel NULL pointer dereference at
> 0100
> [ 272.504834] Call Trace:
> [ 272.504852]
Quoting Tvrtko Ursulin (2018-10-18 16:28:13)
> @@ -1196,6 +1256,7 @@ prepare_workload(unsigned int id, struct workload *wrk,
> unsigned int flags)
> { .base.name =
> I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE,
> .engines_mask = -1,
>
In case of Legacy DP connector on TypeC port, the
flex IO DPMLE register is set to number of lanes configured
by the display driver which will be programmed into DDI_BUF_CTL
PORT_WIDTH_SELECTION.
This needs to be programmed before enabling the shared PLLs hence
add a pre_pll_enable hook for ICL
A collection of very small cleanups/improvements around doorbell checking
that do not deserve their own patch:
- Move doorbell-related HW defs to intel_guc_reg.h
- use GUC_NUM_DOORBELLS instead of GUC_DOORBELL_INVALID where
appropriate
- do not stop on error in guc_verify_doorbells
- do not
On Thu, Oct 18, 2018 at 10:32:37AM -0700, Jeff McGee wrote:
> On Thu, Oct 18, 2018 at 11:57:06AM +0200, Daniel Vetter wrote:
> > On Fri, Oct 12, 2018 at 11:45 PM Jeff McGee wrote:
> > >
> > > On Fri, Oct 12, 2018 at 02:33:26PM -0700, Jeff McGee wrote:
> > > > On Fri, Oct 12, 2018 at 01:51:46PM
Propagate the timeout on transferring the fw back to the caller where it
may act upon it, usually by restarting the xfer before failing.
v2: Simplify the wait to only wait upon the guc signaling completion,
with an assertion that the fw xfer must have completed for it to be
ready!
Testcase:
== Series Details ==
Series: series starting with [1/2] drm/i915/icl: Fix the macros for DFLEXDPMLE
register bits
URL : https://patchwork.freedesktop.org/series/51223/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5011 -> Patchwork_10509 =
== Summary - SUCCESS ==
No
On Mon, Oct 15, 2018 at 02:50:34PM -0700, Anusha Srivatsa wrote:
> For DP 1.4 and above, Display Stream compression can be
> enabled only if Forward Error Correctin can be performed.
>
> Check if the sink supports FEC using the helper.
>
> v2: Mention External DP where ever FEC is mentioned
> in
On Thu, Oct 18, 2018 at 11:12:21AM -0700, Rodrigo Vivi wrote:
> On Thu, Oct 18, 2018 at 10:32:37AM -0700, Jeff McGee wrote:
> > On Thu, Oct 18, 2018 at 11:57:06AM +0200, Daniel Vetter wrote:
> > > On Fri, Oct 12, 2018 at 11:45 PM Jeff McGee wrote:
> > > >
> > > > On Fri, Oct 12, 2018 at
On Mon, Oct 15, 2018 at 02:50:35PM -0700, Anusha Srivatsa wrote:
> If the panel supports FEC, the driver has to
> set the FEC_READY bit in the dpcd register:
> FEC_CONFIGURATION.
>
> This has to happen before link training.
>
> v2: s/intel_dp_set_fec_ready/intel_dp_sink_set_fec_ready
>-
Let's just handle SKL as special case instead of listing
platform by platform.
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_pm.c | 6 +-
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index
Whenever possible let's move towards preferring gen number
and or features instead of hard coding platform codename
everywhere.
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/intel_cdclk.c | 6 +++---
drivers/gpu/drm/i915/intel_ddi.c
Now that we have the number of ddi ports information available
let's use it instead of that ugly platform macro.
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_drv.c | 10 ++
drivers/gpu/drm/i915/i915_drv.h | 2 --
drivers/gpu/drm/i915/i915_irq.c | 5
Instead of a simple bool that shows if we have ddi ports
or not, let's highlight the number of ddi ports.
So we can use this information to determine the code
path instead of using platforms codenames.
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
Let's use this whenever it makes sense and code gets
easier to read.
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_ddi.c| 18 +-
drivers/gpu/drm/i915/intel_dp.c | 24 +---
drivers/gpu/drm/i915/intel_pm.c | 6 +++---
We don't need 2 different blocks.
Specially with on in ordered older-to-newer and the other
one newer-to-older.
Let's start always using newer-to-older order
when it makes sense.
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_cdclk.c | 91 ++
1 file
Also let's always consider next platform follows
the most recent one. Like we have done for transitioning
gen9 to gen10 and gent10 to gen11.
Let's use same approach for gen11+ and only introduce
changes later as needed.
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_cdclk.c |
Continuing with the goal of use less platform codenames:
let's group platforms who has gen10 display.
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/intel_cdclk.c | 2 +-
drivers/gpu/drm/i915/intel_color.c | 2 +-
The goal off this series is to start the trend of prefering
gen number and feature checks instead of hardcoding
individual platform names everywhere.
I tried to use coccinelle but I failed badly because
there are places where it makes sense to have platform
codenames still. On sort part it was
== Series Details ==
Series: re-organize a bit gen10 and gen11
URL : https://patchwork.freedesktop.org/series/51230/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Make number of ddi ports explicit.
Okay!
Commit: drm/i915: Use the ddi_ports
This patch fixes the macros used for defining the DFLEXDPMLE
register bit fields. This accounts for changes in the spec.
Fixes: a2bc69a1a9d6 ("drm/i915/icl: Add register definition for DFLEXDPMLE")
Cc: Animesh Manna
Cc: Paulo Zanoni
Cc: Jose Roberto de Souza
Signed-off-by: Manasi Navare
---
== Series Details ==
Series: drm/i915/guc: Propagate the fw xfer timeout (rev3)
URL : https://patchwork.freedesktop.org/series/51140/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_5010_full -> Patchwork_10507_full =
== Summary - FAILURE ==
Serious unknown changes coming
== Series Details ==
Series: series starting with [v2,1/6] drm/i915/guc: drop negative doorbell
alloc selftest (rev2)
URL : https://patchwork.freedesktop.org/series/51153/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_5011 -> Patchwork_10510 =
== Summary - FAILURE ==
== Series Details ==
Series: re-organize a bit gen10 and gen11
URL : https://patchwork.freedesktop.org/series/51230/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_5011 -> Patchwork_10511 =
== Summary - FAILURE ==
Serious unknown changes coming with Patchwork_10511
On Mon, Oct 15, 2018 at 02:50:36PM -0700, Anusha Srivatsa wrote:
> If FEC is supported, the corresponding
> DP_TP_CTL register bits have to be configured.
>
> The driver has to program the FEC_ENABLE in DP_TP_CTL[30] register
> and wait till FEC_STATUS in DP_TP_CTL[28] is 1.
> Also add the warn
Hi Anusha,
Find my comments below:
On Mon, Oct 15, 2018 at 02:50:37PM -0700, Anusha Srivatsa wrote:
> Set the suitable bits in DP_TP_CTL to stop
> bit correction when DSC is disabled.
>
> - rebased.
> - Add additional check for compression state. (Gaurav)
>
> v3: rebased.
>
> Cc: Gaurav K
== Series Details ==
Series: series starting with [v2,1/6] drm/i915/guc: drop negative doorbell
alloc selftest (rev2)
URL : https://patchwork.freedesktop.org/series/51153/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
fbae90ba884e drm/i915/guc: rename
On Thu, Oct 18, 2018 at 03:52:21PM +0300, Ville Syrjälä wrote:
> On Tue, Oct 16, 2018 at 04:09:19PM -0700, Rodrigo Vivi wrote:
> > On Tue, Oct 16, 2018 at 04:00:26PM -0700, Paulo Zanoni wrote:
> > > Em Sex, 2018-10-12 às 15:42 +0300, Ville Syrjälä escreveu:
> > > > On Thu, Oct 11, 2018 at
== Series Details ==
Series: re-organize a bit gen10 and gen11
URL : https://patchwork.freedesktop.org/series/51230/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
8c7a79b33eb4 drm/i915: Make number of ddi ports explicit.
e86a18876ae8 drm/i915: Use the ddi_ports info to kill
== Series Details ==
Series: series starting with [1/2] drm/i915: Relocate SKL+ NV12 src width w/a
URL : https://patchwork.freedesktop.org/series/51215/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_5010_full -> Patchwork_10508_full =
== Summary - FAILURE ==
Serious
We wrongly assumed that GuC is only using last scratch register
for G2H messages, but in fact it is also using register [14] to
report sleep state status. Remove that register from our H2G
send registers pool.
v2: No message from host to GuC uses more than 8 registers and
the GuC FW itself uses
GuC is disabled by default. Enable it.
Signed-off-by: Michal Wajdeczko
---
drivers/gpu/drm/i915/i915_params.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_params.h
b/drivers/gpu/drm/i915/i915_params.h
index 7e56c51..c681537 100644
---
Propagate the timeout on transferring the fw back to the caller where it
may act upon it, usually by restarting the xfer before failing.
v2: Simplify the wait to only wait upon the guc signaling completion,
with an assertion that the fw xfer must have completed for it to be
ready!
Testcase:
On 18/10/18 12:55, Chris Wilson wrote:
Propagate the timeout on transferring the fw back to the caller where it
may act upon it, usually by restarting the xfer before failing.
v2: Simplify the wait to only wait upon the guc signaling completion,
with an assertion that the fw xfer must have
From: Ville Syrjälä
The SKL+ NV12 src width alignment w/a is still living in an odd place.
Everything else was already relocated closer to the main plane check
function. Move this workaround as well.
As a bonus we avoid the funky rotated vs. not mess with the src
coordinates as this now gets
From: Ville Syrjälä
Let's run through the entire plane check even when the plane
is invisible due to zero constant alpha. This makes for more
consistent behaviour since we check the src/dst coordinates,
stride etc. against the hardware limits.
Signed-off-by: Ville Syrjälä
---
== Series Details ==
Series: series starting with [v3,1/2] drm/i915/guc: Limit number of scratch
registers used for H2G
URL : https://patchwork.freedesktop.org/series/51206/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_5010 -> Patchwork_10505 =
== Summary - FAILURE ==
On Thu, Oct 18, 2018 at 6:57 PM Joonas Lahtinen
wrote:
>
> Hi Dave,
>
> Here comes the final set of fixes under -next-fixes umbrella.
> Next one will be then from -fixes, assuming a release next Sun.
>
> Fixes for bunch of display related issues reported by users, then the
> MST fixes that were
== Series Details ==
Series: drm/i915/guc: Propagate the fw xfer timeout (rev3)
URL : https://patchwork.freedesktop.org/series/51140/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5010 -> Patchwork_10507 =
== Summary - SUCCESS ==
No regressions found.
External URL:
On 17/10/18 11:42, Lis, Tomasz wrote:
On 2018-10-12 20:25, Daniele Ceraolo Spurio wrote:
With the new interface, GuC now requires every lrc to be registered in
one of the stage descriptors, which have been re-designed so that each
descriptor can store up to 64 lrc per class (i.e. equal to
== Series Details ==
Series: drm/i915/guc: Propagate the fw xfer timeout (rev2)
URL : https://patchwork.freedesktop.org/series/51140/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_5010 -> Patchwork_10506 =
== Summary - FAILURE ==
Serious unknown changes coming with
== Series Details ==
Series: series starting with [1/2] drm/i915: Relocate SKL+ NV12 src width w/a
URL : https://patchwork.freedesktop.org/series/51215/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5010 -> Patchwork_10508 =
== Summary - WARNING ==
Minor unknown changes
On Thu, 18 Oct 2018 20:18:53 +0200, Daniele Ceraolo Spurio
wrote:
On 18/10/18 02:13, Chris Wilson wrote:
Quoting Michal Wajdeczko (2018-10-18 00:22:43)
On Thu, 18 Oct 2018 01:09:19 +0200, Daniele Ceraolo Spurio
wrote:
On 17/10/18 13:29, Chris Wilson wrote:
Propagate the timeout on
On 18/10/18 11:30, Michal Wajdeczko wrote:
We wrongly assumed that GuC is only using last scratch register
for G2H messages, but in fact it is also using register [14] to
report sleep state status. Remove that register from our H2G
send registers pool.
v2: No message from host to GuC uses
Quoting Michal Wajdeczko (2018-10-18 19:27:20)
> On Thu, 18 Oct 2018 20:18:53 +0200, Daniele Ceraolo Spurio
> wrote:
>
> >
> >
> > On 18/10/18 02:13, Chris Wilson wrote:
> >> Quoting Michal Wajdeczko (2018-10-18 00:22:43)
> >>> On Thu, 18 Oct 2018 01:09:19 +0200, Daniele Ceraolo Spurio
> >>>
== Series Details ==
Series: drm/i915: Ensure proper HDA suspend/resume ordering with a device link
URL : https://patchwork.freedesktop.org/series/51189/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_5008_full -> Patchwork_10504_full =
== Summary - FAILURE ==
Serious
Quoting Chris Wilson (2018-10-16 19:31:06)
> Fwiw, the shmem_unlock_mapping() call feels quite expensive, almost
> nullifying the advantage gained from not walking the lists in reclaim.
> I'll have better numbers in a couple of days.
Using a test ("igt/benchmarks/gem_syslatency -t 120 -b -m" on
== Series Details ==
Series: drm/i915: Add ppgtt to GVT GEM context
URL : https://patchwork.freedesktop.org/series/51156/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5000 -> Patchwork_10500 =
== Summary - SUCCESS ==
No regressions found.
External URL:
On Thu 18-10-18 07:56:45, Chris Wilson wrote:
> Quoting Chris Wilson (2018-10-16 19:31:06)
> > Fwiw, the shmem_unlock_mapping() call feels quite expensive, almost
> > nullifying the advantage gained from not walking the lists in reclaim.
> > I'll have better numbers in a couple of days.
>
> Using
On 12/10/2018 08:16, Patchwork wrote:
== Series Details ==
Series: drm/i915: GEM_WARN_ON considered harmful (rev2)
URL : https://patchwork.freedesktop.org/series/49340/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4976 -> Patchwork_10434 =
== Summary - SUCCESS ==
Use single exit point to drop rpm wakeref in case of an error.
Fixes: 9d3eb2c33f03 ("drm/i915: Hold rpm wakeref for
debugfs/i915_drop_caches_set")
Signed-off-by: Joonas Lahtinen
Cc: Chris Wilson
Cc: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_debugfs.c | 3 ++-
1 file changed, 2
Quoting Michal Wajdeczko (2018-10-17 20:52:45)
> In response for I915_PARAM_HAS_HUC we are returning value that
> indicates if HuC firmware was loaded and verified. However, our
> previously used positive value was based on specific register bit
> which is about to change on future platform. Let's
== Series Details ==
Series: drm/i915: Add ppgtt to GVT GEM context
URL : https://patchwork.freedesktop.org/series/51156/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5000_full -> Patchwork_10500_full =
== Summary - SUCCESS ==
No regressions found.
== Known issues
On Fri, Mar 16, 2018 at 12:26 AM Byungchul Park wrote:
>
> On 3/15/2018 9:41 PM, Peter Zijlstra wrote:
> > On Thu, Mar 15, 2018 at 11:31:57AM +0100, Daniel Vetter wrote:
> >> Is there any progress on getting cross-release enabled again?
> >
> > Not yet, I'm still fighting the meltdown/spectre
Quoting Michal Wajdeczko (2018-10-18 00:22:43)
> On Thu, 18 Oct 2018 01:09:19 +0200, Daniele Ceraolo Spurio
> wrote:
>
> >
> >
> > On 17/10/18 13:29, Chris Wilson wrote:
> >> Propagate the timeout on transferring the fw back to the caller where it
> >> may act upon it, usually by restarting
1 - 100 of 134 matches
Mail list logo
