On Wed, Jun 10, 2020 at 6:21 AM Rob Herring wrote:
>
> On Sat, May 30, 2020 at 04:10:02PM +0800, Yong Wu wrote:
> > From: Maoguang Meng
> >
> > Update binding document since the avc and vp8 hardware encoder in
> > mt8173 are now separated. Separate "mediatek,mt8173-vcodec-enc" to
> >
On 01/16/2015 08:18 AM, Laurent Pinchart wrote:
On Thursday 15 January 2015 11:12:17 Will Deacon wrote:
On Thu, Jan 15, 2015 at 08:28:44AM +, Thierry Reding wrote:
On Wed, Jan 14, 2015 at 10:46:10AM +, Will Deacon wrote:
On Wed, Jan 14, 2015 at 09:00:24AM +, Alexandre Courbot
On 12/02/2014 01:57 AM, Will Deacon wrote:
This patch plumbs the existing ARM IOMMU DMA infrastructure (which isn't
actually called outside of a few drivers) into arch_setup_dma_ops, so
that we can use IOMMUs for DMA transfers in a more generic fashion.
Since this significantly complicates the
Hi Mark,
On Mon, Dec 8, 2014 at 3:20 PM, Mark Zhang ma...@nvidia.com wrote:
This patch adds suspend/resume support for NVIDIA SMMU.
This patch is created on top of Thierry Reding's patch set:
[PATCH v7 00/12] NVIDIA Tegra memory controller and IOMMU support
You should have this comment
to merge them all via
the Tegra tree. For that I'll need Acked-bys from Mike, Russell and Joerg
on patches 1, 2 and 3, and 5, respectively.
FWIW,
Tested-by: Alexandre Courbot acour...@nvidia.com
Works nicely with both the display and GPU clients, which allows us to
remove the need for CMA
On Mon, Nov 3, 2014 at 5:22 PM, Thierry Reding thierry.red...@gmail.com wrote:
On Sat, Nov 01, 2014 at 02:38:26PM +0900, Alexandre Courbot wrote:
On Fri, Oct 31, 2014 at 10:27 PM, Thierry Reding
thierry.red...@gmail.com wrote:
On Thu, Oct 30, 2014 at 04:08:41PM +0100, Thierry Reding wrote
On Fri, Oct 31, 2014 at 10:27 PM, Thierry Reding
thierry.red...@gmail.com wrote:
On Thu, Oct 30, 2014 at 04:08:41PM +0100, Thierry Reding wrote:
On Wed, Oct 15, 2014 at 03:09:30PM -0700, Olof Johansson wrote:
Hi,
Oh, a few more comments:
On Mon, Oct 13, 2014 at 3:33 AM, Thierry Reding
diff --git a/drivers/memory/tegra/tegra124-mc.c
b/drivers/memory/tegra/tegra124-mc.c
...
+static const struct tegra_smmu_swgroup tegra124_swgroups[] = {
+ { .swgroup = TEGRA_SWGROUP_DC,.reg = 0x240 },
+ { .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 },
+ {
On 10/30/2014 08:04 PM, Terje Bergström wrote:
On 30.10.2014 12:22, Alexandre Courbot wrote:
So should I understand that the GPU group is for addresses without bit
34 set (hence forcibly disabled) while GPUB is used when that bit is
set? Or is it something else?
That's exactly correct
On Thu, Oct 30, 2014 at 7:18 PM, Terje Bergström tbergst...@nvidia.com
wrote:
On 30.10.2014 12:03, Alexandre Courbot wrote:
I had to change the .reg of TEGRA_SWGROUP_GPU to 0xaac to get the IOMMU
to work with GK20A. The reason is still not completely clear to me, but
if you look at the TRM
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