We are about to use iommu_sva_alloc/free_pasid() helpers in iommu core.
That means the pasid life cycle will be managed by iommu core. Use a
local array to save the per pasid private data instead of attaching it
the real pasid.
Signed-off-by: Lu Baolu
---
drivers/iommu/intel/svm.c | 62
pasid.
PATCH[4-6]: Use the generic sva io page fault handler iommu_queue_iopf.
PATCH[7-11]: Add ftrace and debugfs support for io page fault handling.
Please help to review.
Best regards,
baolu
Lu Baolu (11):
iommu/vt-d: Add pasid private data helpers
iommu/vt-d: Use iommu_sva_alloc(free)_pasid
From: Dan Carpenter
In current kernels small allocations never fail, but checking for
allocation failure is the correct thing to do.
Fixes: 18abda7a2d55 ("iommu/vt-d: Fix general protection fault in
aux_detach_device()")
Signed-off-by: Dan Carpenter
Acked-by: Lu Baolu
L
table entry of RID2PASID so that requests requesting the supervisor
privilege are blocked and treated as DMA remapping faults.
Fixes: b802d070a52a1 ("iommu/vt-d: Use iova over first level")
Suggested-by: Jacob Pan
Signed-off-by: Lu Baolu
Link:
https://lore.kernel.org/r/20210512064426
Hi Joerg,
Two small fixes are queued in this series. It includes:
- Use user privilege for RID2PASID translation
- Check memory allocation return value
Please consider them for v5.13.
Best regards,
Lu Baolu
Dan Carpenter (1):
iommu/vt-d: Check for allocation failure in aux_detach_device
attached to a nested mode iommu_domain should
support nested capabilility.
Signed-off-by: Lu Baolu
---
drivers/iommu/intel/iommu.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
Change log:
v1->v2:
- Remove unnecessary global capability check
diff --git a/drivers/iommu/in
0x as PASID for DMA requests w/o PASID.
This is confusing. Tweak this by adding "NO_PASID" explicitly.
Reviewed-by: Ashok Raj
Signed-off-by: Lu Baolu
---
drivers/iommu/intel/dmar.c | 23 +++
1 file changed, 15 insertions(+), 8 deletions(-)
Change log:
v1->v
On 5/13/21 6:58 PM, Keqian Zhu wrote:
On 2021/5/12 19:36, Lu Baolu wrote:
Hi keqian,
On 5/12/21 4:44 PM, Keqian Zhu wrote:
On 2021/5/12 11:20, Lu Baolu wrote:
On 5/11/21 3:40 PM, Keqian Zhu wrote:
For upper layers, before starting page tracking, they check the
dirty_page_trackable
On 5/13/21 12:01 AM, Tianyu Lan wrote:
Hi Christoph and Konrad:
Current Swiotlb bounce buffer uses a pool for all devices. There
is a high overhead to get or free bounce buffer during performance test.
Swiotlb code now use a global spin lock to protect bounce buffer data.
Several device
On 5/13/21 12:56 AM, Raj, Ashok wrote:
On Wed, May 12, 2021 at 02:50:12PM +0800, Lu Baolu wrote:
The Intel IOMMU driver reports the DMA fault reason in a decimal number
while the VT-d specification uses a hexadecimal one. It's inconvenient
that users need to covert them everytime before
On 5/13/21 10:26 AM, Tian, Kevin wrote:
From: Lu Baolu
Sent: Wednesday, May 12, 2021 7:31 PM
Hi Kevin,
On 5/12/21 4:30 PM, Tian, Kevin wrote:
From: Lu Baolu
Sent: Wednesday, May 12, 2021 3:04 PM
Current VT-d implementation supports nested translation only if all
underlying IOMMUs support
Hi Ashok,
On 5/13/21 1:03 AM, Raj, Ashok wrote:
On Wed, May 12, 2021 at 02:44:26PM +0800, Lu Baolu wrote:
When first-level page tables are used for IOVA translation, we use user
privilege by setting U/S bit in the page table entry. This is to make it
consistent with the second level
Hi keqian,
On 5/12/21 4:44 PM, Keqian Zhu wrote:
On 2021/5/12 11:20, Lu Baolu wrote:
On 5/11/21 3:40 PM, Keqian Zhu wrote:
For upper layers, before starting page tracking, they check the
dirty_page_trackable attribution of the domain and start it only it's
capable. Once the page tracking
Hi Kevin,
On 5/12/21 4:30 PM, Tian, Kevin wrote:
From: Lu Baolu
Sent: Wednesday, May 12, 2021 3:04 PM
Current VT-d implementation supports nested translation only if all
underlying IOMMUs support the nested capability. This is unnecessary
as the upper layer is allowed to create different
k_phys, >subdevices);
Thank you!
Acked-by: Lu Baolu
Best regards,
baolu
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attached to a nested mode iommu_domain should
support nested capabilility.
Signed-off-by: Lu Baolu
---
drivers/iommu/intel/iommu.c | 21 +++--
1 file changed, 19 insertions(+), 2 deletions(-)
diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c
index
The Intel VT-d implementation supports device TLB management. Select
PCI_ATS explicitly so that the pci_ats helpers are always available.
Signed-off-by: Lu Baolu
---
drivers/iommu/intel/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/iommu/intel/Kconfig b/drivers/iommu/intel
0x as PASID for DMA requests w/o PASID.
This is confusing. Tweak this by adding "w/o PASID" explicitly.
Signed-off-by: Lu Baolu
---
drivers/iommu/intel/dmar.c | 22 ++
1 file changed, 14 insertions(+), 8 deletions(-)
diff --git a/drivers/iommu/intel/dmar.c b/dri
table entry of RID2PASID so that requests requesting the supervisor
privilege are blocked and treated as DMA remapping faults.
Suggested-by: Jacob Pan
Fixes: b802d070a52a1 ("iommu/vt-d: Use iova over first level")
Signed-off-by: Lu Baolu
---
drivers/iommu/intel/iommu.c | 7 +--
dri
On 5/11/21 3:40 PM, Keqian Zhu wrote:
For upper layers, before starting page tracking, they check the
dirty_page_trackable attribution of the domain and start it only it's
capable. Once the page tracking is switched on the vendor iommu driver
(or iommu core) should block further device
Hi Jason,
On 4/7/21 4:00 AM, Jason Gunthorpe wrote:
On Mon, Mar 25, 2019 at 09:30:34AM +0800, Lu Baolu wrote:
A parent device might create different types of mediated
devices. For example, a mediated device could be created
by the parent device with full isolation and protection
provided
Hi Keqian,
On 5/10/21 7:07 PM, Keqian Zhu wrote:
I suppose this interface is to ask the vendor IOMMU driver to check
whether each device/iommu in the domain supports dirty bit tracking.
But what will happen if new devices with different tracking capability
are added afterward?
Yep, this is
On 5/8/21 3:31 PM, Tian, Kevin wrote:
From: Alex Williamson
Sent: Saturday, May 8, 2021 1:06 AM
Those are the main ones I can think of. It is nice to have a simple
map/unmap interface, I'd hope that a new /dev/ioasid interface wouldn't
raise the barrier to entry too high, but the user needs
Hi Keqian,
On 5/8/21 3:35 PM, Keqian Zhu wrote:
Hi Baolu,
On 2021/5/8 11:46, Lu Baolu wrote:
Hi Keqian,
On 5/7/21 6:21 PM, Keqian Zhu wrote:
Some types of IOMMU are capable of tracking DMA dirty log, such as
ARM SMMU with HTTU or Intel IOMMU with SLADE. This introduces the
dirty log
Hi Keqian,
On 5/7/21 6:21 PM, Keqian Zhu wrote:
Some types of IOMMU are capable of tracking DMA dirty log, such as
ARM SMMU with HTTU or Intel IOMMU with SLADE. This introduces the
dirty log tracking framework in the IOMMU base layer.
Four new essential interfaces are added, and we maintaince
r
Acked-by: Lu Baolu
P.S. Next time when you submit a new version, please use a version tag.
Best regards,
baolu
---
drivers/iommu/intel/dmar.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/iommu/intel/dmar.c b/drivers/iommu/intel/dmar.c
index d5c51b5c20af..c2
Hi Rolf,
On 4/21/21 11:12 PM, Rolf Eike Beer wrote:
Signed-off-by: Rolf Eike Beer
Thanks for the patch!
Can you please adjust the subject to "iommu/vt-d: Fix sysfs leak in
alloc_domain()"? It's not only for hotplug path.
Please also add commit message.
Add below Fixes tag as well:
Fixes:
On 4/20/21 3:32 PM, Keqian Zhu wrote:
Hi Baolu,
Cheers for the your quick reply.
On 2021/4/20 10:09, Lu Baolu wrote:
Hi Keqian,
On 4/20/21 9:25 AM, Keqian Zhu wrote:
Hi Baolu,
On 2021/4/19 21:33, Lu Baolu wrote:
Hi Keqian,
On 2021/4/19 17:32, Keqian Zhu wrote:
+EXPORT_SYMBOL_GPL
Hi Keqian,
On 4/20/21 9:25 AM, Keqian Zhu wrote:
Hi Baolu,
On 2021/4/19 21:33, Lu Baolu wrote:
Hi Keqian,
On 2021/4/19 17:32, Keqian Zhu wrote:
+EXPORT_SYMBOL_GPL(iommu_split_block);
Do you really have any consumers of this interface other than the dirty
bit tracking? If not, I don't
Hi Keqian,
On 2021/4/19 17:32, Keqian Zhu wrote:
+EXPORT_SYMBOL_GPL(iommu_split_block);
Do you really have any consumers of this interface other than the dirty
bit tracking? If not, I don't suggest to make this as a generic IOMMU
interface.
There is an implicit requirement for such
Hi Bingbu,
On 4/19/21 12:57 PM, Bingbu Cao wrote:
Intel IPU(Image Processing Unit) has its own (IO)MMU hardware,
The IPU driver allocates its own page table that is not mapped
via the DMA, and thus the Intel IOMMU driver blocks access giving
this error:
DMAR: DRHD: handling fault status reg 3
Hi Keqian,
On 4/16/21 5:07 PM, Keqian Zhu wrote:
I am worrying about having two sets of APIs for single purpose. From
vendor iommu driver's point of view, this feature is per device. Hence,
it still needs to do the same thing.
Yes, we can unify the granule of feature reporting and status
Hi,
On 2021/4/15 15:43, Keqian Zhu wrote:
design it as not switchable. I will modify the commit message of patch#12,
thanks!
I am not sure that I fully get your point. But I can't see any gaps of
using iommu_dev_enable/disable_feature() to switch dirty log on and off.
Probably I missed
On 4/15/21 2:18 PM, Keqian Zhu wrote:
Hi Baolu,
Thanks for the review!
On 2021/4/14 15:00, Lu Baolu wrote:
Hi Keqian,
On 4/13/21 4:54 PM, Keqian Zhu wrote:
Some types of IOMMU are capable of tracking DMA dirty log, such as
ARM SMMU with HTTU or Intel IOMMU with SLADE. This introduces
: 0x1a30a72003
2. __domain_mapping
dma_pte_free_pagetable
Set the PDE entry to ZERO
Set the PDE entry to 0x21d200883
So we must flush the cache after the entry switch to ZERO
to avoid the obsolete info be preserved.
Cc: David Woodhouse
Cc: Lu Baolu
Cc: Nadav Amit
Cc: Alex
Hi Jason,
On 4/14/21 7:26 PM, Jason Gunthorpe wrote:
On Wed, Apr 14, 2021 at 02:22:09PM +0800, Lu Baolu wrote:
I still worry about supervisor pasid allocation.
If we use iommu_sva_alloc_pasid() to allocate a supervisor pasid, which
mm should the pasid be set? I've ever thought about passing
On 4/13/21 4:54 PM, Keqian Zhu wrote:
Block(largepage) mapping is not a proper granule for dirty log tracking.
Take an extreme example, if DMA writes one byte, under 1G mapping, the
dirty amount reported is 1G, but under 4K mapping, the dirty amount is
just 4K.
This adds a new interface named
Hi Keqian,
On 4/13/21 4:54 PM, Keqian Zhu wrote:
Some types of IOMMU are capable of tracking DMA dirty log, such as
ARM SMMU with HTTU or Intel IOMMU with SLADE. This introduces the
dirty log tracking framework in the IOMMU base layer.
Three new essential interfaces are added, and we
Hi Jacob,
On 4/14/21 8:09 AM, Jacob Pan wrote:
Hi Jean,
On Fri, 9 Apr 2021 11:03:05 -0700, Jacob Pan
wrote:
problems:
* We don't have a use-case for binding the mm of a remote process (and
it's supposedly difficult for device drivers to do it securely). So
OK, we remove the mm argument
Hi Gustavo,
On 4/14/21 3:54 AM, Gustavo A. R. Silva wrote:
Replace call to memcpy() with just a couple of simple assignments in
order to fix the following out-of-bounds warning:
drivers/iommu/intel/svm.c:1198:4: warning: 'memcpy' offset [25, 32] from the
object at 'desc' is out of the bounds
I guess you need to ask Greg KH with this
Cc-ing to sta...@vger.kernel.org.
Best regards,
baolu
On 2021/4/12 3:36, Saeed Mirzamohammadi wrote:
Hi Lu,
Thanks for the review. May I know when do we expect this to be applied
to 5.4?
Thanks,
Saeed
On Apr 7, 2021, at 5:25 PM, Lu Baolu
goto error;
+ return -ENODEV;
if (!dmar_ir_support())
return -ENODEV;
Thanks!
Acked-by: Lu Baolu
Best regards,
baolu
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andy Dunlap
Fixes: f68c7f539b6e9 ("iommu/vt-d: Enable write protect for supervisor SVM")
Signed-off-by: Lu Baolu
---
drivers/iommu/intel/pasid.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/iommu/intel/pasid.c b/drivers/iommu/intel/pasid.c
index 477b2e1d303c..72646bafc52
Hi,
On 2021/4/9 1:08, Jacob Pan wrote:
/**
* iommu_sva_alloc_pasid - Allocate a PASID for the mm
- * @mm: the mm
* @min: minimum PASID value (inclusive)
* @max: maximum PASID value (inclusive)
*
- * Try to allocate a PASID for this mm, or take a reference to the existing one
- *
Hi Jacob,
On 2021/4/9 1:08, Jacob Pan wrote:
The void* drvdata parameter isn't really used in iommu_sva_bind_device()
API, the current IDXD code "borrows" the drvdata for a VT-d private flag
for supervisor SVA usage.
Supervisor/Privileged mode request is a generic feature. It should be
Hi Longpeng,
On 4/8/21 3:37 PM, Longpeng (Mike, Cloud Infrastructure Service Product
Dept.) wrote:
Hi Baolu,
-Original Message-
From: Lu Baolu [mailto:baolu...@linux.intel.com]
Sent: Thursday, April 8, 2021 12:32 PM
To: Longpeng (Mike, Cloud Infrastructure Service Product Dept
Hi Longpeng,
On 4/7/21 2:35 PM, Longpeng (Mike, Cloud Infrastructure Service Product
Dept.) wrote:
Hi Baolu,
-Original Message-
From: Lu Baolu [mailto:baolu...@linux.intel.com]
Sent: Friday, April 2, 2021 12:44 PM
To: Longpeng (Mike, Cloud Infrastructure Service Product Dept
= cap_width;
domain->gaw = guest_width;
adjust_width = guestwidth_to_adjustwidth(guest_width);
agaw = width_to_agaw(adjust_width);
Reviewed-by: Lu Baolu
Best regards,
baolu
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Hi Jason,
On 4/7/21 4:00 AM, Jason Gunthorpe wrote:
On Mon, Mar 25, 2019 at 09:30:34AM +0800, Lu Baolu wrote:
A parent device might create different types of mediated
devices. For example, a mediated device could be created
by the parent device with full isolation and protection
provided
Hi Saeed,
On 4/7/21 12:35 AM, Saeed Mirzamohammadi wrote:
The IOMMU driver calculates the guest addressability for a DMA request
based on the value of the mgaw reported from the IOMMU. However, this
is a fused value and as mentioned in the spec, the guest width
should be calculated based on the
,
size_t size, struct iommu_iotlb_gather *iotlb_gather);
size_t (*unmap_pages)(struct iommu_domain *domain, unsigned long iova,
This looks good to me.
Acked-by: Lu Baolu
Best regards,
baolu
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iommu
)(struct iommu_domain *domain);
void (*iotlb_sync_map)(struct iommu_domain *domain, unsigned long iova,
size_t size);
This looks good to me.
Acked-by: Lu Baolu
Best regards,
baolu
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On 3/20/21 10:54 AM, Lu Baolu wrote:
When first-level page tables are used for IOVA translation, we use user
privilege by setting U/S bit in the page table entry. This is to make it
consistent with the second level translation, where the U/S enforcement
is not available. Clear the SRE
Hi,
On 4/2/21 9:34 AM, Isaac J. Manjarres wrote:
static size_t __iommu_unmap(struct iommu_domain *domain,
unsigned long iova, size_t size,
struct iommu_iotlb_gather *iotlb_gather)
@@ -2476,7 +2519,7 @@ static size_t __iommu_unmap(struct
Hi Isaac,
On 4/3/21 1:25 AM, isa...@codeaurora.org wrote:
On 2021-03-30 22:39, Lu Baolu wrote:
On 3/31/21 1:36 PM, isa...@codeaurora.org wrote:
On 2021-03-30 21:47, Lu Baolu wrote:
On 3/31/21 11:00 AM, Isaac J. Manjarres wrote:
Add a callback for IOMMU drivers to provide a path
On 4/2/21 11:41 AM, Longpeng (Mike, Cloud Infrastructure Service Product
Dept.) wrote:
Hi Baolu,
在 2021/4/2 11:06, Lu Baolu 写道:
Hi Longpeng,
On 4/1/21 3:18 PM, Longpeng(Mike) wrote:
The translation caches may preserve obsolete data when the
mapping size is changed, suppose the following
Hi Longpeng,
On 4/1/21 3:18 PM, Longpeng(Mike) wrote:
diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c
index ee09323..cbcb434 100644
--- a/drivers/iommu/intel/iommu.c
+++ b/drivers/iommu/intel/iommu.c
@@ -2342,9 +2342,20 @@ static inline int hardware_largepage_caps(struct
: 0x1a30a72003
2. __domain_mapping
dma_pte_free_pagetable
Set the PDE entry to ZERO
Set the PDE entry to 0x21d200883
So we must flush the cache after the entry switch to ZERO
to avoid the obsolete info be preserved.
Cc: David Woodhouse
Cc: Lu Baolu
Cc: Nadav Amit
Cc: Alex
On 3/31/21 1:36 PM, isa...@codeaurora.org wrote:
On 2021-03-30 21:47, Lu Baolu wrote:
On 3/31/21 11:00 AM, Isaac J. Manjarres wrote:
Add a callback for IOMMU drivers to provide a path for the
IOMMU framework to call into an IOMMU driver, which can call
into the io-pgtable code, to unmap
On 3/31/21 11:00 AM, Isaac J. Manjarres wrote:
Add a callback for IOMMU drivers to provide a path for the
IOMMU framework to call into an IOMMU driver, which can call
into the io-pgtable code, to unmap a virtually contiguous
range of pages of the same size.
For IOMMU drivers that do not specify
Ashok Raj
Signed-off-by: Lu Baolu
---
drivers/iommu/intel/pasid.h | 1 +
drivers/iommu/intel/iommu.c | 11 ++-
drivers/iommu/intel/pasid.c | 16
3 files changed, 27 insertions(+), 1 deletion(-)
diff --git a/drivers/iommu/intel/pasid.h b/drivers/iommu/intel/pasid.h
index 07
Hi Nadav,
On 3/27/21 12:36 PM, Nadav Amit wrote:
On Mar 26, 2021, at 7:31 PM, Lu Baolu wrote:
Hi Nadav,
On 3/19/21 12:46 AM, Nadav Amit wrote:
So here is my guess:
Intel probably used as a basis for the IOTLB an implementation of
some other (regular) TLB design.
Intel SDM says regarding
Hi Nadav,
On 3/19/21 12:46 AM, Nadav Amit wrote:
So here is my guess:
Intel probably used as a basis for the IOTLB an implementation of
some other (regular) TLB design.
Intel SDM says regarding TLBs (4.10.4.2 “Recommended Invalidation”):
"Software wishing to prevent this uncertainty should
Hi Christoph,
On 3/24/21 1:33 AM, Christoph Hellwig wrote:
On Tue, Mar 23, 2021 at 09:05:58AM +0800, Lu Baolu wrote:
The SVM_FLAG_PRIVATE_PASID has never been referenced in the tree, and
there's no plan to have anything to use it. So cleanup it.
Signed-off-by: Lu Baolu
Looks good
@ -57,7 +57,6 @@ enum cpuhp_state {
CPUHP_PAGE_ALLOC_DEAD,
CPUHP_NET_DEV_DEAD,
CPUHP_PCI_XGENE_DEAD,
- CPUHP_IOMMU_INTEL_DEAD,
CPUHP_IOMMU_IOVA_DEAD,
CPUHP_LUSTRE_CFS_DEAD,
CPUHP_AP_ARM_CACHE_B15_RAC_DEAD,
Reviewed-b
Make some functions static as they are only used inside pasid.c.
Signed-off-by: Lu Baolu
---
drivers/iommu/intel/pasid.c | 4 ++--
drivers/iommu/intel/pasid.h | 2 --
2 files changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/iommu/intel/pasid.c b/drivers/iommu/intel/pasid.c
index
Some functions have been deprecated. Remove the remaining function
delarations.
Signed-off-by: Lu Baolu
---
drivers/iommu/intel/pasid.h | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/iommu/intel/pasid.h b/drivers/iommu/intel/pasid.h
index 444c0bec221a..90a3268d7a77 100644
The SVM_FLAG_PRIVATE_PASID has never been referenced in the tree, and
there's no plan to have anything to use it. So cleanup it.
Signed-off-by: Lu Baolu
---
drivers/iommu/intel/svm.c | 40 ++-
include/linux/intel-svm.h | 16 +++-
2 files changed
The svm_dev_ops has never been referenced in the tree, and there's no
plan to have anything to use it. Remove it to make the code neat.
Signed-off-by: Lu Baolu
---
drivers/iommu/intel/svm.c | 15 +--
include/linux/intel-iommu.h | 3 ---
include/linux/intel-svm.h | 7 ---
3
With commit c588072bba6b5 ("iommu/vt-d: Convert intel iommu driver to
the iommu ops"), the trace events for dma map/unmap have no users any
more. Cleanup them to make the code neat.
Signed-off-by: Lu Baolu
---
include/trace/events/intel_iommu.h | 120 ---
Hi Joerg et al,
This series includes several cleanups in the VT-d driver. Please help to
review.
Best regards,
baolu
Lu Baolu (5):
iommu/vt-d: Remove unused dma map/unmap trace events
iommu/vt-d: Remove svm_dev_ops
iommu/vt-d: Remove SVM_FLAG_PRIVATE_PASID
iommu/vt-d: Remove unused
mu/vt-d: Setup context and enable RID2PASID support")
Signed-off-by: Lu Baolu
---
drivers/iommu/intel/iommu.c | 18 +-
include/linux/intel-iommu.h | 1 +
2 files changed, 10 insertions(+), 9 deletions(-)
diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iom
table entry of RID2PASID so that requests requesting the supervisor
privilege are blocked and treated as DMA remapping faults.
Suggested-by: Jacob Pan
Fixes: b802d070a52a1 ("iommu/vt-d: Use iova over first level")
Signed-off-by: Lu Baolu
---
drivers/iommu/intel/iommu.c | 7 +--
dri
ons on second-level paging entries
- Refine the commit message to make the intention clear.
Lu Baolu (5):
iommu/vt-d: Report the right page fault address
iommu/vt-d: Remove WO permissions on second-level paging entries
iommu/vt-d: Invalidate PASID cache when root/context entry changed
io
-by: Lu Baolu
---
drivers/iommu/intel/pasid.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/iommu/intel/pasid.c b/drivers/iommu/intel/pasid.c
index dd69df5a188a..7a73385edcc0 100644
--- a/drivers/iommu/intel/pasid.c
+++ b/drivers/iommu/intel/pasid.c
@@ -502,6 +502,9 @@ void
/vt-d: Use iova over first level")
Signed-off-by: Lu Baolu
---
drivers/iommu/intel/iommu.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c
index 167219ea8d70..132cbf9f214f 100644
--- a/drivers/iommu/intel/iommu.c
+++
The Address field of the Page Request Descriptor only keeps bit [63:12]
of the offending address. Convert it to a full address before reporting
it to device drivers.
Fixes: eb8d93ea3c1d3 ("iommu/vt-d: Report page request faults for guest SVA")
Signed-off-by: Lu Baolu
---
drivers/i
cleared in prq_event_thread(). This breaks the rule defined
by the VT-d specification. Fix it by moving clearing code up.
Fixes: 5b438f4ba315d ("iommu/vt-d: Support page request in scalable mode")
Cc: Jacob Pan
Reviewed-by: Liu Yi L
Signed-off-by: Lu Baolu
---
drivers/iommu/intel
e pasid_lock with an atomic exchange operation.
Reported-and-tested-by: Dave Jiang
Signed-off-by: Lu Baolu
---
drivers/iommu/intel/pasid.c | 21 +
1 file changed, 13 insertions(+), 8 deletions(-)
Log:
v1->v2:
- v1:
https://lore.kernel.org/linux-iommu/20210317005834
Hi Joerg,
On 3/18/21 6:10 PM, Joerg Roedel wrote:
Hi Baolu,
On Tue, Mar 09, 2021 at 08:46:41AM +0800, Lu Baolu wrote:
The private data field of a page group response descriptor is set then
immediately cleared in prq_event_thread(). Fix this by moving clearing
code up.
Fixes: 5b438f4ba315d
Hi Joerg,
On 3/18/21 6:21 PM, Joerg Roedel wrote:
On Wed, Mar 17, 2021 at 08:58:34AM +0800, Lu Baolu wrote:
The pasid_lock is used to synchronize different threads from modifying a
same pasid directory entry at the same time. It causes below lockdep splat.
[ 83.296538
Hi Joerg,
On 3/18/21 5:12 PM, Joerg Roedel wrote:
Hi,
On Mon, Mar 08, 2021 at 11:47:46AM -0800, Raj, Ashok wrote:
That is the primary motivation, given that we have moved to 1st level for
general IOVA, first level doesn't have a WO mapping. I didn't know enough
about the history to determine
On 3/18/21 4:56 PM, Tian, Kevin wrote:
From: Longpeng (Mike, Cloud Infrastructure Service Product Dept.)
-Original Message-
From: Tian, Kevin [mailto:kevin.t...@intel.com]
Sent: Thursday, March 18, 2021 4:27 PM
To: Longpeng (Mike, Cloud Infrastructure Service Product Dept.)
; Nadav
Hi Nadav,
On 3/18/21 2:12 AM, Nadav Amit wrote:
On Mar 17, 2021, at 2:35 AM, Longpeng (Mike, Cloud Infrastructure Service Product
Dept.) wrote:
Hi Nadav,
-Original Message-
From: Nadav Amit [mailto:nadav.a...@gmail.com]
reproduce the problem with high probability (~50%).
I
Hi Alex,
On 3/17/21 11:18 PM, Alex Williamson wrote:
{MAP, 0x0, 0xc000}, - (b)
use GDB to pause at here, and then DMA read IOVA=0,
IOVA 0 seems to be a special one. Have you verified with other addresses
than IOVA 0?
It is???
When the invalidation queue errors are encountered, dump the information
logged by the VT-d hardware together with the pending queue invalidation
descriptors.
Signed-off-by: Ashok Raj
Tested-by: Guo Kaijie
Signed-off-by: Lu Baolu
---
drivers/iommu/intel/dmar.c | 68
Hi Longpeng,
On 3/17/21 11:16 AM, Longpeng (Mike, Cloud Infrastructure Service
Product Dept.) wrote:
Hi guys,
We find the Intel iommu cache (i.e. iotlb) maybe works wrong in a special
situation, it would cause DMA fails or get wrong data.
The reproducer (based on Alex's vfio testsuite[1]) is
e pasid_lock with an atomic exchange operation.
Reported-and-tested-by: Dave Jiang
Signed-off-by: Lu Baolu
---
drivers/iommu/intel/pasid.c | 14 ++
1 file changed, 6 insertions(+), 8 deletions(-)
diff --git a/drivers/iommu/intel/pasid.c b/drivers/iommu/intel/pasid.c
index
)
return -EINVAL;
+ if (!info->pasid_enabled || !info->pri_enabled || !info->ats_enabled)
+ return -EINVAL;
+
if (info->iommu->flags & VTD_FLAG_SVM_CAPABLE)
return 0;
}
Thanks for the p
Hi Shenming,
On 3/9/21 2:22 PM, Shenming Lu wrote:
This patch follows the discussion here:
https://lore.kernel.org/linux-acpi/YAaxjmJW+ZMvrhac@myrica/
In order to support more scenarios of using IOPF (mainly consider
the nested extension), besides keeping IOMMU_DEV_FEAT_IOPF as a
general
The private data field of a page group response descriptor is set then
immediately cleared in prq_event_thread(). Fix this by moving clearing
code up.
Fixes: 5b438f4ba315d ("iommu/vt-d: Support page request in scalable mode")
Cc: Jacob Pan
Reviewed-by: Liu Yi L
Signed-off-by
Hi Joerg,
On 3/4/21 8:26 PM, Joerg Roedel wrote:
On Thu, Feb 25, 2021 at 02:26:51PM +0800, Lu Baolu wrote:
When the first level page table is used for IOVA translation, it only
supports Read-Only and Read-Write permissions. The Write-Only permission
is not supported as the PRESENT bit
-git a/include/linux/dma-iommu.h b/include/linux/dma-iommu.h
index 706b68d1359b..13d1f4c14d7b 100644
--- a/include/linux/dma-iommu.h
+++ b/include/linux/dma-iommu.h
@@ -40,6 +40,8 @@ void iommu_dma_get_resv_regions(struct device *dev, struct
list_head *list);
void iommu_dma_free_cpu_cached_iovas(unsigned int cpu
add_device() and
iommu_register_device_fault_handler().
Reviewed-by: Eric Auger
Reviewed-by: Jonathan Cameron
Signed-off-by: Jean-Philippe Brucker
I have tested this framework with the Intel VT-d implementation. It
works as expected. Hence,
Reviewed-by: Lu Baolu
Tested-by: Lu Baolu
One possible future op
-Hartman
Cc: Joerg Roedel
Cc: Lu Baolu
Cc: Will Deacon
Cc: Zhangfei Gao
Cc: Zhou Wang
---
include/linux/iommu.h | 20 +---
1 file changed, 17 insertions(+), 3 deletions(-)
diff --git a/include/linux/iommu.h b/include/linux/iommu.h
index 16ce75693d83..45c4eb372f56 100644
ID_WPE (1 << 6) /* Write protect enable */
+#define IOMMU_SVA_VTD_GPASID_LAST (1 << 7)
__u64 flags;
__u32 pat;
__u32 emt;
Acked-by: Lu Baolu
Best regards,
baolu
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return -EINVAL;
}
pasid_set_sre(pte);
+ if (pasid_enable_wpe(pte))
+ return -EINVAL;
+
}
if (flags & PASID_FLAG_FL5LP) {
Acked-by: Lu Baolu
Best regards,
baolu
__
((e) >> 8) & 0xf)
#define VCMD_CMD_OPERAND(e) ((e) << 8)
/*
Thanks a lot for catching this.
Acked-by: Lu Baolu
Best regards,
baolu
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-by: Lu Baolu
---
drivers/iommu/intel/pasid.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/iommu/intel/pasid.c b/drivers/iommu/intel/pasid.c
index 07531e5edfa2..9fb3d3e80408 100644
--- a/drivers/iommu/intel/pasid.c
+++ b/drivers/iommu/intel/pasid.c
@@ -493,6 +493,9 @@ void
table entry of RID2PASID so that requests requesting the supervisor
privilege are blocked and treated as DMA remapping faults.
Suggested-by: Jacob Pan
Fixes: b802d070a52a1 ("iommu/vt-d: Use iova over first level")
Signed-off-by: Lu Baolu
---
drivers/iommu/intel/iommu.c | 7 +--
dri
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