Tegra194 SMMU driver supports Dual ARM SMMU configuration
supported in Tegra194 SOC.
The IOVA accesses from HW devices are interleaved across two
ARM SMMU devices.
Signed-off-by: Krishna Reddy
---
drivers/iommu/Makefile| 1 +
drivers/iommu/tegra194-smmu.c | 201
Prepare fault handling, probe and tlb sync functions to allow sharing
code between ARM SMMU driver and Tegra194 SMMU driver.
Signed-off-by: Krishna Reddy
---
drivers/iommu/arm-smmu-common.c | 53 +++--
drivers/iommu/arm-smmu.c| 42
Rearrange arm-smmu.c code into arm-smmu-common.h, arm-smmu-common.c
and arm-smmu.c.
This patch rearranges the arm-smmu.c code to allow sharing the ARM SMMU
driver code with dual ARM SMMU based Tegra194 SMMU driver.
Signed-off-by: Krishna Reddy
---
drivers/iommu/arm-smmu-common.c | 1922
d transparently
handles programming of two SMMU instances.
The third SMMU instance would use the existing ARM SMMU driver.
Krishna Reddy (3):
iommu/arm-smmu: rearrange arm-smmu.c code
iommu/arm-smmu: Prepare fault, probe, sync functions for sharing code
iommu/tegra194_smmu: Add Tegra194 SMMU d
d transparently
handles programming of two SMMU instances.
The third SMMU instance would use the existing ARM SMMU driver.
Changes in v2:
* Added CONFIG_ARM_SMMU_TEGRA to protect Tegra194 SMMU driver compilation
* Enabled CONFIG_ARM_SMMU_TEGRA in defconfig
* Added SMMU nodes in Tegra194 device tree
Prepare fault handling, probe and tlb sync functions to allow sharing
code between ARM SMMU driver and Tegra194 SMMU driver.
Signed-off-by: Krishna Reddy
---
drivers/iommu/arm-smmu-common.c | 53 +++--
drivers/iommu/arm-smmu.c| 42
Rearrange arm-smmu.c code into arm-smmu-common.h, arm-smmu-common.c
and arm-smmu.c.
This patch rearranges the arm-smmu.c code to allow sharing the ARM SMMU
driver code with dual ARM SMMU based Tegra194 SMMU driver.
Signed-off-by: Krishna Reddy
---
drivers/iommu/arm-smmu-common.c | 1922
Tegra194 SMMU driver supports Dual ARM SMMU configuration
supported in Tegra194 SOC.
The IOVA accesses from HW devices are interleaved across two
ARM SMMU devices.
Signed-off-by: Krishna Reddy
---
drivers/iommu/Kconfig | 10 +++
drivers/iommu/Makefile| 1 +
drivers/iommu
Add SMMU nodes and dma-ranges to Tegra194 device tree.
Tegra194 has three ARM SMMU Instances. Two of them are used
together to access IOVA interleaved. The third one is used
as regular ARM SMMU.
Signed-off-by: Krishna Reddy
---
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 148
Enabling CONFIG_ARM_SMMU_TEGRA that is used
by Tegra194 SOC.
Signed-off-by: Krishna Reddy
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 4b38444..d875f64 100644
--- a/arch/arm64/configs
Hi Will,
Could you provide feedback on this V2 patch set? Your early feedback and
direction on how to Tegra194 SMMU driver into upstream would be highly
appreciated.
Thanks,
-KR
-Original Message-
From: Krishna Reddy
Sent: Wednesday, October 31, 2018 4:49 PM
To: will.dea...@arm.com
Hi Olof,
Thanks for the comments!
>>Based on what I can see, it seems that you're trying to describe two
pieces of hardware with only one device in the DT. That seems like an
odd choice.
T194 SOC HW is designed to use Two ARM SMMU's together like one SMMU.
The IOVA accesses from the HW controlle
evice tree
Changes in v3:
* Created library for ARM SMMU based on arm-smmu.c
* Added support to program multiple ARM SMMU instances identically
* Updated arm-smmu.c/tegra194-smmu.c to use ARM SMMU library functions
Krishna Reddy (6):
iommu/arm-smmu: create library for ARM SMMU
iommu/arm-smmu: Add
Tegra194 SMMU driver supports Dual ARM SMMU configuration
necessary for Tegra194 SOC.
The IOVA accesses from HW devices are interleaved across two
ARM SMMU devices transparently.
Signed-off-by: Krishna Reddy
---
drivers/iommu/Kconfig | 11 ++
drivers/iommu/Makefile| 1
Add support to program multiple ARM SMMU's identically as one SMMU device.
Tegra194 uses Two ARM SMMU's as one SMMU device and both ARM SMMU's need
to be programmed identically.
Signed-off-by: Krishna Reddy
---
drivers/iommu/lib-arm-smmu.c | 191 +++
Add SMMU nodes and dma-ranges to Tegra194 device tree.
Tegra194 has three ARM SMMU Instances. Two of them are used
together to access IOVA interleaved. The third one is used
as regular ARM SMMU.
Signed-off-by: Krishna Reddy
---
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 148
Create library routines to share ARM SMMU programming
and common IOMMU API implementation for ARM SMMU v1 and v2
based architecture Implementations.
Signed-off-by: Krishna Reddy
---
drivers/iommu/Makefile |1 +
drivers/iommu/lib-arm-smmu.c | 1671
Update ARM SMMU driver to use the ARM SMMU library routines.
Signed-off-by: Krishna Reddy
---
drivers/iommu/arm-smmu.c | 1709 +-
1 file changed, 11 insertions(+), 1698 deletions(-)
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
Enabling CONFIG_ARM_SMMU_TEGRA that is used
by Tegra194 SOC.
Signed-off-by: Krishna Reddy
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 5c2b1f6..e5ea13b 100644
--- a/arch/arm64/configs
Hi Robin,
Thanks for the feedback :)
>The whole point of the library idea was to factor out the code in such a way
>that all the details
>specific to a particular implementation can be kept together. But what this
>patch does is insert
>Tegra194-specific handling all through the 'common' code, w
Changes in v5:
Rebased on top of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu.git
next
v4 - https://lkml.org/lkml/2019/10/30/1054
v3 - https://lkml.org/lkml/2019/10/18/1601
v2 - https://lkml.org/lkml/2019/9/2/980
v1 - https://lkml.org/lkml/2019/8/29/1588
Krishna Reddy (5):
iommu
Add DT node for T194 SMMU to enable SMMU support.
Signed-off-by: Krishna Reddy
---
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 77
1 file changed, 77 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index
Add binding for NVIDIA's Tegra194 Soc SMMU that is based
on ARM MMU-500.
Signed-off-by: Krishna Reddy
---
Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 5 +
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
b/Document
Add global/context fault hooks to allow NVIDIA SMMU implementation
handle faults across multiple SMMUs.
Signed-off-by: Krishna Reddy
---
drivers/iommu/arm-smmu-nvidia.c | 100
drivers/iommu/arm-smmu.c| 11 +++-
drivers/iommu/arm-smmu.h| 3 +
3
NVIDIA's Tegra194 soc uses two ARM MMU-500s together to interleave
IOVA accesses across them.
Add NVIDIA implementation for dual ARM MMU-500s and add new compatible
string for Tegra194 soc.
Signed-off-by: Krishna Reddy
---
MAINTAINERS | 2 +
drivers/iommu/Mak
Enable SMMU translations for SDHCI and EQOS transactions on T194.
Signed-off-by: Krishna Reddy
---
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index
>For the record: I don't think we should apply these because we don't have a
>good way of testing them. We currently have three problems that prevent us
>from enabling SMMU on Tegra194:
Out of three issues pointed here, I see that only issue 2) is a real blocker
for enabling SMMU HW by default
NVIDIA's Tegra194 soc uses two ARM MMU-500s together to interleave
IOVA accesses across them.
Add NVIDIA implementation for dual ARM MMU-500s and add new compatible
string for Tegra194 soc.
Signed-off-by: Krishna Reddy
---
MAINTAINERS | 2 +
drivers/iommu/Mak
Add binding for NVIDIA's Tegra194 Soc SMMU that is based
on ARM MMU-500.
Signed-off-by: Krishna Reddy
---
Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 5 +
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
b/Document
://lkml.org/lkml/2019/10/18/1601
v2 - https://lkml.org/lkml/2019/9/2/980
v1 - https://lkml.org/lkml/2019/8/29/1588
Krishna Reddy (4):
iommu/arm-smmu: add NVIDIA implementation for dual ARM MMU-500 usage
dt-bindings: arm-smmu: Add binding for Tegra194 SMMU
iommu/arm-smmu: Add global/context fault
>> drivers/iommu/arm-smmu-nvidia.c:151:33: sparse: sparse: cast removes
>> address space '' of expression
Reported-by: kbuild test robot
Signed-off-by: Krishna Reddy
---
drivers/iommu/arm-smmu-nvidia.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/
Add global/context fault hooks to allow NVIDIA SMMU implementation
handle faults across multiple SMMUs.
Signed-off-by: Krishna Reddy
---
drivers/iommu/arm-smmu-nvidia.c | 100
drivers/iommu/arm-smmu.c| 11 +++-
drivers/iommu/arm-smmu.h| 3 +
3
> > +struct dma_iommu_mapping *
> > +arm_iommu_create_mapping(struct bus_type *bus, dma_addr_t base, size_t
> > size,
> > +int order)
> > +{
> > + unsigned int count = (size >> PAGE_SHIFT) - order;
> > + unsigned int bitmap_size = BITS_TO_LONGS(count) * sizeof(l
> On Wed, Feb 29, 2012 at 04:04:22PM +0100, Marek Szyprowski wrote:
> > +static int arm_iommu_mmap_attrs(struct device *dev, struct
> vm_area_struct *vma,
> > + void *cpu_addr, dma_addr_t dma_addr, size_t size,
> > + struct dma_attrs *attrs)
> > +{
> > + struct arm_vmr
> > > It should be as follows.
> > > unsigned int count = 1 << get_order(size) - order;
>
> To be precise, as below?
>
> unsigned int count = 1 << (get_order(size) - order);
Minus has more precedence than left shift.
"1 << get_order(size) - order;" is equivalent to 1 << (get_order(size) - order
Hi,
I have found a bug in arm_iommu_map_sg().
> +int arm_iommu_map_sg(struct device *dev, struct scatterlist *sg, int nents,
> + enum dma_data_direction dir, struct dma_attrs *attrs) {
> + struct scatterlist *s = sg, *dma = sg, *start = sg;
> + int i, count = 0;
> + u
ux.org.uk;
> minc...@kernel.org; chunsang.je...@linaro.org; linux-
> ker...@vger.kernel.org; subas...@gmail.com; linaro-mm-...@lists.linaro.org;
> linux...@kvack.org; iommu@lists.linux-foundation.org; Krishna Reddy; linux-
> te...@vger.kernel.org; kyungmin.p...@samsung.com;
> pullip...
> > On Tegra, the following use cases need specific IOVA mapping.
> > 1. Few MMIO blocks need IOVA=PA mapping setup.
>
> In that case, why would we enable the IOMMU for that one device; IOMMU
> disabled means VA==PA, right? Perhaps isolation of the device so it can only
> access certain PA ranges
> > The device(H/W controller) need to access few special memory
> > blocks(IOVA==PA) and DRAM as well.
>
> OK, so only /some/ of the VA space is VA==PA, and some is remapped; that's a
> little different that what you originally implied above.
>
> BTW, which HW module is this; AVP/COP or somethin
tlb_sync hook allows nvidia smmu handle tlb sync
across multiple SMMUs as necessary.
Signed-off-by: Krishna Reddy
---
drivers/iommu/arm-smmu-nvidia.c | 32
drivers/iommu/arm-smmu.c| 8 +---
drivers/iommu/arm-smmu.h| 4
3 files changed
Add DT node for T194 SMMU to enable SMMU support.
Signed-off-by: Krishna Reddy
---
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 75
1 file changed, 75 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
the following branch as it is dependent on the
Arm SMMU Refactor changes from Robin Murphy that are present in this branch.
https://git.kernel.org/pub/scm/linux/kernel/git/will/linux.git
for-joerg/arm-smmu/updates
Krishna Reddy (7):
iommu/arm-smmu: add Nvidia SMMUv2 implementation
dt
Enable SMMU translations for SDHCI and EQOS transactions.
Signed-off-by: Krishna Reddy
---
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index ad509bb..0496a87
Add Nvidia SMMUv2 implementation and model info.
Signed-off-by: Krishna Reddy
---
MAINTAINERS | 2 +
drivers/iommu/Makefile | 2 +-
drivers/iommu/arm-smmu-impl.c | 2 +
drivers/iommu/arm-smmu-nvidia.c | 97 +
drivers
Add binding doc for Nvidia's smmu-v2 implementation.
Signed-off-by: Krishna Reddy
---
Documentation/devicetree/bindings/iommu/arm,smmu.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.txt
b/Documentation/devicetree/bindings/iomm
Add Memory controller DT node on T194 and enable it.
This patch is a prerequisite for SMMU enable on T194.
Signed-off-by: Krishna Reddy
---
arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 4
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 7 +++
2 files changed, 11 insertions
Add global/context fault hooks to allow Nvidia SMMU implementation
handle faults across multiple SMMUs.
Signed-off-by: Krishna Reddy
---
drivers/iommu/arm-smmu-nvidia.c | 127
drivers/iommu/arm-smmu.c| 6 ++
drivers/iommu/arm-smmu.h
>> +#global-interrupts = <1>;
>Shouldn't that be 3?
Interrupt line is shared between global and all context faults for each SMMU
instance.
Nvidia implementation checks for both Global and context faults on each
interrupt to an SMMU instance.
It can be either 1 or 3. If we make it
>> +if (smmu->impl->global_fault)
>> +return smmu->impl->global_fault(irq, smmu);
>Can't we just register impl->global_fault (if set) instead of
>arm_smmu_global_fault as the handler when we first set up the IRQs in
>arm_smmu_device_probe()?
>Ideally we'd do the same for the cont
>> +for (i = 0; i < to_nsmmu(smmu)->num_inst; i++)
>It might make more sense to make this the innermost loop, i.e.:
for (i = 0; i < nsmmu->num_inst; i++)
reg &= readl_relaxed(nsmmu_page(smmu, i, page)...
>since polling the instances in parallel rather than in series see
>> +"nidia,smmu-v2"
>> "qcom,smmu-v2"
>I agree with Mikko that the compatible must be at least SoC-specific, but
>potentially even instance-specific (e.g. "nvidia,tegra194-gpu-smmu")
> depending on how many of these parallel-SMMU configurations mi
>> +ARM_SMMU_MATCH_DATA(nvidia_smmuv2, ARM_SMMU_V2, NVIDIA_SMMUV2);
> From the previous discussions, I got the impression that other than the
> 'novel' way they're integrated, the actual SMMU implementations were
> unmodified Arm MMU-500s. Is that the case, or have I misread something?
The ARM
>The number of global interrupts has never been related to the number of
>context interrupts :/
Yeah, They are not related. I was trying to use minimum irq entries in the DT
node as they both would achieve the same functionality.
>Clearly you have one combined interrupt output per SMMU - descr
>> +smmu: iommu@1200 {
>> +compatible = "nvidia,smmu-v2";
>Should we have a compatibility string like "nvidia,tegra194-smmu" so that we
>can have other chips with SMMUv2 that could be different?
As pointed by Robin as well, as Nvidia hasn't modified ARM MMU-500
implementatio
>Wouldn't it work if you replaced all calls of __arm_smmu_tlb_sync() by
>smmu->impl->tlb_sync() and assign __arm_smmu_tlb_sync() as default for
>devices that don't need to override it? That makes this patch slightly larger,
>but it saves us one level of indirection.
The tlb_ops->tlb_sync can be o
>> +static irqreturn_t nsmmu_context_fault_inst(int irq,
>> +struct arm_smmu_device *smmu,
>> +int idx, int inst);
>More of these signed integers that could be unsigned. Also why the need to
>predeclare this? Can you
>> +if (smmu->impl->tlb_sync) {
>> +smmu->impl->tlb_sync(smmu, page, sync, status);
>What I'd hoped is that rather than needing a hook for this, you could just
>override smmu_domain->tlb_ops from .init_context to wire up the alternate
>.sync method directly. That would save this
>>> +ARM_SMMU_MATCH_DATA(nvidia_smmuv2, ARM_SMMU_V2, NVIDIA_SMMUV2);
>> The ARM MMU-500 implementation is unmodified. It is the way the are
>> integrated and used together(for interleaved accesses) is different from
>> regular ARM MMU-500.
>> I have added it to get the model number and to be a
Add Memory controller DT node on T194 and enable it.
This patch is a prerequisite for SMMU enable on T194.
Signed-off-by: Krishna Reddy
---
arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 4
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 7 +++
2 files changed, 11 insertions
Add DT node for T194 SMMU to enable SMMU support.
Signed-off-by: Krishna Reddy
---
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 77
1 file changed, 77 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
Remove const keyword for arm_smmu_flush_ops in arm_smmu_domain
and replace direct references to arm_smmu_tlb_sync* functions with
arm_smmu_flush_ops->tlb_sync().
This is necessary for vendor specific implementations that
need to override arm_smmu_flush_ops in part or full.
Signed-off-by: Kris
Add global/context fault hooks to allow NVIDIA SMMU implementation
handle faults across multiple SMMUs.
Signed-off-by: Krishna Reddy
---
drivers/iommu/arm-smmu-nvidia.c | 100
drivers/iommu/arm-smmu.c| 11 -
drivers/iommu/arm-smmu.h
NVIDIA's Tegra194 soc uses two ARM MMU-500s together to interleave
IOVA accesses across them.
Add NVIDIA implementation for dual ARM MMU-500s and add new compatible
string for Tegra194 soc.
Signed-off-by: Krishna Reddy
---
MAINTAINERS | 2 +
drivers/iommu/Mak
Add binding for NVIDIA's Tegra194 Soc SMMU that is based
on ARM MMU-500.
Signed-off-by: Krishna Reddy
---
Documentation/devicetree/bindings/iommu/arm,smmu.txt | 4
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.txt
b/Documentation/devic
c tlb.
v1 - https://lkml.org/lkml/2019/8/29/1588
Krishna Reddy (7):
iommu/arm-smmu: prepare arm_smmu_flush_ops for override
iommu/arm-smmu: add NVIDIA implementation for dual ARM MMU-500 usage
dt-bindings: arm-smmu: Add binding for Tegra194 SMMU
iommu/arm-smmu: Add global/context fault implementa
Enable SMMU translations for SDHCI and EQOS transactions on T194.
Signed-off-by: Krishna Reddy
---
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index 5ae3bbf
NVIDIA's Tegra194 soc uses two ARM MMU-500s together to interleave
IOVA accesses across them.
Add NVIDIA implementation for dual ARM MMU-500s and add new compatible
string for Tegra194 soc.
Signed-off-by: Krishna Reddy
---
MAINTAINERS | 2 +
drivers/iommu/Mak
Add Memory controller DT node on T194 and enable it.
This patch is a prerequisite for SMMU enable on T194.
Signed-off-by: Krishna Reddy
---
arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 4
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 6 ++
2 files changed, 10 insertions(+)
diff
Remove const keyword for arm_smmu_flush_ops in arm_smmu_domain
and replace direct references to arm_smmu_tlb_sync* functions with
arm_smmu_flush_ops->tlb_sync().
This is necessary for vendor specific implementations that
need to override arm_smmu_flush_ops in part or full.
Signed-off-by: Kris
Add DT node for T194 SMMU to enable SMMU support.
Signed-off-by: Krishna Reddy
---
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 77
1 file changed, 77 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
Add global/context fault hooks to allow NVIDIA SMMU implementation
handle faults across multiple SMMUs.
Signed-off-by: Krishna Reddy
---
drivers/iommu/arm-smmu-nvidia.c | 100
drivers/iommu/arm-smmu.c| 11 -
drivers/iommu/arm-smmu.h
Enable SMMU translations for SDHCI and EQOS transactions on T194.
Signed-off-by: Krishna Reddy
---
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index 6f81e90
Changes in v3:
Rebased on top of
https://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu.git/ next.
Resolved compile error seen with tegra194.dtsi changes after rebase.
v2 - https://lkml.org/lkml/2019/9/2/980
v1 - https://lkml.org/lkml/2019/8/29/1588
Krishna Reddy (7):
iommu/arm-smmu
Add binding for NVIDIA's Tegra194 Soc SMMU that is based
on ARM MMU-500.
Signed-off-by: Krishna Reddy
---
Documentation/devicetree/bindings/iommu/arm,smmu.txt | 4
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.txt
b/Documentation/devic
Hi Robin,
>>Apologies for crossed wires, but I had a series getting rid of
>>arm_smmu_flush_ops which was also meant to end up making things a bit easier
>>for you:
I was looking to rebase on top of your changes first. Then I read Will's reply
that said your work is queued for 5.5.
Let me kno
>>https://git.kernel.org/pub/scm/linux/kernel/git/will/linux.git/log/?h=for-joerg/arm-smmu/updates
Thanks Will! Let me rebase my patches on top of this branch and send it out.
-KR
___
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.li
Add Memory controller DT node on T194 and enable it.
This patch is a prerequisite for SMMU enable on T194.
Signed-off-by: Krishna Reddy
---
arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 4
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 6 ++
2 files changed, 10 insertions(+)
diff
://lkml.org/lkml/2019/10/18/1601
v2 - https://lkml.org/lkml/2019/9/2/980
v1 - https://lkml.org/lkml/2019/8/29/1588
Krishna Reddy (6):
iommu/arm-smmu: add NVIDIA implementation for dual ARM MMU-500 usage
dt-bindings: arm-smmu: Add binding for Tegra194 SMMU
iommu/arm-smmu: Add global/context fault
Add binding for NVIDIA's Tegra194 Soc SMMU that is based
on ARM MMU-500.
Signed-off-by: Krishna Reddy
---
Documentation/devicetree/bindings/iommu/arm,smmu.txt | 4
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.txt
b/Documentation/devic
NVIDIA's Tegra194 soc uses two ARM MMU-500s together to interleave
IOVA accesses across them.
Add NVIDIA implementation for dual ARM MMU-500s and add new compatible
string for Tegra194 soc.
Signed-off-by: Krishna Reddy
---
MAINTAINERS | 2 +
drivers/iommu/Mak
Enable SMMU translations for SDHCI and EQOS transactions on T194.
Signed-off-by: Krishna Reddy
---
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index 6f81e90
Add global/context fault hooks to allow NVIDIA SMMU implementation
handle faults across multiple SMMUs.
Signed-off-by: Krishna Reddy
---
drivers/iommu/arm-smmu-nvidia.c | 100
drivers/iommu/arm-smmu.c| 11 -
drivers/iommu/arm-smmu.h
Add DT node for T194 SMMU to enable SMMU support.
Signed-off-by: Krishna Reddy
---
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 77
1 file changed, 77 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
Limit the IOVA allocated to dma-ranges specified for the device.
This is necessary to ensure that IOVA allocated is addressable
by device.
Signed-off-by: Krishna Reddy
---
drivers/iommu/dma-iommu.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/iommu/dma-iommu.c b/drivers
most of IOVA range supported by
HW? Can IOVA code look for dma-ranges on its own and limit the iova top to
lowest of mask and dma-ranges, if it is present? or any other ways you can
think of?
-KR
-Original Message-
From: Robin Murphy [mailto:robin.mur...@arm.com]
Sent: Friday, S
>OK, so that's really just another variant of the existing problem we have with
>certain PCI root complexes with restrictive inbound windows.
>The appropriate way to handle that is to reserve the unusable areas of the
>IOVA space up-front.
> Since the support for the ACPI equivalent of "dma-range
Tested-by: Krishna Reddy
Validated the entire patch set on Tegra194 SOC based platform and confirmed
that arm-smmu driver is functional as it has been.
-KR
-Original Message-
From: Robin Murphy
Sent: Friday, August 9, 2019 10:08 AM
To: w...@kernel.org
Cc: iommu@lists.linux
>> + - nvdia,tegra194-smmu-500
>The -500 suffix here seems a bit redundant since there's no other type of SMMU
>in Tegra194, correct?
Yeah, there is only one type of SMMU supported in T194. It was added to be
synonymous with mmu-500. Can be removed.
-KR
___
>Should NVIDIA_TEGRA194_SMMU be a separate value for smmu->model, perhaps? That
>way we avoid this somewhat odd check here.
NVIDIA haven't made any changes to arm,mmu-500. It is only used in different
topology. New model would be mis-leading here.
As suggested by Robin, It can just be moved to
Add binding for NVIDIA's Tegra194 SoC SMMU topology that is based
on ARM MMU-500.
Signed-off-by: Krishna Reddy
---
Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 5 +
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.ya
Add global/context fault hooks to allow NVIDIA SMMU implementation
handle faults across multiple SMMUs.
Signed-off-by: Krishna Reddy
---
drivers/iommu/arm-smmu-nvidia.c | 101 +++-
drivers/iommu/arm-smmu.c| 17 +-
drivers/iommu/arm-smmu.h| 3
- https://lkml.org/lkml/2019/10/30/1054
v3 - https://lkml.org/lkml/2019/10/18/1601
v2 - https://lkml.org/lkml/2019/9/2/980
v1 - https://lkml.org/lkml/2019/8/29/1588
Krishna Reddy (3):
iommu/arm-smmu: add NVIDIA implementation for dual ARM MMU-500 usage
dt-bindings: arm-smmu: Add binding for
NVIDIA's Tegra194 SoC uses two ARM MMU-500s together to interleave
IOVA accesses across them.
Add NVIDIA implementation for dual ARM MMU-500s and add new compatible
string for Tegra194 SoC SMMU topology.
Signed-off-by: Krishna Reddy
---
MAINTAINERS | 2 +
drivers/
>> + if (!nvidia_smmu->bases[0])
>> + nvidia_smmu->bases[0] = smmu->base;
>> +
>> + return nvidia_smmu->bases[inst] + (page << smmu->pgshift); }
>Not critical -- just a nit: why not put the bases[0] in init()?
smmu->base is not available during nvidia_smmu_impl_init() call. It
>> +static irqreturn_t nvidia_smmu_context_fault_bank(int irq,
>> + void __iomem *cb_base = nvidia_smmu_page(smmu, inst,
>> + smmu->numpage + idx);
[...]
>> + fsr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSR);
[...]
>> + writel_relaxed(fsr, cb_base + ARM_SMMU_CB_FSR);
>It reads FSR
/5/21/1114
v4 - https://lkml.org/lkml/2019/10/30/1054
v3 - https://lkml.org/lkml/2019/10/18/1601
v2 - https://lkml.org/lkml/2019/9/2/980
v1 - https://lkml.org/lkml/2019/8/29/1588
Krishna Reddy (3):
iommu/arm-smmu: add NVIDIA implementation for dual ARM MMU-500 usage
dt-bindings: arm-smmu: Add
NVIDIA's Tegra194 SoC uses two ARM MMU-500s together to interleave
IOVA accesses across them.
Add NVIDIA implementation for dual ARM MMU-500s and add new compatible
string for Tegra194 SoC SMMU topology.
Signed-off-by: Krishna Reddy
---
MAINTAINERS | 2 +
drivers/
Add global/context fault hooks to allow NVIDIA SMMU implementation
handle faults across multiple SMMUs.
Signed-off-by: Krishna Reddy
---
drivers/iommu/arm-smmu-nvidia.c | 98 +
drivers/iommu/arm-smmu.c| 17 +-
drivers/iommu/arm-smmu.h| 3 +
3
Add binding for NVIDIA's Tegra194 SoC SMMU topology that is based
on ARM MMU-500.
Signed-off-by: Krishna Reddy
---
Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 5 +
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.ya
>> +struct arm_smmu_device *nvidia_smmu_impl_init(struct arm_smmu_device
>> +*smmu) {
>> +unsigned int i;
>> +for (i = 1; i < MAX_SMMU_INSTANCES; i++) {
>> +struct resource *res;
>> +
>> +res = platform_get_resource(pdev, IORESOURCE_MEM, i);
>> +if
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