Hi Jean,
On Tue, Sep 21, 2021 at 9:33 PM Jean-Philippe Brucker
wrote:
>
> On Fri, Apr 23, 2021 at 03:21:39PM +0530, Vivek Gautam wrote:
> > Redirect the incoming page faults to the registered fault handler
> > that can take the fault information such as, pasid, page re
Add page_response iommu ops callback to send page response to
the device that generated io page fault.
Signed-off-by: Vivek Gautam
---
drivers/iommu/virtio-iommu.c | 47
1 file changed, 47 insertions(+)
diff --git a/drivers/iommu/virtio-iommu.c b/drivers
Once the page faults are handled, the response has to be sent to
virtio-iommu backend, from where it can be sent to the host to
prepare the response to a generated io page fault by the device.
Add a new virt-queue request type to handle this.
Signed-off-by: Vivek Gautam
---
include/uapi/linux
SVA bind and unbind implementations will allow to prepare translation
context with CPU page tables that can be programmed into host iommu
hardware to realize shared address space utilization between the CPU
and virtualized devices using virtio-iommu.
Signed-off-by: Vivek Gautam
---
drivers
Implementing the alloc_shared_cd and free_shared_cd in cd-lib, and
start using them for arm-smmu-v3-sva implementation.
Signed-off-by: Vivek Gautam
---
.../arm/arm-smmu-v3/arm-smmu-v3-cd-lib.c | 71
.../iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c | 83
In preparation to adding shared descriptor allocation and free pasid
table ops, pull out the alloc_shared_cd and free_shared_cd helpers from
arm-smmu-v3 and place them in arm-smmu-v3-cd-lib library driver.
Signed-off-by: Vivek Gautam
---
.../arm/arm-smmu-v3/arm-smmu-v3-cd-lib.c | 149
. This also requires enabling the
PRI capability on the device.
Signed-off-by: Vivek Gautam
---
drivers/iommu/virtio-iommu.c | 268 ++
include/uapi/linux/virtio_iommu.h | 1 +
2 files changed, 269 insertions(+)
diff --git a/drivers/iommu/virtio-iommu.c b/drivers
Add pasid table ops to allocate and free shared contexts. These helpers
interact using mmu notifiers, so add a mmu notifier implementation
structure in pasid tables as well. This change can help pull out the
shared pasid (context-descriptor) implementation out of arm-smmu-v3.
Signed-off-by: Vivek
Redirect the incoming page faults to the registered fault handler
that can take the fault information such as, pasid, page request
group-id, address and pasid flags.
Signed-off-by: Vivek Gautam
---
drivers/iommu/virtio-iommu.c | 80 ++-
include/uapi/linux
Add a io page fault queue to the driver so that it can be used
to redirect faults to the handler.
Signed-off-by: Vivek Gautam
---
drivers/iommu/virtio-iommu.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/drivers/iommu/virtio-iommu.c b/drivers/iommu/virtio-iommu.c
Keeping a record of list of endpoints that are served by the virtio-iommu
device would help in redirecting the requests of page faults to the
correct endpoint device to handle such requests.
Signed-off-by: Vivek Gautam
---
drivers/iommu/virtio-iommu.c | 21 +
1 file changed
Add fault information for group-id and necessary flags for page
request faults that can be handled by page fault handler in
virtio-iommu driver.
Signed-off-by: Vivek Gautam
Cc: Joerg Roedel
Cc: Will Deacon
Cc: Robin Murphy
Cc: Jean-Philippe Brucker
Cc: Eric Auger
Cc: Alex Williamson
Cc
/linux-iommu/20210115121342.15093-1-vivek.gau...@arm.com/
[3] https://www.spinics.net/lists/arm-kernel/msg886518.html
Vivek Gautam (11):
uapi/virtio-iommu: Add page request grp-id and flags information
iommu/virtio: Maintain a list of endpoints served by viommu_dev
iommu/virtio: Handle incoming
Hi Eric,
On Fri, Feb 12, 2021 at 11:44 PM Auger Eric wrote:
>
> Hi Vivek,
>
> On 2/12/21 11:58 AM, Vivek Gautam wrote:
> > Update nested domain information required for stage1 page table.
>
> s/reuqired/required in the commit title
Oh! my bad.
> >
&
Update nested domain information required for stage1 page table.
Signed-off-by: Vivek Gautam
---
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 16 ++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
b/drivers/iommu/arm/arm
Add a vendor specific structure for domain nesting info for
arm smmu-v3, and necessary info fields required to populate
stage1 page tables.
Signed-off-by: Vivek Gautam
---
include/uapi/linux/iommu.h | 31 +--
1 file changed, 25 insertions(+), 6 deletions(-)
diff
ttps://lore.kernel.org/kvm/306e7dd2-9eb2-0ca3-6a93-7c9aa0821...@arm.com/
[5]
https://github.com/vivek-arm/linux/tree/5.11-rc3-nested-pgtbl-arm-smmuv3-virtio-iommu
Vivek Gautam (2):
iommu: Report domain nesting info for arm-smmu-v3
iommu: arm-smmu-v3: Report domain nesting info reuqired for st
Hi Yi,
On Sat, Jan 23, 2021 at 2:29 PM Liu, Yi L wrote:
>
> Hi Eric,
>
> > From: Auger Eric
> > Sent: Tuesday, January 19, 2021 6:03 PM
> >
> > Hi Yi, Vivek,
> >
> [...]
> > > I see. I think there needs a change in the code there. Should also expect
> > > a nesting_info returned instead of an
Fault type information can tell about a page request fault or
an unreceoverable fault, and further additions to fault reasons
and the related PASID information can help in handling faults
efficiently.
Signed-off-by: Vivek Gautam
Cc: Joerg Roedel
Cc: Will Deacon
Cc: Michael S. Tsirkin
Cc
-by: Vivek Gautam
Cc: Joerg Roedel
Cc: Will Deacon
Cc: Michael S. Tsirkin
Cc: Robin Murphy
Cc: Jean-Philippe Brucker
Cc: Eric Auger
Cc: Alex Williamson
Cc: Kevin Tian
Cc: Jacob Pan
Cc: Liu Yi L
Cc: Lorenzo Pieralisi
Cc: Shameerali Kolothum Thodi
---
drivers/iommu/virtio-iommu.c | 131
-off-by: Vivek Gautam
Cc: Joerg Roedel
Cc: Will Deacon
Cc: Michael S. Tsirkin
Cc: Robin Murphy
Cc: Jean-Philippe Brucker
Cc: Eric Auger
Cc: Alex Williamson
Cc: Kevin Tian
Cc: Jacob Pan
Cc: Liu Yi L
Cc: Lorenzo Pieralisi
Cc: Shameerali Kolothum Thodi
---
drivers/iommu/virtio-iommu.c | 314
needed with current iommu-pasid-table infrastructure.
Also updating uapi defines as required by latest changes]
Signed-off-by: Vivek Gautam
Cc: Joerg Roedel
Cc: Will Deacon
Cc: Michael S. Tsirkin
Cc: Robin Murphy
Cc: Jean-Philippe Brucker
Cc: Eric Auger
Cc: Alex Williamson
Cc: Kevin
From: Jean-Philippe Brucker
Add the required UAPI defines for binding pasid tables in virtio-iommu.
This mode allows to hand stage-1 page tables over to the guest.
Signed-off-by: Jean-Philippe Brucker
[Vivek: Refactor to cleanup headers for invalidation]
Signed-off-by: Vivek Gautam
Cc: Joerg
In preparation to add attach pasid table op, separate out the
existing attach request code to a separate method.
Signed-off-by: Vivek Gautam
Cc: Joerg Roedel
Cc: Will Deacon
Cc: Michael S. Tsirkin
Cc: Robin Murphy
Cc: Jean-Philippe Brucker
Cc: Eric Auger
Cc: Alex Williamson
Cc: Kevin Tian
Add info about asid_bits and additional flags to table format
probing header.
Signed-off-by: Vivek Gautam
Cc: Joerg Roedel
Cc: Will Deacon
Cc: Michael S. Tsirkin
Cc: Robin Murphy
Cc: Jean-Philippe Brucker
Cc: Eric Auger
Cc: Alex Williamson
Cc: Kevin Tian
Cc: Jacob Pan
Cc: Liu Yi L
Cc
aisd_bits data is required to prepare stage-1 tables for arm-smmu-v3.
Signed-off-by: Vivek Gautam
Cc: Joerg Roedel
Cc: Will Deacon
Cc: Robin Murphy
Cc: Jean-Philippe Brucker
Cc: Eric Auger
Cc: Alex Williamson
Cc: Kevin Tian
Cc: Jacob Pan
Cc: Liu Yi L
Cc: Lorenzo Pieralisi
Cc
n separate structures for page table and pasid table format.]
Signed-off-by: Vivek Gautam
Cc: Joerg Roedel
Cc: Will Deacon
Cc: Michael S. Tsirkin
Cc: Robin Murphy
Cc: Jean-Philippe Brucker
Cc: Eric Auger
Cc: Alex Williamson
Cc: Kevin Tian
Cc: Jacob Pan
Cc: Liu Yi L
Cc: Lorenzo Pieralisi
Cc:
-Philippe Brucker
[Vivek: Use a single "struct virtio_iommu_probe_table_format" rather
than separate structures for page table and pasid table format.
Also update commit message.]
Signed-off-by: Vivek Gautam
Cc: Joerg Roedel
Cc: Will Deacon
Cc: Michael S. Tsirkin
Cc: Ro
Te change allows different consumers of arm-smmu-v3-cd-lib to set
their respective sync op for pasid entries.
Signed-off-by: Vivek Gautam
Cc: Joerg Roedel
Cc: Will Deacon
Cc: Robin Murphy
Cc: Jean-Philippe Brucker
Cc: Eric Auger
Cc: Alex Williamson
Cc: Kevin Tian
Cc: Jacob Pan
Cc: Liu Yi
Update base address information in vendor pasid table info to pass that
to user-space for stage1 table management.
Signed-off-by: Vivek Gautam
Cc: Joerg Roedel
Cc: Will Deacon
Cc: Robin Murphy
Cc: Jean-Philippe Brucker
Cc: Eric Auger
Cc: Alex Williamson
Cc: Kevin Tian
Cc: Jacob Pan
Cc
Update arm-smmu-v3 context descriptor (CD) library driver to work
with iommu-pasid-table APIs. These APIs are then used in arm-smmu-v3
drivers to manage CD tables.
Signed-off-by: Vivek Gautam
Cc: Joerg Roedel
Cc: Will Deacon
Cc: Robin Murphy
Cc: Jean-Philippe Brucker
Cc: Eric Auger
Cc: Alex
for registering a vendor API that attaches
to these ops. The vendor APIs would eventually perform arch level
implementations for these PASID tables.
Signed-off-by: Vivek Gautam
Cc: Joerg Roedel
Cc: Will Deacon
Cc: Robin Murphy
Cc: Jean-Philippe Brucker
Cc: Eric Auger
Cc: Alex Williamson
Cc: Kevin Tian
Cc
driver call such code.
Signed-off-by: Vivek Gautam
Cc: Joerg Roedel
Cc: Will Deacon
Cc: Robin Murphy
Cc: Jean-Philippe Brucker
Cc: Eric Auger
Cc: Alex Williamson
Cc: Kevin Tian
Cc: Jacob Pan
Cc: Liu Yi L
Cc: Lorenzo Pieralisi
Cc: Shameerali Kolothum Thodi
---
drivers/iommu/arm/arm-smmu
format
Vivek Gautam (9):
iommu/arm-smmu-v3: Create a Context Descriptor library
iommu: Add a simple PASID table library
iommu/arm-smmu-v3: Update drivers to work with iommu-pasid-table
iommu/arm-smmu-v3: Update CD base address info for user-space
iommu/arm-smmu-v3: Set sync op from consumer
Hi Yi,
On Tue, Jan 12, 2021 at 2:51 PM Liu, Yi L wrote:
>
> Hi Vivek,
>
> > From: Vivek Gautam
> > Sent: Tuesday, January 12, 2021 2:50 PM
> >
> > Hi Yi,
> >
> >
> > On Thu, Sep 10, 2020 at 4:13 PM Liu Yi L wrote:
> > >
Hi Yi,
On Thu, Sep 10, 2020 at 4:13 PM Liu Yi L wrote:
>
> This patch is added as instead of returning a boolean for DOMAIN_ATTR_NESTING,
> iommu_domain_get_attr() should return an iommu_nesting_info handle. For
> now, return an empty nesting info struct for now as true nesting is not
> yet
are [B] and your kernel branch with smmute [C], I
was able to
test smmute by initiating different DMA transactions. With model logs I was able
to validate ATS and PRI command flows as well.
So I am happy to give my tested-by tag.
Tested-by: Vivek Gautam
Best regards
Vivek
[A]
https://developer.a
On Fri, Aug 23, 2019 at 12:03 PM Vivek Gautam
wrote:
>
> Add reset hook for sdm845 based platforms to turn off
> the wait-for-safe sequence.
>
> Understanding how wait-for-safe logic affects USB and UFS performance
> on MTP845 and DB845 boards:
>
> Qcom's implementation of
conv=sync
300+0 records in
300+0 records out
314572800 bytes (300.0MB) copied, 1.030541 seconds, 291.1MB/s
real0m 1.03s
user0m 0.00s
sys 0m 0.54s
Signed-off-by: Vivek Gautam
---
drivers/iommu/arm-smmu-impl.c | 27 ++-
1 file changed, 26 insertions(+), 1
There are scnenarios where drivers are required to make a
scm call in atomic context, such as in one of the qcom's
arm-smmu-500 errata [1].
[1] ("https://source.codeaurora.org/quic/la/kernel/msm-4.9/
tree/drivers/iommu/arm-smmu.c?h=msm-4.9#n4842")
Signed-off-by: Vivek Gautam
Qcom's smmu-500 needs to toggle wait-for-safe sequence to
handle TLB invalidation sync's.
Few firmwares allow doing that through SCM interface.
Add API to toggle wait for safe from firmware through a
SCM call.
Signed-off-by: Vivek Gautam
Reviewed-by: Bjorn Andersson
---
drivers/firmware
c30a
[5] https://patchwork.kernel.org/patch/11096265/
[6] https://git.kernel.org/pub/scm/linux/kernel/git/will/linux.git/
Vivek Gautam (3):
firmware: qcom_scm-64: Add atomic version of qcom_scm_call
firmware/qcom_scm: Add scm call to handle smmu errata
iommu: arm-smmu-impl: Add sd
uggest adding any other data variable in the
ARM_SMMU_MATCH_DATA?
To show SoC specific needs, I have the change attached in this email to
take care of the SDM845 'wait-for-safe' sequence.
Please take a look.
Thanks & Regards
Vivek
};
static inline void __iomem *arm_smmu_page(struct arm
.
Hi,
I have given this series a shot with 5.3-rc5 kernel on MTP sdm845
device, and smmu works as expected.
Tested-by: Vivek Gautam
Best regards
Vivek
Robin Murphy (17):
iommu/arm-smmu: Mask TLBI address correctly
iommu/qcom: Mask TLBI addresses correctly
iommu/arm-smmu: Convert GR0
On Tue, Aug 6, 2019 at 3:56 AM Bjorn Andersson
wrote:
>
> On Wed 12 Jun 00:15 PDT 2019, Vivek Gautam wrote:
>
> > Indicate on MTP SDM845 that firmware implements handler to
> > TLB invalidate erratum SCM call where SAFE sequence is toggled
> > to achieve optimum perfo
On Tue, Aug 6, 2019 at 3:58 AM Bjorn Andersson
wrote:
>
> On Wed 19 Jun 04:34 PDT 2019, Vivek Gautam wrote:
>
> > On Tue, Jun 18, 2019 at 11:25 PM Will Deacon wrote:
> > >
> > > On Wed, Jun 12, 2019 at 12:45:51PM +0530, Vivek Gautam wrote:
> > > > Th
On Wed, Jun 26, 2019 at 8:18 PM Will Deacon wrote:
>
> On Wed, Jun 26, 2019 at 12:03:02PM +0530, Vivek Gautam wrote:
> > On Tue, Jun 25, 2019 at 7:09 PM Will Deacon wrote:
> > >
> > > On Tue, Jun 25, 2019 at 12:34:56PM +0530, Vivek Gautam wrote:
> >
On Tue, Jun 25, 2019 at 7:09 PM Will Deacon wrote:
>
> On Tue, Jun 25, 2019 at 12:34:56PM +0530, Vivek Gautam wrote:
> > On Mon, Jun 24, 2019 at 10:33 PM Will Deacon wrote:
> > > Instead, I think this needs to be part of a separate file that is
> > > maintain
Hi Will,
On Mon, Jun 24, 2019 at 10:33 PM Will Deacon wrote:
>
> [+Krishna]
>
> Hi Vivek,
>
> On Mon, Jun 24, 2019 at 03:58:32PM +0530, Vivek Gautam wrote:
> > On Tue, Jun 18, 2019 at 11:22 PM Will Deacon wrote:
> > > On Fri, Jun 14, 2019 at 02:48:07PM +0530,
Hi Will,
On Tue, Jun 18, 2019 at 11:22 PM Will Deacon wrote:
>
> Hi Vivek,
>
> On Fri, Jun 14, 2019 at 02:48:07PM +0530, Vivek Gautam wrote:
> > On 6/14/2019 9:35 AM, Bjorn Andersson wrote:
> > > On Wed 12 Jun 00:15 PDT 2019, Vivek Gautam wrote:
> > >
> >
On Tue, Jun 18, 2019 at 11:25 PM Will Deacon wrote:
>
> On Wed, Jun 12, 2019 at 12:45:51PM +0530, Vivek Gautam wrote:
> > There are scnenarios where drivers are required to make a
> > scm call in atomic context, such as in one of the qcom's
> > arm-smmu-500 errata
On 6/14/2019 9:35 AM, Bjorn Andersson wrote:
On Wed 12 Jun 00:15 PDT 2019, Vivek Gautam wrote:
Qcom's implementation of arm,mmu-500 adds a WAIT-FOR-SAFE logic
to address under-performance issues in real-time clients, such as
Display, and Camera.
On receiving an invalidation requests
On 6/14/2019 9:36 AM, Bjorn Andersson wrote:
On Wed 12 Jun 00:15 PDT 2019, Vivek Gautam wrote:
Indicate on MTP SDM845 that firmware implements handler to
TLB invalidate erratum SCM call where SAFE sequence is toggled
to achieve optimum performance on real-time clients, such as
display
/commit/drivers/iommu/arm-smmu.c?h=CogSystems-msm-49/msm-4.9=da765c6c75266b38191b38ef086274943f353ea7
[4]
https://source.codeaurora.org/quic/la/kernel/msm-4.9/commit/drivers/iommu/arm-smmu.c?h=CogSystems-msm-49/msm-4.9=8696005aaaf745de68f57793c1a534a34345c30a
Vivek Gautam (4):
firmware: qcom_scm-64
Qcom's smmu-500 needs to toggle wait-for-safe logic to
handle TLB invalidations.
Few firmwares allow doing that through SCM interface.
Add API to toggle wait for safe from firmware through a
SCM call.
Signed-off-by: Vivek Gautam
Reviewed-by: Bjorn Andersson
---
drivers/firmware/qcom_scm-32.c
if=/dev/sda of=/dev/zero bs=1048576 count=300 conv=sync
300+0 records in
300+0 records out
314572800 bytes (300.0MB) copied, 1.030541 seconds, 291.1MB/s
real0m 1.03s
user0m 0.00s
sys 0m 0.54s
Signed-off-by: Vivek Gautam
---
drivers/iommu/arm-smmu.c | 16
1 file changed
m-4.9=da765c6c75266b38191b38ef086274943f353ea7")
Signed-off-by: Vivek Gautam
Reviewed-by: Bjorn Andersson
---
drivers/firmware/qcom_scm-64.c | 136 -
1 file changed, 92 insertions(+), 44 deletions(-)
diff --git a/drivers/firmware/qcom_scm-64.c b/drivers/firmware/qcom_scm-
Indicate on MTP SDM845 that firmware implements handler to
TLB invalidate erratum SCM call where SAFE sequence is toggled
to achieve optimum performance on real-time clients, such as
display and camera.
Signed-off-by: Vivek Gautam
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 1 +
1 file changed
On Mon, Jun 3, 2019 at 4:14 PM Rob Clark wrote:
>
> On Mon, Jun 3, 2019 at 12:57 AM Vivek Gautam
> wrote:
> >
> >
> >
> > On 6/3/2019 11:50 AM, Tomasz Figa wrote:
> > > On Mon, Jun 3, 2019 at 4:40 AM Rob Clark wrote:
> > >> On Fri, May 10, 2
On 6/3/2019 11:50 AM, Tomasz Figa wrote:
On Mon, Jun 3, 2019 at 4:40 AM Rob Clark wrote:
On Fri, May 10, 2019 at 7:35 AM Rob Clark wrote:
On Tue, Dec 4, 2018 at 2:29 PM Rob Herring wrote:
On Sat, Dec 1, 2018 at 10:54 AM Rob Clark wrote:
This solves a problem we see with drm/msm,
On Thu, May 23, 2019 at 4:11 PM Robin Murphy wrote:
>
> On 2019-05-16 10:30 am, Vivek Gautam wrote:
> > Few Qualcomm platforms such as, sdm845 have an additional outer
> > cache called as System cache, aka. Last level cache (LLC) that
> > allows non-coherent devices to
Hi Robin,
On Thu, May 16, 2019 at 3:00 PM Vivek Gautam
wrote:
>
> Few Qualcomm platforms such as, sdm845 have an additional outer
> cache called as System cache, aka. Last level cache (LLC) that
> allows non-coherent devices to upgrade to using caching.
> This cache sits right
,
outer read write-back non-transient
Coherent I/O devices use system cache by marking the memory as
normal cached.
Non-coherent I/O devices should mark the memory as normal
sys-cached in page tables to use system cache.
Signed-off-by: Vivek Gautam
---
V3 version of this patch and related series
LPAE_TCR_RGN_NC << ARM_LPAE_TCR_ORGN0_SHIFT);
> + }
This looks okay to me based on the discussion that we had on a similar
patch that I
posted. So,
Reviewed-by: Vivek Gautam
[1] https://lore.kernel.org/patchwork/patch/1032939/
Thanks & regards
Vivek
>
> s
On Tue, May 14, 2019 at 12:26 PM Vivek Gautam
wrote:
>
> Hi Robin,
>
>
> On Mon, May 13, 2019 at 5:02 PM Robin Murphy wrote:
> >
> > On 13/05/2019 11:04, Vivek Gautam wrote:
> > > Few Qualcomm platforms such as, sdm845 have an additional outer
> > >
Hi Robin,
On Mon, May 13, 2019 at 5:02 PM Robin Murphy wrote:
>
> On 13/05/2019 11:04, Vivek Gautam wrote:
> > Few Qualcomm platforms such as, sdm845 have an additional outer
> > cache called as System cache, aka. Last level cache (LLC) that
> > allows non-coherent dev
,
outer read write-back non-transient
Coherent I/O devices use system cache by marking the memory as
normal cached.
Non-coherent I/O devices should mark the memory as normal
sys-cached in page tables to use system cache.
Signed-off-by: Vivek Gautam
---
V3 version of this patch and related series
to quickly identify the faulting
master device.
Signed-off-by: Vivek Gautam
Reviewed-by: Bjorn Andersson
---
Changes since v1:
- Addressed review comments, given by Bjorn, for nits.
drivers/iommu/arm-smmu-regs.h | 2 ++
drivers/iommu/arm-smmu.c | 7 +--
2 files changed, 7 insertions
On Fri, Apr 19, 2019 at 5:55 AM Bjorn Andersson
wrote:
>
> On Mon 15 Apr 10:37 PDT 2019, Vivek Gautam wrote:
>
> > Bits[15:0] in CBFRSYNRA register contain information about
> > StreamID of the incoming transaction that generated the
> > fault. Dump CBFRSYNR
to quickly identify the faulting
master device.
Signed-off-by: Vivek Gautam
---
V1 of the patch available @
https://lore.kernel.org/patchwork/patch/1061615/
Changes from v1:
- Dump the raw register value of CBFRSYNRA register in the
context fault log rather than extracting the SID inforamtion
On 4/15/2019 3:11 PM, Robin Murphy wrote:
On 15/04/2019 09:07, Vivek Gautam wrote:
Extract the SID and add the information to context fault log.
This is specially useful in a distributed smmu architecture
where multiple masters are connected to smmu. SID information
helps to quickly identify
Extract the SID and add the information to context fault log.
This is specially useful in a distributed smmu architecture
where multiple masters are connected to smmu. SID information
helps to quickly identify the faulting master device.
Signed-off-by: Vivek Gautam
---
drivers/iommu/arm-smmu
On 4/2/2019 7:24 PM, Robin Murphy wrote:
On 30/03/2019 14:18, Vivek Gautam wrote:
You should probably have some "bus" and "iface" clocks too, per the
requirement of "qcom,smmu-v2". Maybe Vivek might know what's relevant
for MSM8998?
As Jeffrey rightly mention
Hi Marc,
On Fri, Mar 29, 2019 at 11:59 PM Robin Murphy wrote:
>
> On 29/03/2019 10:51, Marc Gonzalez wrote:
> > On 28/03/2019 18:05, Marc Gonzalez wrote:
> >
> >> ANOC1 SMMU filters PCIe accesses.
> >
> > I'm not sure this description is entirely accurate...
> >
> > ANOC likely stands for
On 3/26/2019 2:39 AM, Bjorn Andersson wrote:
On Sun 09 Sep 23:25 PDT 2018, Vivek Gautam wrote:
There are scnenarios where drivers are required to make a
scm call in atomic context, such as in one of the qcom's
arm-smmu-500 errata [1].
[1] ("https://source.codeaurora.org/quic/la/kerne
On Tue, Jan 29, 2019 at 8:34 PM Ard Biesheuvel
wrote:
>
> (+ Bjorn)
>
> On Mon, 28 Jan 2019 at 12:27, Vivek Gautam
> wrote:
> >
> > Hi Ard,
> >
> > On Thu, Jan 24, 2019 at 1:25 PM Ard Biesheuvel
> > wrote:
> > >
> >
Hi Will,
On Tue, Jan 22, 2019 at 11:14 AM Will Deacon wrote:
>
> On Mon, Jan 21, 2019 at 11:35:30AM +0530, Vivek Gautam wrote:
> > On Sun, Jan 20, 2019 at 5:31 AM Will Deacon wrote:
> > > On Thu, Jan 17, 2019 at 02:57:18PM +0530, Vivek Gautam wrote:
> > > > Ad
On Mon, Jan 21, 2019 at 6:43 PM Robin Murphy wrote:
>
> On 17/01/2019 09:27, Vivek Gautam wrote:
> > From Robin's comment [1] about touching TCR configurations -
> >
> > "TBH if we're going to touch the TCR attributes at all then we should
> > probably corr
Hi Ard,
On Thu, Jan 24, 2019 at 1:25 PM Ard Biesheuvel
wrote:
>
> On Thu, 24 Jan 2019 at 07:58, Vivek Gautam
> wrote:
> >
> > On Mon, Jan 21, 2019 at 7:55 PM Ard Biesheuvel
> > wrote:
> > >
> > > On Mon, 21 Jan 2019 at 14:56, Robin Murphy wr
10:50, Ard Biesheuvel wrote:
> > >>> On Mon, 21 Jan 2019 at 11:17, Vivek Gautam
> > >>> wrote:
> > >>>>
> > >>>> Hi,
> > >>>>
> > >>>>
> > >>>> On Mon, Jan 21, 2019 at 12:56
On Mon, Jan 21, 2019 at 7:23 PM Robin Murphy wrote:
>
> On 21/01/2019 05:53, Vivek Gautam wrote:
> > A number of arm_smmu_domain's attributes can be assigned based
> > on the iommu domains's attributes. These local attributes better
> > be managed by a bitmap.
> > So
Hi,
On Mon, Jan 21, 2019 at 12:56 PM Ard Biesheuvel
wrote:
>
> On Mon, 21 Jan 2019 at 06:54, Vivek Gautam
> wrote:
> >
> > Qualcomm SoCs have an additional level of cache called as
> > System cache, aka. Last level cache (LLC). This cache sits right
> > befor
Hi Will,
On Sun, Jan 20, 2019 at 5:31 AM Will Deacon wrote:
>
> On Thu, Jan 17, 2019 at 02:57:18PM +0530, Vivek Gautam wrote:
> > Adding a device tree option for arm smmu to enable non-cacheable
> > memory for page tables.
> > We already enable a smmu feature
system cache.
Signed-off-by: Vivek Gautam
---
drivers/iommu/io-pgtable-arm.c | 15 +--
drivers/iommu/io-pgtable.h | 4
include/linux/iommu.h | 2 ++
3 files changed, 19 insertions(+), 2 deletions(-)
diff --git a/drivers/iommu/io-pgtable-arm.c b/drivers/iommu/io
://lore.kernel.org/patchwork/cover/1032938/
Vivek Gautam (3):
iommu/arm-smmu: Move to bitmap for arm_smmu_domain atrributes
iommu/io-pgtable-arm: Add support to use system cache
iommu/arm-smmu: Add support to use system cache
drivers/iommu/arm-smmu.c | 28
drivers
A number of arm_smmu_domain's attributes can be assigned based
on the iommu domains's attributes. These local attributes better
be managed by a bitmap.
So remove boolean flags and move to a 32-bit bitmap, and enable
each bits separtely.
Signed-off-by: Vivek Gautam
---
drivers/iommu/arm-smmu.c
.
Signed-off-by: Vivek Gautam
---
drivers/iommu/arm-smmu.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index af18a7e7f917..7ebbcf1b2eb3 100644
--- a/drivers/iommu/arm-smmu.c
+++ b/drivers/iommu/arm-smmu.c
@@ -188,6 +188,7 @@ struct
-cacheable page tables for all masters
sitting on SMMU. Should this control be available per smmu_domain
as each master may have a different perf requirement?
Enabling this for the entire SMMU may not be desirable for all
masters.
[1] https://lore.kernel.org/patchwork/patch/1020906/
Vivek Gautam (2
ot_ using dma-coherent smmu to have non-cacheable page table
mappings.
Having another quirk flag can help in having non-cacheable memory for
page tables once and for all.
[1] https://lore.kernel.org/patchwork/patch/1020906/
Signed-off-by: Vivek Gautam
---
drivers/iommu/io-pgtab
On 1/8/2019 12:29 PM, Bjorn Andersson wrote:
On Thu 11 Oct 02:49 PDT 2018, Vivek Gautam wrote:
Add device node for arm,mmu-500 available on sdm845.
This MMU-500 with single TCU and multiple TBU architecture
is shared among all the peripherals except gpu.
Hi Vivek,
Applying this patch
Hi Robin,
On Fri, Dec 7, 2018 at 2:54 PM Vivek Gautam wrote:
>
> Hi Robin,
>
> On Tue, Dec 4, 2018 at 8:51 PM Robin Murphy wrote:
> >
> > On 04/12/2018 11:01, Vivek Gautam wrote:
> > > Qualcomm SoCs have an additional level of cache called as
> > >
On Thu, Dec 13, 2018 at 9:20 AM Tomasz Figa wrote:
>
> On Fri, Dec 7, 2018 at 6:25 PM Vivek Gautam
> wrote:
> >
> > Hi Robin,
> >
> > On Tue, Dec 4, 2018 at 8:51 PM Robin Murphy wrote:
> > >
> > > On 04/12/2018 11:01, Vivek Gautam wrote:
>
On Thu, Dec 13, 2018 at 4:16 PM Will Deacon wrote:
>
> On Thu, Dec 13, 2018 at 02:35:07PM +0530, Vivek Gautam wrote:
> > Qcom's implementation of arm,mmu-500 works well with current
> > arm-smmu driver implementation. Adding a soc specific compatible
> > along with arm,mm
Qcom's implementation of arm,mmu-500 works well with current
arm-smmu driver implementation. Adding a soc specific compatible
along with arm,mmu-500 makes the bindings future safe.
Signed-off-by: Vivek Gautam
Reviewed-by: Rob Herring
Cc: Will Deacon
---
Hi Joerg,
I am picking this out
Hi Will,
On Fri, Oct 12, 2018 at 11:37 AM Vivek Gautam
wrote:
>
>
>
> On 10/12/2018 3:46 AM, Rob Herring wrote:
> > On Thu, 11 Oct 2018 15:19:29 +0530, Vivek Gautam wrote:
> >> Qcom's implementation of arm,mmu-500 works well with current
> >> arm-smmu driver i
Hi Robin,
On Tue, Dec 4, 2018 at 8:51 PM Robin Murphy wrote:
>
> On 04/12/2018 11:01, Vivek Gautam wrote:
> > Qualcomm SoCs have an additional level of cache called as
> > System cache, aka. Last level cache (LLC). This cache sits right
> > before the DDR, and is tightly
://source.codeaurora.org/quic/la/kernel/msm-4.9/commit/?h=msm-4.9=d4c72c413ea27c43f60825193d4de9cb8ffd9602
Signed-off-by: Vivek Gautam
---
Changes since v1:
- Addressed Tomasz's comments for basing the change on
"NO_INNER_CACHE" concept for non-coherent I/O devices
rather than capturing
On Mon, Dec 3, 2018 at 7:56 PM Rob Clark wrote:
>
> On Mon, Dec 3, 2018 at 7:45 AM Robin Murphy wrote:
> >
> > Hi Rob,
> >
> > On 01/12/2018 16:53, Rob Clark wrote:
> > > This solves a problem we see with drm/msm, caused by getting
> > > iommu_dma_ops while we attach our own domain and manage it
Add bindings doc for Qcom's smmu-v2 implementation.
Signed-off-by: Vivek Gautam
Reviewed-by: Tomasz Figa
Tested-by: Srinivas Kandagatla
Reviewed-by: Rob Herring
Reviewed-by: Robin Murphy
---
Changes since v18:
None.
.../devicetree/bindings/iommu/arm,smmu.txt | 39
-off-by: Vivek Gautam
Reviewed-by: Tomasz Figa
Tested-by: Srinivas Kandagatla
Reviewed-by: Robin Murphy
---
Changes since v18:
None.
drivers/iommu/arm-smmu.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index 1917d214c4d9
1 - 100 of 343 matches
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