On Sat, Nov 01, 2014 at 02:38:26PM +0900, Alexandre Courbot wrote:
On Fri, Oct 31, 2014 at 10:27 PM, Thierry Reding
thierry.red...@gmail.com wrote:
On Thu, Oct 30, 2014 at 04:08:41PM +0100, Thierry Reding wrote:
On Wed, Oct 15, 2014 at 03:09:30PM -0700, Olof Johansson wrote:
Hi,
Oh,
On Mon, Nov 3, 2014 at 5:22 PM, Thierry Reding thierry.red...@gmail.com wrote:
On Sat, Nov 01, 2014 at 02:38:26PM +0900, Alexandre Courbot wrote:
On Fri, Oct 31, 2014 at 10:27 PM, Thierry Reding
thierry.red...@gmail.com wrote:
On Thu, Oct 30, 2014 at 04:08:41PM +0100, Thierry Reding wrote:
On Fri, Oct 31, 2014 at 10:27 PM, Thierry Reding
thierry.red...@gmail.com wrote:
On Thu, Oct 30, 2014 at 04:08:41PM +0100, Thierry Reding wrote:
On Wed, Oct 15, 2014 at 03:09:30PM -0700, Olof Johansson wrote:
Hi,
Oh, a few more comments:
On Mon, Oct 13, 2014 at 3:33 AM, Thierry Reding
On Thu, Oct 30, 2014 at 04:08:41PM +0100, Thierry Reding wrote:
On Wed, Oct 15, 2014 at 03:09:30PM -0700, Olof Johansson wrote:
Hi,
Oh, a few more comments:
On Mon, Oct 13, 2014 at 3:33 AM, Thierry Reding
thierry.red...@gmail.com wrote:
diff --git a/drivers/memory/Makefile
On 30.10.2014 12:03, Alexandre Courbot wrote:
I had to change the .reg of TEGRA_SWGROUP_GPU to 0xaac to get the IOMMU
to work with GK20A. The reason is still not completely clear to me, but
if you look at the TRM you see that 0xaa8 is basically constant, with
the SMMU translation bit hardcoded
On 30.10.2014 12:22, Alexandre Courbot wrote:
So should I understand that the GPU group is for addresses without bit
34 set (hence forcibly disabled) while GPUB is used when that bit is
set? Or is it something else?
That's exactly correct. And only GPUB can be programmed to be SMMU
translated.
diff --git a/drivers/memory/tegra/tegra124-mc.c
b/drivers/memory/tegra/tegra124-mc.c
...
+static const struct tegra_smmu_swgroup tegra124_swgroups[] = {
+ { .swgroup = TEGRA_SWGROUP_DC,.reg = 0x240 },
+ { .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 },
+ {
On 10/30/2014 08:04 PM, Terje Bergström wrote:
On 30.10.2014 12:22, Alexandre Courbot wrote:
So should I understand that the GPU group is for addresses without bit
34 set (hence forcibly disabled) while GPUB is used when that bit is
set? Or is it something else?
That's exactly correct. And
On 30.10.2014 15:35, Alexandre Courbot wrote:
Great, thanks for confirming!
Thierry, how do you want to address this? We could change the register
for the GPU group, or (maybe preferable if we want to reflect the actual
hardware state) add the GPUB group. I don't know if that would be easy
On Thu, Oct 30, 2014 at 7:18 PM, Terje Bergström tbergst...@nvidia.com
wrote:
On 30.10.2014 12:03, Alexandre Courbot wrote:
I had to change the .reg of TEGRA_SWGROUP_GPU to 0xaac to get the IOMMU
to work with GK20A. The reason is still not completely clear to me, but
if you look at the TRM
On Wed, Oct 15, 2014 at 03:09:30PM -0700, Olof Johansson wrote:
Hi,
Oh, a few more comments:
On Mon, Oct 13, 2014 at 3:33 AM, Thierry Reding
thierry.red...@gmail.com wrote:
diff --git a/drivers/memory/Makefile b/drivers/memory/Makefile
index c32d31981be3..1c932e7e7b8d 100644
---
On Wed, Oct 15, 2014 at 03:05:36PM -0700, Olof Johansson wrote:
Hi,
On Mon, Oct 13, 2014 at 3:33 AM, Thierry Reding
thierry.red...@gmail.com wrote:
[...]
diff --git a/drivers/memory/tegra/tegra-mc.c
b/drivers/memory/tegra/tegra-mc.c
new file mode 100644
index
Hi,
On Mon, Oct 13, 2014 at 3:33 AM, Thierry Reding
thierry.red...@gmail.com wrote:
[...]
diff --git a/drivers/memory/tegra/tegra-mc.c b/drivers/memory/tegra/tegra-mc.c
new file mode 100644
index ..0f0c8be096d0
--- /dev/null
+++ b/drivers/memory/tegra/tegra-mc.c
@@ -0,0 +1,1061
Hi,
Oh, a few more comments:
On Mon, Oct 13, 2014 at 3:33 AM, Thierry Reding
thierry.red...@gmail.com wrote:
diff --git a/drivers/memory/Makefile b/drivers/memory/Makefile
index c32d31981be3..1c932e7e7b8d 100644
--- a/drivers/memory/Makefile
+++ b/drivers/memory/Makefile
@@ -12,4 +12,5 @@
From: Thierry Reding tred...@nvidia.com
The memory controller on NVIDIA Tegra exposes various knobs that can be
used to tune the behaviour of the clients attached to it.
Currently this driver sets up the latency allowance registers to the HW
defaults. Eventually an API should be exported by this
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