This patch provides the test application for DMA_MAP_BENCHMARK.
Before running the test application, we need to bind a device to dma_map_
benchmark driver. For example, unbind "xxx" from its original driver and
bind to dma_map_benchmark:
echo dma_map_benchmark > /sys/bus/platform/devices/xxx/driv
Nowadays, there are increasing requirements to benchmark the performance
of dma_map and dma_unmap particually while the device is attached to an
IOMMU.
This patch enables the support. Users can run specified number of threads
to do dma_map_page and dma_unmap_page on a specific NUMA node with the
s
Nowadays, there are increasing requirements to benchmark the performance
of dma_map and dma_unmap particually while the device is attached to an
IOMMU.
This patchset provides the benchmark infrastruture for streaming DMA
mapping. The architecture of the code is pretty much similar with GUP
benchma
On 02/11/2020 08:06, Barry Song wrote:
Nowadays, there are increasing requirements to benchmark the performance
of dma_map and dma_unmap particually while the device is attached to an
IOMMU.
This patch enables the support. Users can run specified number of threads
to do dma_map_page and dma_unma
> -Original Message-
> From: John Garry
> Sent: Monday, November 2, 2020 10:19 PM
> To: Song Bao Hua (Barry Song) ;
> iommu@lists.linux-foundation.org; h...@lst.de; robin.mur...@arm.com;
> m.szyprow...@samsung.com
> Cc: linux-kselft...@vger.kernel.org; Shuah Khan ; Joerg
> Roedel ; Linux
Hi,
Please check out https://bugzilla.kernel.org/show_bug.cgi?id=209857, thanks!
Regards,
Tom
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Hi Linus,
On Sat, Oct 31, 2020 at 8:51 PM Linus Torvalds
wrote:
> On Sat, Oct 31, 2020 at 2:40 AM Christoph Hellwig wrote:
> > dma-mapping fix for 5.10:
> >
> > - fix an integer overflow on 32-bit platforms in the new DMA range code
> >(Geert Uytterhoeven)
>
> So this is just a stylistic ni
On 02/11/2020 02:00, Lu Baolu wrote:
Hi Tvrtko,
On 10/12/20 4:44 PM, Tvrtko Ursulin wrote:
On 29/09/2020 01:11, Lu Baolu wrote:
Hi Tvrtko,
On 9/28/20 5:44 PM, Tvrtko Ursulin wrote:
On 27/09/2020 07:34, Lu Baolu wrote:
Hi,
The previous post of this series could be found here.
https://lor
On Thu, Oct 29, 2020 at 05:26:08PM +, Will Deacon wrote:
> On Tue, Oct 27, 2020 at 04:34:04PM -0600, Jordan Crouse wrote:
> > This short series adds support for the adreno-smmu implementation of the
> > arm-smmu driver and the device-tree bindings to turn on the implementation
> > for the sm845
Add a special implementation for the SMMU attached to most Adreno GPU
target triggered from the qcom,adreno-smmu compatible string.
The new Adreno SMMU implementation will enable split pagetables
(TTBR1) for the domain attached to the GPU device (SID 0) and
hard code it context bank 0 so the GPU h
From: Rob Clark
For the Adreno GPU's SMMU, we want SCTLR.HUPCF set to ensure that
pending translations are not terminated on iova fault. Otherwise
a terminated CP read could hang the GPU by returning invalid
command-stream data.
Signed-off-by: Rob Clark
Reviewed-by: Bjorn Andersson
Signed-off
Set the qcom,adreno-smmu compatible string for the GPU SMMU to enable
split pagetables and per-instance pagetables for drm/msm.
Signed-off-by: Jordan Crouse
Signed-off-by: Rob Clark
Reviewed-by: Bjorn Andersson
---
arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi | 9 +
arch/arm64/boot/dts/
Every Qcom Adreno GPU has an embedded SMMU for its own use. These
devices depend on unique features such as split pagetables,
different stall/halt requirements and other settings. Identify them
with a compatible string so that they can be identified in the
arm-smmu implementation specific code.
Si
(resend with expanded CC list so everybody can see all the patches)
This short series adds support for the adreno-smmu implementation of the
arm-smmu driver and the device-tree bindings to turn on the implementation
for the sm845 and sc7180 GPUs. These changes are the last ones needed to enable
pe
On Mon, Nov 02, 2020 at 10:08:23AM -0700, Jordan Crouse wrote:
> On Thu, Oct 29, 2020 at 05:26:08PM +, Will Deacon wrote:
> > On Tue, Oct 27, 2020 at 04:34:04PM -0600, Jordan Crouse wrote:
> > > This short series adds support for the adreno-smmu implementation of the
> > > arm-smmu driver and t
On 2020-11-02 17:14, Jordan Crouse wrote:
Add a special implementation for the SMMU attached to most Adreno GPU
target triggered from the qcom,adreno-smmu compatible string.
The new Adreno SMMU implementation will enable split pagetables
(TTBR1) for the domain attached to the GPU device (SID 0)
On 2020-11-02 17:14, Jordan Crouse wrote:
From: Rob Clark
For the Adreno GPU's SMMU, we want SCTLR.HUPCF set to ensure that
pending translations are not terminated on iova fault. Otherwise
a terminated CP read could hang the GPU by returning invalid
command-stream data.
Signed-off-by: Rob Cla
On 2020-11-02 17:14, Jordan Crouse wrote:
Every Qcom Adreno GPU has an embedded SMMU for its own use. These
devices depend on unique features such as split pagetables,
different stall/halt requirements and other settings. Identify them
with a compatible string so that they can be identified in th
On 2020-11-02 18:22, Robin Murphy wrote:
On 2020-11-02 17:14, Jordan Crouse wrote:
Every Qcom Adreno GPU has an embedded SMMU for its own use. These
devices depend on unique features such as split pagetables,
different stall/halt requirements and other settings. Identify them
with a compatible s
On Thu, Oct 29, 2020 at 12:26 PM Nicolas Saenz Julienne
wrote:
>
> Introduce of_dma_get_max_cpu_address(), which provides the highest CPU
> physical address addressable by all DMA masters in the system. It's
> specially useful for setting memory zones sizes at early boot time.
>
> Signed-off-by: N
Hi Jean-Philippe,
On Fri, 30 Oct 2020 11:18:27 +0100, Jean-Philippe Brucker
wrote:
> On Mon, Oct 26, 2020 at 02:05:06PM -0700, Jacob Pan wrote:
> > > This looks good to me, with small comments below.
> > >
> > Can I add your Reviewed-by tag after addressing the comments?
>
> Yes sure, this
On 11/2/20 7:52 PM, Tvrtko Ursulin wrote:
On 02/11/2020 02:00, Lu Baolu wrote:
Hi Tvrtko,
On 10/12/20 4:44 PM, Tvrtko Ursulin wrote:
On 29/09/2020 01:11, Lu Baolu wrote:
Hi Tvrtko,
On 9/28/20 5:44 PM, Tvrtko Ursulin wrote:
On 27/09/2020 07:34, Lu Baolu wrote:
Hi,
The previous post of th
Hi Robin,
Recently, I have read and learned the code related to io-pgtable-arm.c.
There
are two question on arm_lpae_install_table.
1、the first
static arm_lpae_iopte arm_lpae_install_table(arm_lpae_iopte *table,
arm_lpae_iopte *ptep,
Hi Alex,
On 10/31/20 5:06 AM, Alex Williamson wrote:
On Fri, 30 Oct 2020 06:16:28 +
"Tian, Kevin" wrote:
From: Lu Baolu
Sent: Friday, October 30, 2020 12:58 PM
With the IOMMU driver registering iommu_ops for the mdev_bus, the
IOMMU
operations on an mdev could be done in the same way as
Convert MediaTek SMI to DT schema.
Signed-off-by: Yong Wu
---
.../mediatek,smi-common.txt | 50 ---
.../mediatek,smi-common.yaml | 140 ++
.../memory-controllers/mediatek,smi-larb.txt | 50 ---
.../memory-controllers/mediatek,smi-larb
This patchset mainly adds SMI support for mt8192.
It comes from the patchset[1]. I seperate the smi part into this patchset.
And the two part(IOMMU/SMI) patchset don't depend on each other.
Rebase on v5.10-rc1.
changenote:
v5: Fix complain from yamllint.
v4:
https://lore.kernel.org/linux-med
Add mt8192 smi support in the bindings.
Signed-off-by: Yong Wu
Reviewed-by: Rob Herring
---
.../bindings/memory-controllers/mediatek,smi-common.yaml | 4 +++-
.../bindings/memory-controllers/mediatek,smi-larb.yaml| 2 ++
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git
Add mt8192 smi support.
Signed-off-by: Yong Wu
---
drivers/memory/mtk-smi.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c
index 691e4c344cf8..ac350f8d1e20 100644
--- a/drivers/memory/mtk-smi.c
+++ b/drivers/memory/mtk
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