From: Suravee Suthikulpanit
This patch series modifies the existing IOMMU and Perf drivers to support
systems with multiple IOMMUs by allocating an amd_iommu PMU per IOMMU instance.
This allows users to specify performance events and filters separately for each
IOMMU.
This has been tested on
This patch contains the following minor fixup:
* Fixed overflow handling since u64 delta would lose the MSB sign bit.
* Remove unnecessary local64_set().
* Coding style and make use of GENMASK_ULL macro.
Cc: Peter Zijlstra
Cc: Borislav Petkov
Signed-off-by: Suravee Suthikulpanit
, and will use proper IOMMU index.
Cc: Peter Zijlstra
Cc: Borislav Petkov
Cc: Joerg Roedel
Signed-off-by: Suravee Suthikulpanit
---
arch/x86/events/amd/iommu.c | 17 +++--
arch/x86/events/amd/iommu.h | 7 ++-
drivers/iommu/amd_iommu_init.c | 35
Zijlstra
Cc: Borislav Petkov
Signed-off-by: Suravee Suthikulpanit
---
arch/x86/events/amd/iommu.c | 119
1 file changed, 64 insertions(+), 55 deletions(-)
diff --git a/arch/x86/events/amd/iommu.c b/arch/x86/events/amd/iommu.c
index 2403c78..5fd97b5
This patch introduces amd_iommu_get_num_iommus(). This is intended for
Perf AMD IOMMU driver.
Cc: Joerg Roedel
Signed-off-by: Suravee Suthikulpanit
---
arch/x86/events/amd/iommu.h | 2 ++
drivers/iommu/amd_iommu_init.c | 7 ++-
drivers/iommu/amd_iommu_proto.h | 1 +
3 files changed, 9
This patch declare pr_fmt for perf/amd_iommu and remove unnecessary
pr_debug.
Cc: Peter Zijlstra
Cc: Borislav Petkov
Signed-off-by: Suravee Suthikulpanit
---
arch/x86/events/amd/iommu.c | 12
1 file changed, 4 insertions(+), 8 deletions(-)
diff --git a/arch/x86/events/amd
driver for supporting multi-IOMMU in subsequent patch.
Cc: Peter Zijlstra
Cc: Borislav Petkov
Cc: Joerg Roedel
Signed-off-by: Suravee Suthikulpanit
---
arch/x86/events/amd/iommu.c | 45 +++-
arch/x86/events/amd/iommu.h | 8 +++--
drivers/iommu/amd_iommu_init.c | 77
This patch cleans up:
* Various bitwise operations in perf_iommu_enable_event
* Make use macros BIT(x)
This should not affect logic and functionality.
Cc: Peter Zijlstra
Cc: Borislav Petkov
Signed-off-by: Suravee Suthikulpanit
---
arch/x86/events/amd/iommu.c | 12 ++--
1 file
On 1/4/17 21:48, Joerg Roedel wrote:
On Fri, Dec 23, 2016 at 08:38:45PM +0700, Suravee Suthikulpanit wrote:
--- a/arch/x86/events/amd/iommu.h
+++ b/arch/x86/events/amd/iommu.h
@@ -24,15 +24,12 @@
#define PC_MAX_SPEC_BNKS 64
#define PC_MAX_SPEC_CNTRS
driver for supporting multi-IOMMU in subsequent patch.
This patch also removes unnecessary function declarations in
amd_iommu_proto.h.
Cc: Peter Zijlstra
Cc: Borislav Petkov
Cc: Joerg Roedel
Signed-off-by: Suravee Suthikulpanit
---
arch/x86/events/amd/iommu.c | 45
, and will use proper IOMMU index.
This patch also removes unnecessary function declaration in
amd_iommu_proto.h.
Cc: Peter Zijlstra
Cc: Borislav Petkov
Cc: Joerg Roedel
Signed-off-by: Suravee Suthikulpanit
---
arch/x86/events/amd/iommu.c | 17 +++--
arch/x86/events/amd/iommu.h
From: Suravee Suthikulpanit
This patch series modifies the existing IOMMU and Perf drivers to support
systems with multiple IOMMUs by allocating an amd_iommu PMU per IOMMU instance.
This allows users to specify performance events and filters separately for each
IOMMU.
This has been tested on
Zijlstra
Cc: Borislav Petkov
Signed-off-by: Suravee Suthikulpanit
---
arch/x86/events/amd/iommu.c | 119
1 file changed, 64 insertions(+), 55 deletions(-)
diff --git a/arch/x86/events/amd/iommu.c b/arch/x86/events/amd/iommu.c
index 2403c78..5fd97b5
This patch contains the following minor fixup:
* Fixed overflow handling since u64 delta would lose the MSB sign bit.
* Remove unnecessary local64_set().
* Coding style and make use of GENMASK_ULL macro.
Cc: Peter Zijlstra
Cc: Borislav Petkov
Signed-off-by: Suravee Suthikulpanit
This patch declare pr_fmt for perf/amd_iommu and remove unnecessary
pr_debug.
Cc: Peter Zijlstra
Cc: Borislav Petkov
Signed-off-by: Suravee Suthikulpanit
---
arch/x86/events/amd/iommu.c | 12
1 file changed, 4 insertions(+), 8 deletions(-)
diff --git a/arch/x86/events/amd
This patch cleans up:
* Various bitwise operations in perf_iommu_enable_event
* Make use macros BIT(x)
This should not affect logic and functionality.
Cc: Peter Zijlstra
Cc: Borislav Petkov
Signed-off-by: Suravee Suthikulpanit
---
arch/x86/events/amd/iommu.c | 12 ++--
1 file
This patch introduces amd_iommu_get_num_iommus(). This is intended for
Perf AMD IOMMU driver.
Cc: Joerg Roedel
Signed-off-by: Suravee Suthikulpanit
---
arch/x86/events/amd/iommu.h| 2 ++
drivers/iommu/amd_iommu_init.c | 7 ++-
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git
On 1/10/17 21:43, Joerg Roedel wrote:
On Mon, Jan 09, 2017 at 09:33:42PM -0600, Suthikulpanit, Suravee wrote:
+static struct amd_iommu *get_amd_iommu(uint idx)
+{
+ uint i = 0;
+ struct amd_iommu *iommu = NULL;
+
+ for_each_iommu(iommu) {
+ if (i == idx)
+
, and will use proper IOMMU index.
This patch also removes unnecessary function declaration in
amd_iommu_proto.h.
Cc: Peter Zijlstra
Cc: Borislav Petkov
Cc: Joerg Roedel
Signed-off-by: Suravee Suthikulpanit
---
NOTE: This contains the fix in get_amd_iommu() as suggested by Joerg.
arch/x86
Boris,
On 1/13/17 00:52, Borislav Petkov wrote:
On Mon, Jan 09, 2017 at 09:33:47PM -0600, Suravee Suthikulpanit wrote:
This patch adds multi-IOMMU support for perf by exposing
an AMD IOMMU PMU for each IOMMU found in the system via:
/sys/device/amd_iommu_x /* where x is the IOMMU index
On 1/13/17 18:49, Borislav Petkov wrote:
On Fri, Jan 13, 2017 at 05:24:01PM +0700, Suravee Suthikulpanit wrote:
IIUC, Perf tools looks at the /sys/devices/x to identify
availalble PMUs. Are you planning to have perf tools look at
/sys/devices/system/iommu/xxx instead?
No, I'm pla
On 1/12/17 17:19, Borislav Petkov wrote:
Also, looking at that driver more, this needs to die, like now:
#define format_groupattr_groups[0]
#define cpumask_group attr_groups[1]
#define events_groupattr_groups[2]
#define null_group attr_groups[3]
Like, kill it dead. Define a sep
Peter,
On 1/11/17 18:57, Peter Zijlstra wrote:
On Mon, Jan 09, 2017 at 09:33:41PM -0600, Suravee Suthikulpanit wrote:
This patch contains the following minor fixup:
* Fixed overflow handling since u64 delta would lose the MSB sign bit.
Please explain.. afaict this actually introduces a bug
Declare pr_fmt for perf/amd_iommu and remove unnecessary pr_debug.
Also check return value when _init_events_attrs fails.
Cc: Peter Zijlstra
Cc: Borislav Petkov
Signed-off-by: Suravee Suthikulpanit
---
arch/x86/events/amd/iommu.c | 20
1 file changed, 8 insertions(+), 12
From: Suravee Suthikulpanit
* Clean up various bitwise operations in perf_iommu_enable_event
* Make use macros BIT(x)
This should not affect logic and functionality.
Cc: Peter Zijlstra
Cc: Borislav Petkov
Signed-off-by: Suravee Suthikulpanit
---
arch/x86/events/amd/iommu.c | 18
From: Suravee Suthikulpanit
This patch series modifies the existing IOMMU and Perf drivers to support
systems with multiple IOMMUs by allocating an amd_iommu PMU per IOMMU instance.
This allows users to specify performance events and filters separately for each
IOMMU.
This has been tested on
From: Suravee Suthikulpanit
In, perf_iommu_start(), we need to check the return value from
amd_iommu_set_reg(). In case of failure, we should not enable the PMU.
Also, in perf_iommu_read(), we need to check the return value from
amd_iommu_get_reg() before using the value.
Cc: Peter Zijlstra
Introduce amd_iommu_get_num_iommus(), which returns the value of
amd_iommus_present, then replaces the direct access to the variable
which is now declared as static.
This function will also be used by Perf AMD IOMMU driver.
Cc: Borislav Petkov
Cc: Joerg Roedel
Signed-off-by: Suravee
, and will use proper IOMMU index.
This patch also removes unnecessary function declaration in
amd_iommu_proto.h.
Cc: Peter Zijlstra
Cc: Borislav Petkov
Cc: Joerg Roedel
Signed-off-by: Suravee Suthikulpanit
---
arch/x86/events/amd/iommu.c | 17 +++--
arch/x86/events/amd/iommu.h
From: Suravee Suthikulpanit
Introduce static amd_iommu_attr_groups to simplify the
sysfs attributes initialization code.
Cc: Peter Zijlstra
Cc: Borislav Petkov
Signed-off-by: Suravee Suthikulpanit
---
arch/x86/events/amd/iommu.c | 85 -
1 file
* Fix overflow handling since u64 delta would lose the MSB sign bit.
* Remove unnecessary local64_cmpxchg().
* Coding style and make use of GENMASK_ULL macro.
Cc: Peter Zijlstra
Cc: Borislav Petkov
Signed-off-by: Suravee Suthikulpanit
---
arch/x86/events/amd/iommu.c | 23
From: Suravee Suthikulpanit
Add multi-IOMMU support for perf by exposing an AMD IOMMU PMU
for each IOMMU found in the system via:
/bus/event_source/devices/amd_iommu_x
where x is the IOMMU index. This allows users to specify
different events to be programed onto performance counters
of each
From: Suravee Suthikulpanit
The current amd_iommu_pc_get_set_reg_val() cannot support multiple IOMMUs
It is also confusing since it is trying to support set and get in
one function.
So break it down to amd_iommu_pc_[get|set]_reg(),
and modifies them to allow callers to specify IOMMU index. This
Boris,
On 1/23/17 02:55, Borislav Petkov wrote:
@@ -421,46 +427,46 @@ static __init void amd_iommu_pc_exit(void)
};
static __init int
-_init_perf_amd_iommu(struct perf_amd_iommu *perf_iommu, char *name)
+init_one_perf_amd_iommu(struct perf_amd_iommu *perf_iommu, unsigned int idx)
{
i
Peter,
On 1/25/17 16:46, Peter Zijlstra wrote:
On Mon, Jan 16, 2017 at 01:23:36AM -0600, Suravee Suthikulpanit wrote:
+ pi = container_of(event->pmu, struct perf_amd_iommu, pmu);
+ hwc->idx = pi->idx;
+ hwc->config = event->attr.conf
Boris,
On 1/25/17 16:55, Borislav Petkov wrote:
On Wed, Jan 25, 2017 at 10:46:53AM +0100, Peter Zijlstra wrote:
Which is absolutely insane.
Right,
IMO, the simplest thing to do for your purposes is to embed a struct
amd_iommu pointer into struct perf_amd_iommu at init time so that you
don't
Peter,
On 1/23/17 19:33, Peter Zijlstra wrote:
On Mon, Jan 16, 2017 at 01:23:30AM -0600, Suravee Suthikulpanit wrote:
static void perf_iommu_read(struct perf_event *event)
{
- u64 count = 0ULL;
- u64 prev_raw_count = 0ULL;
- u64 delta = 0ULL;
+ u64 count, prev
From: Suravee Suthikulpanit
Clean up register initialization and make use of BIT_ULL(x)
where appropriate. This should not affect logic and functionality.
Cc: Peter Zijlstra
Cc: Borislav Petkov
Signed-off-by: Suravee Suthikulpanit
---
arch/x86/events/amd/iommu.c | 18 +-
1
From: Suravee Suthikulpanit
The current amd_iommu_pc_get_set_reg_val() cannot support multiple IOMMUs.
So, modify it to allow callers to specify IOMMU. This prepares the driver
for supporting multi-IOMMU in subsequent patch.
Cc: Peter Zijlstra
Cc: Borislav Petkov
Cc: Joerg Roedel
Signed-off
From: Suravee Suthikulpanit
This patch series modifies the existing IOMMU and Perf drivers to support
systems with multiple IOMMUs by allocating an amd_iommu PMU per IOMMU instance.
This allows users to specify performance events and filters separately for each
IOMMU.
This has been tested on
Fix coding style and make use of GENMASK_ULL macro.
Cc: Peter Zijlstra
Cc: Borislav Petkov
Cc: Joerg Roedel
Signed-off-by: Suravee Suthikulpanit
---
arch/x86/events/amd/iommu.c | 16 ++--
1 file changed, 6 insertions(+), 10 deletions(-)
diff --git a/arch/x86/events/amd/iommu.c b
Declare pr_fmt for perf/amd_iommu and remove unnecessary pr_debug.
Also check return value when _init_events_attrs fails.
Cc: Peter Zijlstra
Cc: Borislav Petkov
Signed-off-by: Suravee Suthikulpanit
---
arch/x86/events/amd/iommu.c | 20
1 file changed, 8 insertions(+), 12
will use a proper IOMMU index.
Cc: Peter Zijlstra
Cc: Borislav Petkov
Cc: Joerg Roedel
Signed-off-by: Suravee Suthikulpanit
---
arch/x86/events/amd/iommu.c | 17 +++--
arch/x86/events/amd/iommu.h | 9 -
drivers/iommu/amd_iommu_init.c | 37
: Suravee Suthikulpanit
---
arch/x86/events/amd/iommu.h | 2 ++
drivers/iommu/amd_iommu.c | 6 +++---
drivers/iommu/amd_iommu_init.c | 11 +--
drivers/iommu/amd_iommu_proto.h | 1 +
drivers/iommu/amd_iommu_types.h | 3 ---
5 files changed, 15 insertions(+), 8 deletions(-)
diff
From: Suravee Suthikulpanit
Introduce static amd_iommu_attr_groups to simplify the
sysfs attributes initialization code.
Cc: Peter Zijlstra
Cc: Borislav Petkov
Signed-off-by: Suravee Suthikulpanit
---
arch/x86/events/amd/iommu.c | 81 ++---
1 file
From: Suravee Suthikulpanit
Add multi-IOMMU support for perf by exposing an AMD IOMMU PMU
for each IOMMU found in the system via:
/bus/event_source/devices/amd_iommu_x
where x is the IOMMU index. This allows users to specify
different events to be programmed onto performance counters
of each
Boris,
On 2/9/17 02:33, Borislav Petkov wrote:
On Tue, Feb 07, 2017 at 02:40:36AM -0600, Suravee Suthikulpanit wrote:
From: Suravee Suthikulpanit
[..]
+ perf_iommu->max_banks= amd_iommu_pc_get_max_banks(idx);
+ perf_iommu->max_counters = amd_iommu_pc_get_max_counte
Declare pr_fmt for perf/amd_iommu and remove unnecessary pr_debug.
Also check return value when _init_events_attrs fails.
Cc: Peter Zijlstra
Cc: Borislav Petkov
Signed-off-by: Suravee Suthikulpanit
---
arch/x86/events/amd/iommu.c | 20
1 file changed, 8 insertions(+), 12
From: Suravee Suthikulpanit
This patch series modifies the existing IOMMU and Perf drivers to support
systems with multiple IOMMUs by allocating an amd_iommu PMU per IOMMU instance.
This allows users to specify performance events and filters separately for each
IOMMU.
This has been tested on
From: Suravee Suthikulpanit
Clean up coding style and fix a bug in the 64-bit register read
logic since it overwrites the upper 32-bit when reading the lower 32-bit.
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd_iommu_init.c | 13 -
1 file changed, 8 insertions(+), 5
Fix coding style and make use of GENMASK_ULL macro.
Cc: Peter Zijlstra
Cc: Borislav Petkov
Cc: Joerg Roedel
Signed-off-by: Suravee Suthikulpanit
---
arch/x86/events/amd/iommu.c | 16 ++--
1 file changed, 6 insertions(+), 10 deletions(-)
diff --git a/arch/x86/events/amd/iommu.c b
: Suravee Suthikulpanit
---
arch/x86/events/amd/iommu.h | 2 ++
drivers/iommu/amd_iommu.c | 6 +++---
drivers/iommu/amd_iommu_init.c | 11 +--
drivers/iommu/amd_iommu_proto.h | 1 +
drivers/iommu/amd_iommu_types.h | 3 ---
5 files changed, 15 insertions(+), 8 deletions(-)
diff
From: Suravee Suthikulpanit
Clean up register initializaton and make use of BIT_ULL(x)
where appropriate. This should not affect logic and functionality.
Cc: Peter Zijlstra
Cc: Borislav Petkov
Signed-off-by: Suravee Suthikulpanit
---
arch/x86/events/amd/iommu.c | 18 +-
1
will use a proper IOMMU index.
Cc: Peter Zijlstra
Cc: Borislav Petkov
Cc: Joerg Roedel
Signed-off-by: Suravee Suthikulpanit
---
arch/x86/events/amd/iommu.c | 17 +++--
arch/x86/events/amd/iommu.h | 9 -
drivers/iommu/amd_iommu_init.c | 34
From: Suravee Suthikulpanit
The current amd_iommu_pc_get_set_reg_val() cannot support multiple IOMMUs.
So, modify it to allow callers to specify IOMMU. This prepares the driver
for supporting multi-IOMMU in subsequent patch.
Cc: Peter Zijlstra
Cc: Borislav Petkov
Cc: Joerg Roedel
Signed-off
From: Suravee Suthikulpanit
Add multi-IOMMU support for perf by exposing an AMD IOMMU PMU
for each IOMMU found in the system via:
/bus/event_source/devices/amd_iommu_x
where x is the IOMMU index. This allows users to specify
different events to be programmed onto performance counters
of each
From: Suravee Suthikulpanit
Introduce static amd_iommu_attr_groups to simplify the
sysfs attributes initialization code.
Cc: Peter Zijlstra
Cc: Borislav Petkov
Signed-off-by: Suravee Suthikulpanit
---
arch/x86/events/amd/iommu.c | 81 ++---
1 file
Peter,
On 2/14/17 19:31, Peter Zijlstra wrote:
On Tue, Feb 07, 2017 at 08:57:52AM +0700, Suravee Suthikulpanit wrote:
But instead it looks like you get the counter form:
#define _GET_CNTR(ev) ((u8)(ev->hw.extra_reg.reg))
Which is absolutely insane.
So, the IOMMU counters
On 2/24/17 01:11, Peter Zijlstra wrote:
However, I have looked into reworking to not use the extra_regs, and I see
that the union in struct hw_perf_event currently contains various PMU-specific
structures (hardware, software, tracepoint, intel_cqm, itrace, amd_power,
and breakpoint).
For amd_i
From: Suravee Suthikulpanit
Clean up coding style and fix a bug in the 64-bit register read
logic since it overwrites the upper 32-bit when reading the lower 32-bit.
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd_iommu_init.c | 13 -
1 file changed, 8 insertions(+), 5
From: Suravee Suthikulpanit
This patch series modifies the existing IOMMU and Perf drivers to support
systems with multiple IOMMUs by allocating an amd_iommu PMU per IOMMU instance.
This allows users to specify performance events and filters separately for each
IOMMU.
This has been tested on
Declare pr_fmt for perf/amd_iommu and remove unnecessary pr_debug.
Also check return value when _init_events_attrs fails.
Cc: Peter Zijlstra
Cc: Borislav Petkov
Signed-off-by: Suravee Suthikulpanit
---
arch/x86/events/amd/iommu.c | 22 +-
1 file changed, 9 insertions
: Suravee Suthikulpanit
---
arch/x86/events/amd/iommu.h | 2 ++
drivers/iommu/amd_iommu.c | 6 +++---
drivers/iommu/amd_iommu_init.c | 11 +--
drivers/iommu/amd_iommu_proto.h | 1 +
drivers/iommu/amd_iommu_types.h | 3 ---
5 files changed, 15 insertions(+), 8 deletions(-)
diff
will use a proper IOMMU index.
Cc: Peter Zijlstra
Cc: Borislav Petkov
Cc: Joerg Roedel
Signed-off-by: Suravee Suthikulpanit
---
arch/x86/events/amd/iommu.c | 17 +++--
arch/x86/events/amd/iommu.h | 9 -
drivers/iommu/amd_iommu_init.c | 34
From: Suravee Suthikulpanit
Clean up register initializaton and make use of BIT_ULL(x)
where appropriate. This should not affect logic and functionality.
Cc: Peter Zijlstra
Cc: Borislav Petkov
Signed-off-by: Suravee Suthikulpanit
---
arch/x86/events/amd/iommu.c | 18 +-
1
From: Suravee Suthikulpanit
The current amd_iommu_pc_get_set_reg_val() cannot support multiple IOMMUs.
So, modify it to allow callers to specify IOMMU. This prepares the driver
for supporting multi-IOMMU in subsequent patch.
Cc: Peter Zijlstra
Cc: Borislav Petkov
Cc: Joerg Roedel
Signed-off
Fix coding style and make use of GENMASK_ULL macro.
Cc: Peter Zijlstra
Cc: Borislav Petkov
Cc: Joerg Roedel
Signed-off-by: Suravee Suthikulpanit
---
arch/x86/events/amd/iommu.c | 16 ++--
1 file changed, 6 insertions(+), 10 deletions(-)
diff --git a/arch/x86/events/amd/iommu.c b
From: Suravee Suthikulpanit
Current AMD IOMMU Perf PMU inappropriately uses hardware struct
inside the union inside the struct hw_perf_event, mainly the use of
extra_reg.
Instead, introduce amd_iommu-specific struct with required
parameters to be programmed onto the IOMMU performance counter
From: Suravee Suthikulpanit
Introduce static amd_iommu_attr_groups to simplify the
sysfs attributes initialization code.
Cc: Peter Zijlstra
Cc: Borislav Petkov
Signed-off-by: Suravee Suthikulpanit
---
arch/x86/events/amd/iommu.c | 81 ++---
1 file
From: Suravee Suthikulpanit
Add multi-IOMMU support for perf by exposing an AMD IOMMU PMU
for each IOMMU found in the system via:
/bus/event_source/devices/amd_iommu_x
where x is the IOMMU index. This allows users to specify
different events to be programmed onto performance counters
of each
From: Suravee Suthikulpanit
This patch series modifies the existing IOMMU and Perf drivers to support
systems with multiple IOMMUs by allocating an amd_iommu PMU per IOMMU instance.
This allows users to specify performance events and filters separately for each
IOMMU.
This has been tested on
Fix coding style and make use of GENMASK_ULL macro.
Cc: Peter Zijlstra
Cc: Borislav Petkov
Cc: Joerg Roedel
Signed-off-by: Suravee Suthikulpanit
---
arch/x86/events/amd/iommu.c | 16 ++--
1 file changed, 6 insertions(+), 10 deletions(-)
diff --git a/arch/x86/events/amd/iommu.c b
Declare pr_fmt for perf/amd_iommu and remove unnecessary pr_debug.
Also check return value when _init_events_attrs fails.
Cc: Peter Zijlstra
Cc: Borislav Petkov
Signed-off-by: Suravee Suthikulpanit
---
arch/x86/events/amd/iommu.c | 22 +-
1 file changed, 9 insertions
From: Suravee Suthikulpanit
Clean up register initializaton and make use of BIT_ULL(x)
where appropriate. This should not affect logic and functionality.
Cc: Peter Zijlstra
Cc: Borislav Petkov
Signed-off-by: Suravee Suthikulpanit
---
arch/x86/events/amd/iommu.c | 18 +-
1
From: Suravee Suthikulpanit
Clean up coding style and fix a bug in the 64-bit register read
logic since it overwrites the upper 32-bit when reading the lower 32-bit.
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd_iommu_init.c | 13 -
1 file changed, 8 insertions(+), 5
From: Suravee Suthikulpanit
Current AMD IOMMU Perf PMU inappropriately uses hardware struct
inside the union inside the struct hw_perf_event, mainly the use of
extra_reg.
Instead, introduce amd_iommu-specific struct with required
parameters to be programmed onto the IOMMU performance counter
From: Suravee Suthikulpanit
The current amd_iommu_pc_get_set_reg_val() cannot support multiple IOMMUs.
So, modify it to allow callers to specify IOMMU. This prepares the driver
for supporting multi-IOMMU in subsequent patch.
Cc: Peter Zijlstra
Cc: Borislav Petkov
Cc: Joerg Roedel
Signed-off
will use a proper IOMMU index.
Cc: Peter Zijlstra
Cc: Borislav Petkov
Cc: Joerg Roedel
Signed-off-by: Suravee Suthikulpanit
---
arch/x86/events/amd/iommu.c | 17 +++--
arch/x86/events/amd/iommu.h | 9 -
drivers/iommu/amd_iommu_init.c | 34
From: Suravee Suthikulpanit
Add multi-IOMMU support for perf by exposing an AMD IOMMU PMU
for each IOMMU found in the system via:
/bus/event_source/devices/amd_iommu_x
where x is the IOMMU index. This allows users to specify
different events to be programmed onto performance counters
of each
From: Suravee Suthikulpanit
Introduce static amd_iommu_attr_groups to simplify the
sysfs attributes initialization code.
Cc: Peter Zijlstra
Cc: Borislav Petkov
Signed-off-by: Suravee Suthikulpanit
---
arch/x86/events/amd/iommu.c | 81 ++---
1 file
: Suravee Suthikulpanit
---
arch/x86/events/amd/iommu.h | 2 ++
drivers/iommu/amd_iommu.c | 6 +++---
drivers/iommu/amd_iommu_init.c | 11 +--
drivers/iommu/amd_iommu_proto.h | 1 +
drivers/iommu/amd_iommu_types.h | 3 ---
5 files changed, 15 insertions(+), 8 deletions(-)
diff
, the guest_mode bit should be set and cleared only when
SVM updates posted-interrupt information via irq_set_vcpu_affinity().
Signed-off-by: Suravee Suthikulpanit
Cc: Joerg Roedel
---
drivers/iommu/amd_iommu.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers
invalid interrupt remapping.
Also, the guest_mode bit should be set and cleared only when
SVM updates posted-interrupt interrupt remapping information.
Signed-off-by: Suravee Suthikulpanit
Cc: Joerg Roedel
---
Changes in v2:
* Fix compiler warning of unused variable 'dev_data' in
irte_
On 6/25/17 12:55, Nick Sarnie wrote:
On Fri, May 5, 2017 at 1:27 PM, Alex Williamson
wrote:
On Wed, 3 May 2017 12:28:35 -0400
Nick Sarnie wrote:
On Wed, May 3, 2017 at 10:37 AM, Matthias Ehrenfeuchter wrote:
Hi,
There are a lot of messages/threads out there about bad performance while
u
On 6/29/17 00:26, Steven Walter wrote:
So, I'm trying to reproduce this issue on the Ryzen system w/ the following
setup:
* Host kernel v4.11 (with this patch https://lkml.org/lkml/2017/6/23/295)
* guest VM RHEL7.3
* guest graphic driver = radeon
* qemu-system-x86_64 --version
Q
On 6/28/17 19:44, Joerg Roedel wrote:
On Mon, Jun 26, 2017 at 04:28:04AM -0500, Suravee Suthikulpanit wrote:
Pass-through devices to VM guest can get updated IRQ affinity
information via irq_set_affinity() when not running in guest mode.
Currently, AMD IOMMU driver in GA mode ignores the
IRTE[GALogIntr] bit should set when enabling guest_mode, which enables
IOMMU to generate entry in GALog when IRTE[IsRun] is not set, and send
an interrupt to notify IOMMU driver.
Signed-off-by: Suravee Suthikulpanit
Cc: Joerg Roedel
Fixes: d98de49a53e48 ('iommu/amd: Enable vAPIC inte
On 1/23/2013 1:06 AM, Joerg Roedel wrote:
On Tue, Jan 22, 2013 at 05:19:10PM -0600, Suthikulpanit, Suravee wrote:
From: Suravee Suthikulpanit
@@ -1171,6 +1195,8 @@ static int iommu_init_pci(struct amd_iommu *iommu)
for (i = 0; i < 0x83; i++)
io
On 4/2/2013 10:29 AM, Borislav Petkov wrote:
On Tue, Apr 02, 2013 at 05:03:04PM +0200, Joerg Roedel wrote:
On Tue, Apr 02, 2013 at 04:40:37PM +0200, Borislav Petkov wrote:
While you guys are at it, can someone fix this too pls (ASUS board with
a PD on it).
[0.220342] [Firmware Bug]: AMD-Vi
On 4/18/2013 1:35 PM, Joerg Roedel wrote:
On Thu, Apr 18, 2013 at 11:59:58AM -0500, Suthikulpanit, Suravee wrote:
One last concern I have for this patch is the case when we re-enable
the interrupt, then another interrupt happens while we processing
the log and set the bit. If the interrupt thre
This is the rework of the original patch set here:
http://lists.linuxfoundation.org/pipermail/iommu/2013-January/005075.html
These patches implement the AMD IOMMU Performance Counter functionality
via custom perf PMU and implement static counting for various IOMMU
translations.
1) Extend the
Ping
On 5/22/2013 2:15 PM, suravee.suthikulpa...@amd.com wrote:
From: Suravee Suthikulpanit
This patch set implements framework for handling errors reported via IOMMU
event log. It also implements mechanism to filter/suppress error messages when
IOMMU hardware generates large amount event
On 6/17/2013 6:09 AM, Peter Zijlstra wrote:
On Wed, Jun 12, 2013 at 03:14:36AM -0500, Suravee Suthikulanit wrote:
Peter/Joerg
Please let me know if you have any questions/concerns about regarding this
patch set.
I've applied them for now -- Joerg holler if you want them held back.
Thank you
Uv2 hardware implementation,
and has been corrected since version 2.02 of the specification
(available through AMD NDA).
Signed-off-by: Jay Cornwall
Reviewed-by: Suravee Suthikulpanit
Applied, thanks.
Does this mean that PASIDs are only 16 bits wide now from the former 20
bits?
Thank yo
On 3/4/2014 10:53 AM, Suravee Suthikulpanit wrote:
On 3/4/2014 8:12 AM, Joerg Roedel wrote:
On Wed, Feb 26, 2014 at 03:49:31PM -0600,
suravee.suthikulpa...@amd.com wrote:
From: Jay Cornwall
This patch corrects the PASID format in the INVALIDATE_IOTLB_PAGES
command, which was caused by
Joerg,
Do you have any concerns about the V2 of this patch?
Thanks,
Suravee
On 3/5/2014 6:54 PM, suravee.suthikulpa...@amd.com wrote:
From: Suravee Suthikulpanit
In reality, the spec can only support 16-bit PASID since
INVALIDATE_IOTLB_PAGES and COMPLETE_PPR_REQUEST commands only allow 16
ir_data when calling modify_irte_ga() as done previously.
Fixes: b9c6ff94e43a ("iommu/amd: Re-factor guest virtual APIC (de-)activation
code")
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd_iommu.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/iom
GASup and automatically fallback to using
AMD_IOMMU_GUEST_IR_LEGACY if GA mode is not supported.
Fixes: 3928aa3f5775 ("iommu/amd: Detect and enable guest vAPIC support")
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd_iommu_init.c | 2 +-
1 file changed, 1 insertion(+),
Ping.
Thanks,
Suravee
On 4/22/20 8:30 PM, Suravee Suthikulpanit wrote:
Currently, system fails to boot because the legacy interrupt remapping
mode does not enable 128-bit IRTE (GA), which is required for x2APIC
support.
Fix by using AMD_IOMMU_GUEST_IR_LEGACY_GA mode when booting with
kernel
e mode 100644 drivers/iommu/amd_iommu.h
Thank you for cleaning up.
Reviewed-by: Suravee Suthikulpanit
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