If you can give me some sample part numbers I'll have a look.
- Cirilo
On Tue, Jun 9, 2015 at 1:55 AM, Wayne Stambaugh
wrote:
> Does anyone have a parametric 3D model generator script for two pin J
> lead components like SMD tantalum caps or SMD DO diode packages? I'm
> using some of the large
> On Jun 8, 2015, at 2:28 PM, Heiko Rosemann wrote:
>
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> On 06/08/2015 10:41 PM, Andy Peters wrote:
>>
>>> On Jun 8, 2015, at 12:19 PM, Heiko Rosemann
>>> wrote:
>>>
>>> So you have a single "canonical" version of each footprint and
>>> symb
Hi,
I already sent in this patch but as a reply to my existing pin targets
thread; I think it may have got lost. This patch enables pin "targets"
on bus entries as well, as Wayne suggested, and hides them when the bus
entry is connected.
--
Chris
commit a646e6c4b1a9ef624b4f56101d3a55f747558bf2
On Mon, Jun 08, 2015 at 11:28:08PM +0200, Heiko Rosemann wrote:
> > A given component should have exactly ONE available footprint. If
> > your opamp comes in PDIP-8 and SOIC-8, those are two different
> > components.
>
> Why? There's a good point for the opposite: Making different PCBs (SMD
> for
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On 06/08/2015 10:41 PM, Andy Peters wrote:
>
>> On Jun 8, 2015, at 12:19 PM, Heiko Rosemann
>> wrote:
>>
>> So you have a single "canonical" version of each footprint and
>> symbol. No need to copy symbols for creating new components, no
>> need to
> On Jun 8, 2015, at 12:19 PM, Heiko Rosemann wrote:
>
> The "components library" is the approach Eagle uses, and I have a bit
> of Eagle experience, so let me try to explain...
>
> In that approach, you do _not_ place just a symbol in a schematic, but
> an entire component (maybe a TL072ACD) o
On 08.06.2015 19:42, "Torsten Hüter" wrote:
> Boost.Geometry (not Boost.Polygon) - because this library has almost the same
> performance compared to Clipper but is more general; because they use
> metaprogrammin
Hi Torsten,
Thanks for the tip. I've known this performance comparison, it shows
C
On 6/8/2015 6:10 AM, LordBlick wrote:
> In response to a message written on 07.06.2015, 20:20, from Wayne
> Stambaugh:
>> I just committed a patch (r5718) from Dick that should greatly simplify
>> the process of footprint assignment using cvpcb. This patch does away
>> with using the intermediate
Chris,
I committed this patch with a minor change to make the exception message
a bit more understandable.
Thanks,
Wayne
On 6/7/2015 7:24 PM, Chris Pavlina wrote:
> If you try to load a kicad_pcb into pcbnew that refers to an invalid net
> ID, pcbnew crashes after failing an assertion. It shou
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On 06/08/2015 06:42 PM, Andy Peters wrote:
>
>> On Jun 7, 2015, at 1:33 AM, Eldar Khayrullin
>> wrote:
>>
>>> What problem is this trying to solve?
>
>> No copy sch symbols, no copy pcb footprints, more ready parts
>> with same sch symbol and footp
I agree with you. Too loudly that this is a problem.
I only suggested own idea as a new feature.
P.s.In my work we use a narrow specific range of parts and make cvpcb
looks excessive.
For me, it'snot difficult. But for simple users that use pcad it is
difficult.
They say: whatto dorethe same t
Hi Tom,
just for reference, you can find a benchmark of various polygon libraries here:
http://rogue-modron.blogspot.de/2011/04/polygon-clipping-wrapper-benchmark.html
It shows as well that Clipper performs better than Boost.Polygon and thus is a
good selection. And CGAL is well known but slow
Andy,
Regardless of the technical merits of the above replies, I want to make
something clear.
When I use eeschema, sometimes I am making sketches to send to remote team
members, and I definitely don't know the part number at that point.
This is what I was doing for the original email. I was la
Hi folks!
This is just to say my original question has been answered quite a few
replies up, which was that KiCad still supports both philosophies, and the
library team is going this way.
Thanks everyone! I'm certain there's a bunch more discussion we can do on
this, but I'm glad I got the clari
> On Jun 7, 2015, at 1:33 AM, Eldar Khayrullin wrote:
>
>> What problem is this trying to solve?
> No copy sch symbols, no copy pcb footprints,
> more ready parts with same sch symbol and footprint, but different
> pins assignment.
I still don’t understand why you think there are problems.
L
08/06/15, 18:55, Wayne Stambaugh kirjoitti:
> Does anyone have a parametric 3D model generator script for two pin J
> lead components like SMD tantalum caps or SMD DO diode packages? I'm
> using some of the large SMD wire wound resistor packages (2515, 4527,
> etc.) in some of my designs and I was
Does anyone have a parametric 3D model generator script for two pin J
lead components like SMD tantalum caps or SMD DO diode packages? I'm
using some of the large SMD wire wound resistor packages (2515, 4527,
etc.) in some of my designs and I was hoping there would be an easier
way to create them
08/06/15, 16:06, Chris Pavlina kirjoitti:
> Also keep in mind that the standard is pay-to-access. That's not fit for
> an open-source project. I rather suspect it would be frowned upon if we
> were to buy a copy and then put it into the documentation for all to
> access - and if we don't, how ca
08/06/15, 17:54, Chris Pavlina kirjoitti:
> Yes, but "we" are not a small group, "we" are everybody who can
> contribute. How can an open source project implement/follow a standard
> when it can't make that standard available to its contributors?
>
> On Mon, Jun 08, 2015 at 05:34:46PM +0300, Ve
Yes, but "we" are not a small group, "we" are everybody who can
contribute. How can an open source project implement/follow a standard
when it can't make that standard available to its contributors?
On Mon, Jun 08, 2015 at 05:34:46PM +0300, Vesa Solonen wrote:
>
> I generally agree with both of
GCC was still generating a warning using the reference as well so I
applied your patch in r5722.
Thanks,
Wayne
On 6/8/2015 10:08 AM, Chris Pavlina wrote:
> Nope, using a by-reference parameter does not appease clang; no idea about
> MSVC.
>
>
> On Mon, Jun 08, 2015 at 09:15:16AM -0400, Wayne
Nope, using a by-reference parameter does not appease clang; no idea about MSVC.
On Mon, Jun 08, 2015 at 09:15:16AM -0400, Wayne Stambaugh wrote:
> On 6/8/2015 8:58 AM, Chris Pavlina wrote:
> > It can't and it shouldn't - gcc is the one at fault here. wxString
> > provides the constructor:
> >
One is a search and the other is a direct access by index.
It's an academic discussion anyway - as long as the conflict is resolved
somehow so that kicad compiling doesn't depend on a gcc quirk, I'm
happy.
On Mon, Jun 08, 2015 at 09:15:16AM -0400, Wayne Stambaugh wrote:
> On 6/8/2015 8:58 AM,
On 6/8/2015 8:58 AM, Chris Pavlina wrote:
> It can't and it shouldn't - gcc is the one at fault here. wxString
> provides the constructor:
>
> wxString(char ch, size_t nRepeat=1)
>
> which is the one in question, I believe, as the integer literal can also
> represent a character.
>
> Using a r
In response to a message written on 08.06.2015, 15:01, from Lorenzo Marcantonio:
On Mon, Jun 08, 2015 at 02:57:46PM +0200, LordBlick wrote:
IMHO, there is no any obstacles, that NPTH pads can have some net, only last
wall is in peoples minds… ;)
There *are* issues having a net attached to an N
Also keep in mind that the standard is pay-to-access. That's not fit for
an open-source project. I rather suspect it would be frowned upon if we
were to buy a copy and then put it into the documentation for all to
access - and if we don't, how can we follow it?
Forget the damn standard. Make ou
On Mon, Jun 08, 2015 at 02:57:46PM +0200, LordBlick wrote:
> IMHO, there is no any obstacles, that NPTH pads can have some net, only last
> wall is in peoples minds… ;)
There *are* issues having a net attached to an NPTH, at least last time
I checked (i.e. when they where added). pcbnew has no han
Let's not get too hung up on EN60617-3. I really don't care if KiCad is
compliant to some standard other than exporting to third party file
formats. What I do care about is the user experience. If the goal is
to make it obvious to the user (IMO a good thing) that a schematic
connection is or is
It can't and it shouldn't - gcc is the one at fault here. wxString
provides the constructor:
wxString(char ch, size_t nRepeat=1)
which is the one in question, I believe, as the integer literal can also
represent a character.
Using a reference should work too, though changing the name is a more
I use this workaround ...
I manually added net number to the NPTH drill pad (with notepad)...
please find attached the pcb module
then you can use this module inside a library (import without editing
and save lib) and it is possible to wire tracks and there is no DRC
violations...
maybe to s
In response to a message written on 08.06.2015, 14:37, from Lorenzo Marcantonio:
On Mon, Jun 08, 2015 at 01:15:39PM +0200, Tomasz Wlostowski wrote:
There is another way: don't use a pad to simulate a via. Letting vias
retain their nets (or - in case of footprints - follow the connectivity
starti
Really! Clang can't differentiate between
SCH_SHEET_LIST::GetSheet(const wxString, bool);
and
SCH_SHEET_LIST::GetSheet(int);
How can these two definitions be ambiguous? Does using a reference to
the wxString instead of passing the entire string on the stack fix the
problem? If so, I would pr
On Mon, Jun 08, 2015 at 01:15:39PM +0200, Tomasz Wlostowski wrote:
> There is another way: don't use a pad to simulate a via. Letting vias
> retain their nets (or - in case of footprints - follow the connectivity
> starting from pads) is IMHO a way to fix this and many other issues
> (thermal via f
60617-3 allows a dotless junction (as in 03-02-06), but the same
connection can be represented with two 03-02-05; it is not a violation of
the standard to always use dots.
On Mon, Jun 08, 2015 at 08:48:12AM +0300, Vesa Solonen wrote:
> 08/06/15, 00:44, Wayne Stambaugh kirjoitti:
> > One thing I
On 08.06.2015 12:24, Cirilo Bernardo wrote:
> One method which comes to mind is to add yet another hole definition in
> software, and that may be the best way to address the problem; this way
> we can also ensure the correct thickness of the annulus and check the
> chosen number/size of vias.
Ther
One method which comes to mind is to add yet another hole definition in
software, and that may be the best way to address the problem; this way we
can also ensure the correct thickness of the annulus and check the chosen
number/size of vias.
- Cirilo
On Mon, Jun 8, 2015 at 5:59 PM, Lorenzo Marca
In response to a message written on 07.06.2015, 20:20, from Wayne Stambaugh:
I just committed a patch (r5718) from Dick that should greatly simplify
the process of footprint assignment using cvpcb. This patch does away
with using the intermediate *.cmp file and directly updates the s-expr
netlis
Having troubles getting an useable workflow with a common usage: the mounting
hole with satellite vias (see attachment).
Rationale: when you have a big hole for a screw and need to have plane
connectivity, a PTH supported pad is often not a good choice. Mostly because on
the wave solder machine th
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