[kicad-users] How to edit eeschema title block?
Hi all. Is it possible to edit the line "KiCad EDA" which appears in the schematics title block (bottom right corner of the sheet) when using eeshema? I have tried the "Page Settings" box but nowhere does it let you modify the actual page template...
[kicad-users] Re: eeschema 20080715 Netlist Errors
Jean-Pierre, I believe I know what happened, it was to some degree a problem with mixing eeschema versions between different engineers working on the same project. Two of the sheets were developed separately, one root containing one child sheet. We then added that root sheet to another schematic as a child sheet. The name of the child sheet that had been the root was changed. One of the nets that contained several erroneously merged nets had the same name as the previous root schematic. I believe at some point in time one of the schematics was manually edited and some of the sheet timestamps had been removed. Interestingly enough, eeschema still rendered the schematics correctly. I guess the only complaint I have is the lack of verbose diagnostics in the schematic to netlist conversion. I had to find the errors in PCB, emitters and collectors of transistors being shorted together and the like. Thanks for your consideration and timely response. --- In kicad-users@yahoogroups.com, jean-pierre charras wrote: > > daystar1013 a écrit : > > > > The new format for eeschema appears to be causing problems with local > > labels, global labels, and the new hierarchical label when generating > > netlists. > > I am working with a schematic that several people have been working on. > > It has a root sheet, a sheet inside the root and another one in the > > second level sheet. > > When the netlist was generated nets were merged for no apparent reason > > and given names that were not specified on any net. The PCB > > interconnectivity was really screwed up. > > > "New" hierarchical labels are the old global labels. the current global > labels are new and are actually "globals" (as said in new doc) > I have no problem with new eeschema labels handling. > So, can you send me your kicad project ? > > > -- > > Jean-Pierre CHARRAS > > Maître de conférences > Directeur d'études 2ieme année. > Génie Electrique et Informatique Industrielle 2 > Institut Universitaire de Technologie 1 de Grenoble > BP 67, 38402 St Martin d'Heres Cedex > > Recherche : > GIPSA-LIS - INPG > 46, Avenue Félix Viallet > 38031 Grenoble cedex >
[kicad-users] Netlist from EEschema not working in PCBnew
The 20080715 version of EEschema for Win32 is generating netlist pads for my C and R components that PCBnew can't handle. The netlist shows pins numbered "A" and "B", but if I look at the other components the pins are numbered "1" and "2" and so forth. Moving the whole thing into PCBnew generates a ratsnest that DOESNT include any of the R or C components. If I turn on warnings the Netlist update complains that it can't find some of the pads "A" and "B" from a couple of the components. What gives?
Re: [kicad-users] Re: eeschema 20080715 Netlist Errors
I had a very strange shematic error: in the main sheet I managed to add 2 daughter shematics exactly in the same place! The problem is that it was not visible and I could not move only one of them... I had to edit the file Did anyone have some similar problem? Alain daystar1013 escreveu: > Jean-Pierre, > > I believe I know what happened, it was to some degree a problem with > mixing eeschema versions between different engineers working on the > same project. > Two of the sheets were developed separately, one root containing one > child sheet. We then added that root sheet to another schematic as a > child sheet. The name of the child sheet that had been the root was > changed. One of the nets that contained several erroneously merged > nets had the same name as the previous root schematic. I believe at > some point in time one of the schematics was manually edited and some > of the sheet timestamps had been removed. Interestingly enough, > eeschema still rendered the schematics correctly. > I guess the only complaint I have is the lack of verbose diagnostics > in the schematic to netlist conversion. I had to find the errors in > PCB, emitters and collectors of transistors being shorted together > and the like. > > Thanks for your consideration and timely response. > > --- In kicad-users@yahoogroups.com, jean-pierre charras [EMAIL PROTECTED]> wrote: >> daystar1013 a écrit : >>> The new format for eeschema appears to be causing problems with > local >>> labels, global labels, and the new hierarchical label when > generating >>> netlists. >>> I am working with a schematic that several people have been > working on. >>> It has a root sheet, a sheet inside the root and another one in > the >>> second level sheet. >>> When the netlist was generated nets were merged for no apparent > reason >>> and given names that were not specified on any net. The PCB >>> interconnectivity was really screwed up. >>> >> "New" hierarchical labels are the old global labels. the current > global >> labels are new and are actually "globals" (as said in new doc) >> I have no problem with new eeschema labels handling. >> So, can you send me your kicad project ? >> >> >> -- >> >> Jean-Pierre CHARRAS >> >> Maître de conférences >> Directeur d'études 2ieme année. >> Génie Electrique et Informatique Industrielle 2 >> Institut Universitaire de Technologie 1 de Grenoble >> BP 67, 38402 St Martin d'Heres Cedex >> >> Recherche : >> GIPSA-LIS - INPG >> 46, Avenue Félix Viallet >> 38031 Grenoble cedex >> > > > > > > Please read the Kicad FAQ in the group files section before posting your > question. > Please post your bug reports here. They will be picked up by the creator of > Kicad. > Please visit http://www.kicadlib.org for details of how to contribute your > symbols/modules to the kicad library. > For building Kicad from source and other development questions visit the > kicad-devel group at http://groups.yahoo.com/group/kicad-develYahoo! Groups > Links > > > > >
[kicad-users] gerbview printing and plotting
Hi list, I've just finished a test pcb with kicad and plot it to gerber files. Everything went fine and i can load and see the .pho in gerbview, but the "plot" menu just ends to nothing. Then I tried to print to a ps or pdf file, but the result is just ugly, distorted. Am I missing something? Or is it a bug? Victor PS : I'm using version 20080715 on linux.
