uppresses the
> warning if the pins are in different units.
>
This warning is necessary.
Because for pins at same location, some changes can be made for all pins.
See Eeschema doc, chapter 11.6.3
--
Jean-Pierre CHARRAS
Maître de conférences
Directeur d'études 2ieme année.
Génie Elec
ftmost board. It seems to be
> missing the vias from the other boards. There's no problem with any of
> the other drill holes. The plotting for the panel is OK as well.
>
Please, can you send me yours PCB files ?
(to jean-pierre.char...@gipsa-lab.inpg.fr)
--
Jean-Pierre CHARRAS
Ma
automatically or manually?
>
>
> In case you are wondering why I should want to do this, the issue
> arises most often when drawing guarding and shielding traces. I've
> managed to work around the problem so far, but not without difficulty.
>
>
> Best wishes
>
>
>
ctly as I need. The only problem is that Zone-Fill
> is ignoring that extra copper area and is making a short :( (I could
> workaround using the zone clearence)
>
> Do you need a sample file? If I send only the .brd file, is it ok?
>
Yes, send me your board file.
--
Jean-Pierre CHARRAS
M
parameter (like zone
clearance)
For the known case, a change from 0.381 mm to 0.386 mm solves the problem.
--
Jean-Pierre CHARRAS
Maître de conférences
Directeur d'études 2ieme année.
Génie Electrique et Informatique Industrielle 2
Institut Universitaire de Technologie 1 de Grenoble
BP 67, 384
how does he made the routing ? manually,
> > autorouter(kicad) or autorouter extern ?is there an method ?
> >
>
Me.
By hand.
there are 2300 pads on this board
Boards i use to test kicad have 4500 pads (and more). They are routed by
hand.
--
Jean-Pierre CHARRAS
Maître de
th under XP SP3. Can
> also try on Ubuntu 8.04 in a few days if it would help.
>
> Thanks, Heiko
>
I am working on this.
But you have a zone clearance = 20 inches for all zones.
This is that freezes Pcbnew
With a "decent" clearance value (i tested 0.02 "), Pcbnew
t stuck.
>
> David.
>
Spaces always create problems.
Eeschema handles spaces in labels, but many netlist formats do not.
So to avoid problems in eeschema or pcbnew:
Do not use spaces or / in labels.
Do not use spaces in values and names.
--
Jean-Pierre CHARRAS
Maître de conférences
ems be silent?
>
Problems can be a lack of command to edit a via.
(edit layers pairs of an existing via, automatic change of layer pairs
when creating a new track starting or ending on a via (or deleting
atrack) , merging 2 vias at the same coordinate ...)
But of an other hand we need a volunteer
new tool to edit/add/remove fields in Libedit
--
Jean-Pierre CHARRAS
Maître de conférences
Directeur d'études 2ieme année.
Génie Electrique et Informatique Industrielle 2
Institut Universitaire de Technologie 1 de Grenoble
BP 67, 38402 St Martin d'Heres Cedex
Recherche :
Grenoble Image Parole Signal Automatique (GIPSA - INPG)
Grenoble France
ges, or adding a
suitable cutout or similar zone)
--
Jean-Pierre CHARRAS
Maître de conférences
Directeur d'études 2ieme année.
Génie Electrique et Informatique Industrielle 2
Institut Universitaire de Technologie 1 de Grenoble
BP 67, 38402 St Martin d'Heres Cedex
Recherche :
Grenoble I
Uploaded to my site the kicad-2008-08-25c version that solves the
problem in pcbnew/modedit.
--
Jean-Pierre CHARRAS
Maître de conférences
Directeur d'études 2ieme année.
Génie Electrique et Informatique Industrielle 2
Institut Universitaire de Technologie 1 de Grenoble
BP 67, 38402 St M
is not a problem in eeschema, but a *lot* of netlist formats do not
accept spaces in names.
I do not know the kicad version you are using.
The last version replaces spaces in labels in pcbnew netlist, but it is
better to avoid spaces in names.
See (with a text editor) the .net file to verify w
jean-pierre charras - INPG a écrit :
>
> gembler01 a écrit :
> >
> > This problem is reappearing in both the next-to-latest (2008-07-15
> > Final Win XP) and the latest version (2008-08-25 Final Win XP). In
> > 2008-07-15 I successfully defined and filled a zon
lves (i hope)
this problem
see iut-tice.ujf-grenoble.fr/cao/
--
Jean-Pierre CHARRAS
Maître de conférences
Directeur d'études 2ieme année.
Génie Electrique et Informatique Industrielle 2
Institut Universitaire de Technologie 1 de Grenoble
BP 67, 38402 St Martin d'Heres Cedex
Rech
gembler01 a écrit :
>
> Jean-Pierre,
>
> I sent the brd file to your @inpg.fr address. Did you receive it?
>
> -Gary
>
Yes.
I am working on it.
--
Jean-Pierre CHARRAS
Maître de conférences
Directeur d'études 2ieme année.
Génie Electrique et Informatique Industrielle 2
ase send me your board
--
Jean-Pierre CHARRAS
Maître de conférences
Directeur d'études 2ieme année.
Génie Electrique et Informatique Industrielle 2
Institut Universitaire de Technologie 1 de Grenoble
BP 67, 38402 St Martin d'Heres Cedex
Recherche :
Grenoble Image Parole Signal Automati
s.
Rémy Halvick is a better contributor than Jean Dupont (a guy like John
Smith)
--
Jean-Pierre CHARRAS
Maître de conférences
Directeur d'études 2ieme année.
Génie Electrique et Informatique Industrielle 2
Institut Universitaire de Technologie 1 de Grenoble
BP 67, 38402 St Martin d&
ations, help files and GUI.
If the about box cannot display all names, I can add a separate dialog
box for these contributors (like the author of the free editor SciTE did)
in help menu (something like help/contents, help/about and help/about
translators)
--
Jean-Pierre CHARRAS
Maître de conf
nnectors, etc. rather than have to position them with
> the mouse.
>
>
Yes, no problem.
--
Jean-Pierre CHARRAS
Maître de conférences
Directeur d'études 2ieme année.
Génie Electrique et Informatique Industrielle 2
Institut Universitaire de Technologie 1 de Grenoble
BP 67, 38402
> way, or is it a bug? This is present in the new release too.
>
See menu: preferences/Display Options/Show Vias Holes
And save the preferences.
> The "Set ALL via holes to default" context menu option also does not
> seem to work.
>
Ok. Will be solved in the final re
I uploaded a new kicad (2008-08-25-RC1x) to
iut-tice.ujf-grenoble.fr/cao/
This is a bug fix release.
--
Jean-Pierre CHARRAS
Maître de conférences
Directeur d'études 2ieme année.
Génie Electrique et Informatique Industrielle 2
Institut Universitaire de Technologie 1 de Grenoble
BP 67,
x27;ve just started this one and it's crashing with
> only four components on the sheet.
>
> Files are pasted below:
>
Your lib is missing.
Send me (zipped) the 5570.cache.lib file which is the schematic library
cache of your current design.
--
Jean-Pierre CHARRAS
Maître
X194. 437Y-83.439
> G05
> T5
> X196.215Y-89. 789G85X196. 215Y-86.741
> G05
> T7
> X189.992Y-89. 952G85X189. 992Y-86.578
> G05
>
> so as far as I can see, the lines containing the routed hole
> information are the same (the holes haven't moved), but the drill size
e the old global labels. the current global
labels are new and are actually "globals" (as said in new doc)
I have no problem with new eeschema labels handling.
So, can you send me your kicad project ?
--
Jean-Pierre CHARRAS
Maître de conférences
Directeur d'études 2ieme année
I removed the corrupted install file and uploaded a new one (non corrupted).
--
Jean-Pierre CHARRAS
Maître de conférences
Directeur d'études 2ieme année.
Génie Electrique et Informatique Industrielle 2
Institut Universitaire de Technologie 1 de Grenoble
BP 67, 38402 St Martin d'H
-grenoble.fr/kicad/ (full install and stable
versions only)
and also (for snapshots, infos, news ...)
http://kicad.sourceforge.net/
Sources can be found here:
http://kicad.svn.sourceforge.net/
--
Jean-Pierre CHARRAS
Maître de conférences
Directeur d'études 2ieme année.
Génie Electriq
yajeed2000 a écrit :
> Hi,
> Are we nearing a stable release yet?
> If not do we have long to wait?
> Please let us all know, Thanks.
>
> David
>
The next stable version is now ready.
I am just updating the doc, before the stable release.
--
Jean-Pierre CHARRAS
rawing oblong pads, some next drawings can
be incorrectly drawn (bad size)
This old bug is now solved (Postscript output will be Ok in next release,
coming soon)
Can you confirm you have oblong pads on your board ?
Jean-Pierre CHARRAS
Maître de conférences
Directeur d'études 2ieme année.
Génie
dit select the given library
load any footprint from this lib
save it.
the .mod and .mdc will be updated (.mdc created if not exists)
--
Jean-Pierre CHARRAS
Maître de conférences
Directeur d'études 2ieme année.
Génie Electrique et Informatique Industrielle 2
Institut Universitaire de Techn
;
This is a wxGTK bug, fixed in recent wxGTK releases ( >= 2.7.1)
For old versions, See the wxGTK patch in how-to-build-kicad.txt.
in this file there is an other patch for printing.
--
Jean-Pierre CHARRAS
Maître de conférences
Directeur d'études 2ieme année.
Génie Electrique et Infor
ined in the .net file wich i realy dont want
>
You are using spaces in labels.
This is not a problem with eeschema, but it is a big problem in ** most
** of netlist formats.
DO NOT use spaces (or exotic letters) in names or labels in a schematic.
--
Jean-Pierre CHARRAS
Maître de conférences
extras softwares.
>
> I ill look the possibilits, Don't kow if good result!
>
> I ill attempt clear the code and push avaliable to friends!
>
Volunteers could help you...
The most important thing is ; write comments in your code.
> []'s
> Renie
>
>
terface to svn.
It make svn use **very** easy.
What you are writing is a very interesting tool for kicad.
Perhaps can you consider to use wxWidgets instead of Delphi.
wxWidget is very powerfull and it is easier to use as Delphi.
And with wxWidget, internationalization is very easy (strings li
er, and the other to the component layer. However,
> I cannot route any of them, because KiCAD says that they are in shor
> circuit. Does anyone have any suggestions?
> Thanks in advance.
>
>
Yours pads ** must** have the same pad number.
Change they, and reread the netlist
editor, change hotkey values (there are comments to do
that within the hotkey file: eeschema.key or pcbney.key)
3 - Rerun eeschema (better) ( or reread hotkey file in preferences menu
for fast test) If no bugs, it must be work (I hope it).
4 - Write a small ( or big ) tutorial about this (under
r, because the pins are already connected by other tracks,
and from the point of view of the DRC, the connection exists, and
therefore there is no DRC error.
The "missing" via is redondant and therefore not necessary ( of course,
from the point of view of the DRC).
--
Jean-Pie
L310 connecting layer 1 and
layer 2.
Of course, because your via diameter is smaller than track width (not a
good practice!) if you want to see a small white via on a white track,
select the sketch mode for tracks, or change the track color
--
Jean-Pierre CHARRAS
Maître de conférences
Dir
ematic(s) and
> create the netlist. This all went ok as it normally had. Next I ran
> (or rather tried to run) cvpcb to assign the footprints to the new
> parts. BAM it crashed right away.
>
Can you send me (or/and send to Dick H.) your files (zip your project
and send the zipped file)
for debugging.
>
If not already done, send the .brd file (no other file is needed) to
Dick or to me
--
Jean-Pierre CHARRAS
Maître de conférences
Directeur d'études 2ieme année.
Génie Electrique et Informatique Industrielle 2
Institut Universitaire de Technologie 1 de Grenoble
BP 67,
Due to a problem in eeschema annotation, I released a new candidate version
(kicad-2007-11-29-RC2). See:
iut-tice.ujf-grenoble.fr/cao/
--
Jean-Pierre CHARRAS
Maître de conférences
Directeur d'études 2ieme année.
Génie Electrique et Informatique Industrielle 2
Institut Universitai
dave a écrit :
> jean-pierre charras wrote:
>
>
>> dave a écrit :
>>
>>
>>> Dan Andersson wrote:
>>>
>>>
>>>
>>>> On Sunday 25 November 2007 07:15:05 dave wrote:
>>>>
>>>>
>&
55, U056, U057 ... this is
because these components are flagged as "power symbols"
Only power symbols (like VCC, GND ...) must be flagged "power
component" because they are not really "components", they are special
symbols
--
Jean-Pierre CHARRAS
Maître de conférences
Directeur d'études 2ieme année.
Génie Electrique et Informatique Industrielle 2
Institut Universitaire de Technologie 1 de Grenoble
BP 67, 38402 St Martin d'Heres Cedex
Recherche :
GIPSA-LIS - INPG
46, Avenue Félix Viallet
38031 Grenoble cedex
A Kicad release candidate (kicad-2007-11-19-RC) was uploaded. See:
iut-tice.ujf-grenoble.fr/cao/
--
Jean-Pierre CHARRAS
Maître de conférences
Directeur d'études 2ieme année.
Génie Electrique et Informatique Industrielle 2
Institut Universitaire de Technologie 1 de Grenoble
BP 67, 38402 St M
> Cool - thanks. So the drill file that is produced is OK, and is not
> affected by this error?
>
>
>
The drill file is Ok.
This problem is due to drc markers on your board which are not drawn in
drill map.
You can remove these markers if you want.
--
Jean-Pierre CH
o be created succesfully. Does anyone know what this
> error means?
>
>
This is an internal problem, and i suppose this is only for the drill map.
Do not worry about this.
--
Jean-Pierre CHARRAS
Maître de conférences
Directeur d'études 2ieme année.
Génie Electrique et Informatique
rangierer90 a écrit :
> Hello,
>
> at first let me say thank you for this great program. I think
> it is a highlight in the open source world.
>
>
> Here is my problem:
> I need a connection on the bottom layer and the
> same connection on the top layer.
> I need this because of high current for t
a schematic problem
(when you are designing your schematic, you want a resistor, or a
capacitor, or a transistor, not a part number 09 4567 A34-rev 4, not a
sm0806 package or a sm0603 - rotated 90° package...)
I believe the footprint selection is board design problem.
--
Jean-Pierre CHARRAS
M
r rs274x format, see:
http://www.artwork.com/gerber/274x/rs274x.htm
--
Jean-Pierre CHARRAS
Maître de conférences
Directeur d'études 2ieme année.
Génie Electrique et Informatique Industrielle 2
Institut Universitaire de Technologie 1 de Grenoble
BP 67, 38402 St Martin d'Heres Cedex
Reche
binary file
--
Jean-Pierre CHARRAS
Maître de conférences
Directeur d'études 2ieme année.
Génie Electrique et Informatique Industrielle 2
Institut Universitaire de Technologie 1 de Grenoble
BP 67, 38402 St Martin d'Heres Cedex
Recherche :
Grenoble Image Parole Signal Automatique (GI
s the "Hight contrast mode" (left toolbar, "Hight contrast mode
display") which shows the active layer in normal color, and others
layers in dark gray color.
--
Jean-Pierre CHARRAS
Maître de conférences
Directeur d'études 2ieme année.
Génie Electrique et Informatique Indust
tlist. Of course if myschema.tmp does not exists,
the pad-pcb netlist is void...
--
Jean-Pierre CHARRAS
Maître de conférences
Directeur d'études 2ieme année.
Génie Electrique et Informatique Industrielle 2
Institut Universitaire de Technologie 1 de Grenoble
BP 67, 38402 St Martin d'Heres
rsion of wxGTK does not have this bug.
--
Jean-Pierre CHARRAS
Maître de conférences
Directeur d'études 2ieme année.
Génie Electrique et Informatique Industrielle 2
Institut Universitaire de Technologie 1 de Grenoble
BP 67, 38402 St Martin d'Heres Cedex
Recherche :
Grenoble Image Parole
d on this one.
>
> Thanks,
>
> Glenn.
>
>
>
The reference name of your powers is pwr? (pwr1, pwr2 ...) and **MUST**
be #pwr?
A component with a reference starting by # is *not* listed in reports or
netlist.
(see eeschema doc, chapter 10.8)
Jean-P
er to avoid problems:
Rename the kicad directory C:\Program Files\KiCad to C:\Program
Files\kicad AND edit the desktop icon properties ( change KiCad to kicad)
or:
install kicad in root directory (c:\ or d:\)
or
download the new autoinstall archive (this bug is solved)
--
Jean-Pierre CHARRAS
M
I have uploaded a new (stable version) : kicad-2007-01-15
--
Jean-Pierre CHARRAS
Maître de conférences
Directeur d'études 2ieme année.
Génie Electrique et Informatique Industrielle 2
Institut Universitaire de Technologie 1 de Grenoble
BP 67, 38402 St Martin d'Heres Cedex
Recherche :
his tool is not activated, pins with are in the same location are
deleted, moved ... for all the parts (because usually all the parts have
the same look)..
The meaning of "common to unit" is : this pin is shown for all parts
with the same name and pin number
When the attribut
I have uploaded a new kicad release candidate (kicad-2007-01-03-RC2) at:
iut-tice.ujf-grenoble.fr/cao/
Some bugs are fixed.
Some new enhancements.
This is the last release candidate before the stable version.
--
Jean-Pierre CHARRAS
Maître de conférences
Directeur d'études 2ieme année.
-Pierre CHARRAS
Maître de conférences
Directeur d'études 2ieme année.
Génie Electrique et Informatique Industrielle 2
Institut Universitaire de Technologie 1 de Grenoble
BP 67, 38402 St Martin d'Heres Cedex
Recherche :
LIS - INPG
46, Avenue Félix Viallet
38031 Grenoble Cedex
n user permission!
If you want choose the parts in a multipart component, first annotate
your schematic, and after change the automatic selection of the parts.
And **do not* use the "all components" option after this.
--
Jean-Pierre CHARRAS
Maître de conférences
Directeur d
or building Kicad from source and other development questions visit the kicad-devel group at http://groups.yahoo.com/group/kicad-devel
>Yahoo! Groups Links
>
>
>
>
>
>
>
>
>
>
--
Jean-Pierre CHARRAS
Maître de conférences
Directeur d'études 2ieme année.
Génie
ingedbonilla a écrit :
>I am making a GPL design and layout of an audio codec, currently I
>have been modifying all modules to include the assembly Drawing in the
>Decal.
>
>I created the 2D shape in the Drawing layer, but when I have a board
>with two sides mounted components, it is imposs
I have uploaded the last kicad release (kicad-2006-04-24)
Many small but usefull enhancements
--
Jean-Pierre CHARRAS
Maître de conférences
Directeur d'études 2ieme année.
Génie Electrique et Informatique Industrielle 2
Institut Universitaire de Technologie 1 de Grenoble
BP 67, 384
I have uploaded the kicad stable version (kicad-2006-03-28.*)
Only few changes since kicad-2006-03-21 (2 small bugs fixed)
--
Jean-Pierre CHARRAS
Maître de conférences
Directeur d'études 2ieme année.
Génie Electrique et Informatique Industrielle 2
Institut Universitaire de Technologie
I have uploaded a new release candidate for kicad (the last before the
stable version)
Spanish translation is updated.
Bugs reported from the first release candidate are fixed.
--
Jean-Pierre CHARRAS
Maître de conférences
Directeur d'études 2ieme année.
Génie Electrique et Informa
65 matches
Mail list logo
