On Sun, May 19, 2013 at 02:17:33PM -0700, David Daney wrote:
On 05/19/2013 07:17 AM, Gleb Natapov wrote:
On Sat, May 18, 2013 at 06:54:26AM -0700, Sanjay Lal wrote:
From: David Daney david.da...@cavium.com
There are several parts to this:
o All registers are 64-bits wide, 32-bit guests
On Mon, May 20, 2013 at 02:11:19AM +, Qinchuanyu wrote:
Vhost thread provide both tx and rx ability for virtio-net.
In the forwarding scenarios, tx and rx share the vhost thread, and throughput
is limited by single thread.
So I did a patch for provide vhost thread per virtqueue, not
Il 19/05/2013 08:37, Vadim Rozenfeld ha scritto:
On Thu, 2013-05-16 at 16:45 +0200, Paolo Bonzini wrote:
Il 16/05/2013 16:26, Vadim Rozenfeld ha scritto:
Yes, I have this check added in the second patch.
Move it here please.
OK, will do it.
Or better, remove all the handling of
On Mon, May 20, 2013 at 10:05:38AM +0200, Paolo Bonzini wrote:
Il 19/05/2013 08:37, Vadim Rozenfeld ha scritto:
On Thu, 2013-05-16 at 16:45 +0200, Paolo Bonzini wrote:
Il 16/05/2013 16:26, Vadim Rozenfeld ha scritto:
Yes, I have this check added in the second patch.
Move it here
Il 20/05/2013 10:36, Gleb Natapov ha scritto:
On Mon, May 20, 2013 at 10:05:38AM +0200, Paolo Bonzini wrote:
Il 19/05/2013 08:37, Vadim Rozenfeld ha scritto:
On Thu, 2013-05-16 at 16:45 +0200, Paolo Bonzini wrote:
Il 16/05/2013 16:26, Vadim Rozenfeld ha scritto:
Yes, I have this check added
On Mon, May 20, 2013 at 10:42:52AM +0200, Paolo Bonzini wrote:
Il 20/05/2013 10:36, Gleb Natapov ha scritto:
On Mon, May 20, 2013 at 10:05:38AM +0200, Paolo Bonzini wrote:
Il 19/05/2013 08:37, Vadim Rozenfeld ha scritto:
On Thu, 2013-05-16 at 16:45 +0200, Paolo Bonzini wrote:
Il
Il 20/05/2013 10:49, Gleb Natapov ha scritto:
On Mon, May 20, 2013 at 10:42:52AM +0200, Paolo Bonzini wrote:
Il 20/05/2013 10:36, Gleb Natapov ha scritto:
On Mon, May 20, 2013 at 10:05:38AM +0200, Paolo Bonzini wrote:
Il 19/05/2013 08:37, Vadim Rozenfeld ha scritto:
On Thu, 2013-05-16 at
Rusty Russell ru...@rustcorp.com.au wrote:
The point of the patch is that it's unusable:
#define VIRTIO_PCI_CONFIG(dev)((dev)-msix_enabled ? 24 : 20)
ie. it's accessing a member of the kernel's virtio_pci_dev structure.
Ah, okay. In that case, zap it and see if anyone
On Mon, 2013-05-20 at 10:05 +0200, Paolo Bonzini wrote:
Il 19/05/2013 08:37, Vadim Rozenfeld ha scritto:
On Thu, 2013-05-16 at 16:45 +0200, Paolo Bonzini wrote:
Il 16/05/2013 16:26, Vadim Rozenfeld ha scritto:
Yes, I have this check added in the second patch.
Move it here please.
On 05/19/2013 06:04 PM, Gleb Natapov wrote:
+/*
+ * Do not repeatedly zap a root page to avoid unnecessary
+ * KVM_REQ_MMU_RELOAD, otherwise we may not be able to
+ * progress:
+ *vcpu 0vcpu 1
+
On Mon, May 20, 2013 at 10:56:22AM +0200, Paolo Bonzini wrote:
Il 20/05/2013 10:49, Gleb Natapov ha scritto:
On Mon, May 20, 2013 at 10:42:52AM +0200, Paolo Bonzini wrote:
Il 20/05/2013 10:36, Gleb Natapov ha scritto:
On Mon, May 20, 2013 at 10:05:38AM +0200, Paolo Bonzini wrote:
Il
On 05/19/2013 06:47 PM, Gleb Natapov wrote:
On Fri, May 17, 2013 at 05:12:57AM +0800, Xiao Guangrong wrote:
Move deletion shadow page from the hash list from kvm_mmu_commit_zap_page to
kvm_mmu_prepare_zap_page so that we can call kvm_mmu_commit_zap_page
once for multiple
On Mon, May 20, 2013 at 10:56:22AM +0200, Paolo Bonzini wrote:
In any case, this patch needs more comments and a better commit message.
Microsoft docs are decent, but there are several non-obvious points in
how the patches were done, and they need to be documented.
I wish you were right about
Il 20/05/2013 11:25, Gleb Natapov ha scritto:
So in Hyper-V spec they
say:
Special value of 0x is used to indicate that this facility is no
longer a reliable source of reference time and the virtual machine must
fall back to a different source (for example, the virtual PM
On Mon, May 20, 2013 at 11:32:27AM +0200, Paolo Bonzini wrote:
Il 20/05/2013 11:25, Gleb Natapov ha scritto:
So in Hyper-V spec they
say:
Special value of 0x is used to indicate that this facility is no
longer a reliable source of reference time and the virtual machine must
On Mon, May 20, 2013 at 05:19:26PM +0800, Xiao Guangrong wrote:
On 05/19/2013 06:47 PM, Gleb Natapov wrote:
On Fri, May 17, 2013 at 05:12:57AM +0800, Xiao Guangrong wrote:
Move deletion shadow page from the hash list from kvm_mmu_commit_zap_page
to
kvm_mmu_prepare_zap_page so that we can
On Sun, May 19, 2013 at 10:56:16PM +, Narasimhan, Sriram wrote:
Hi Michael,
Comments inline...
-Original Message-
From: Michael S. Tsirkin [mailto:m...@redhat.com]
Sent: Sunday, May 19, 2013 1:03 PM
To: Narasimhan, Sriram
Cc: ru...@rustcorp.com.au;
Hi all,
sorry that I am a bit unresponsive about this series. I have a few days off and
can't spend much time in this.
If I read that the REFERENCE TSC breaks migration I don't think its a good
option to include it at all.
I have this hyperv_refcnt MSR in an internal patch I sent over about 1.5
On Mon, 2013-05-20 at 10:56 +0200, Paolo Bonzini wrote:
Il 20/05/2013 10:49, Gleb Natapov ha scritto:
On Mon, May 20, 2013 at 10:42:52AM +0200, Paolo Bonzini wrote:
Il 20/05/2013 10:36, Gleb Natapov ha scritto:
On Mon, May 20, 2013 at 10:05:38AM +0200, Paolo Bonzini wrote:
Il 19/05/2013
On Mon, 2013-05-20 at 12:25 +0300, Gleb Natapov wrote:
On Mon, May 20, 2013 at 10:56:22AM +0200, Paolo Bonzini wrote:
In any case, this patch needs more comments and a better commit message.
Microsoft docs are decent, but there are several non-obvious points in
how the patches were done,
On Mon, May 20, 2013 at 08:25:11PM +1000, Vadim Rozenfeld wrote:
On Mon, 2013-05-20 at 12:25 +0300, Gleb Natapov wrote:
On Mon, May 20, 2013 at 10:56:22AM +0200, Paolo Bonzini wrote:
In any case, this patch needs more comments and a better commit message.
Microsoft docs are decent, but
On Mon, 2013-05-20 at 13:27 +0300, Gleb Natapov wrote:
On Mon, May 20, 2013 at 08:25:11PM +1000, Vadim Rozenfeld wrote:
On Mon, 2013-05-20 at 12:25 +0300, Gleb Natapov wrote:
On Mon, May 20, 2013 at 10:56:22AM +0200, Paolo Bonzini wrote:
In any case, this patch needs more comments and a
Hi
Please, send any topic that you are interested in covering.
Thanks, Juan.
--
To unsubscribe from this list: send the line unsubscribe kvm in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Hi Alex,
Alex Williamson alex.william...@redhat.com wrote:
On Sun, 2013-05-19 at 23:26 +0400, Maik Broemme wrote:
Hi Knut,
Knut Omang kn...@ifi.uio.no wrote:
On Mon, 2013-05-13 at 16:23 -0600, Alex Williamson wrote:
On Mon, 2013-05-13 at 22:55 +0200, Knut Omang wrote:
Hi
On Sun, Feb 10, 2013 at 02:19:29PM +0200, Gleb Natapov wrote:
On Sat, Feb 09, 2013 at 11:31:45AM +0200, Avi Kivity wrote:
Single-operand MUL and DIV access an extended accumulator: AX for byte
instructions, and DX:AX, EDX:EAX, or RDX:RAX for larger-sized instructions.
Add support for
On Sat, Feb 09, 2013 at 11:32:25AM +0200, Avi Kivity wrote:
Signed-off-by: Avi Kivity avi.kiv...@gmail.com
Applied, thanks.
---
x86/emulator.c | 19 ---
1 file changed, 16 insertions(+), 3 deletions(-)
diff --git a/x86/emulator.c b/x86/emulator.c
index a128e13..96576e5
Il 19/05/2013 06:52, Jun Nakajima ha scritto:
From: Nadav Har'El n...@il.ibm.com
Recent KVM, since http://kerneltrap.org/mailarchive/linux-kvm/2010/5/2/6261577
switch the EFER MSR when EPT is used and the host and guest have different
NX bits. So if we add support for nested EPT (L1 guest
Il 19/05/2013 06:52, Jun Nakajima ha scritto:
From: Nadav Har'El n...@il.ibm.com
For preparation, we just move gpte_access() and prefetch_invalid_gpte() from
mmu.c to paging_tmpl.h.
Signed-off-by: Nadav Har'El n...@il.ibm.com
Signed-off-by: Jun Nakajima jun.nakaj...@intel.com
Il 19/05/2013 06:52, Jun Nakajima ha scritto:
From: Nadav Har'El n...@il.ibm.com
Since link_shadow_page() is used by a routine in mmu.c, add an
EPT-specific link_shadow_page() in paging_tmp.h, rather than moving
it.
Signed-off-by: Nadav Har'El n...@il.ibm.com
Signed-off-by: Jun Nakajima
Il 19/05/2013 06:52, Jun Nakajima ha scritto:
+ switch (type) {
+ case VMX_EPT_EXTENT_GLOBAL:
+ if (!(nested_vmx_ept_caps VMX_EPT_EXTENT_GLOBAL_BIT))
+ nested_vmx_failValid(vcpu,
+ VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
Il 19/05/2013 06:52, Jun Nakajima ha scritto:
From: Nadav Har'El n...@il.ibm.com
Advertise the support of EPT to the L1 guest, through the appropriate MSR.
This is the last patch of the basic Nested EPT feature, so as to allow
bisection through this patch series: The guest will not see EPT
Il 19/05/2013 06:52, Jun Nakajima ha scritto:
@@ -7441,10 +7443,81 @@ static void nested_ept_inject_page_fault(struct
kvm_vcpu *vcpu,
* Note no need to set vmcs12-vm_exit_reason as it is already copied
* from vmcs02 in nested_vmx_vmexit() above, i.e., EPT_VIOLATION.
*/
Il 19/05/2013 06:52, Jun Nakajima ha scritto:
From: Nadav Har'El n...@il.ibm.com
kvm_set_cr3() attempts to check if the new cr3 is a valid guest physical
address. The problem is that with nested EPT, cr3 is an *L2* physical
address, not an L1 physical address as this test expects.
As the
Il 19/05/2013 06:52, Jun Nakajima ha scritto:
From: Nadav Har'El n...@il.ibm.com
The existing code for handling cr3 and related VMCS fields during nested
exit and entry wasn't correct in all cases:
If L2 is allowed to control cr3 (and this is indeed the case in nested EPT),
during nested
Il 19/05/2013 06:52, Jun Nakajima ha scritto:
From: Nadav Har'El n...@il.ibm.com
Some additional comments to preexisting code:
Explain who (L0 or L1) handles EPT violation and misconfiguration exits.
Don't mention shadow on either EPT or shadow as the only two options.
Signed-off-by:
On Mon, May 20, 2013 at 12:57:47PM +0200, Juan Quintela wrote:
Hi
Please, send any topic that you are interested in covering.
Thanks, Juan.
Generating acpi tables.
Cc'd a bunch of people who might be interested in this topic.
Kevin - could you join on Tuesday? There appears a
On Tue, May 14, 2013 at 03:13:29PM +0100, Marc Zyngier wrote:
Add HYP and S2 page flags, for both normal and device memory.
Reviewed-by: Christopher Covington c...@codeaurora.org
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
Reviewed-by: Catalin Marinas catalin.mari...@arm.com
--
To
From: Lai Jiangshan la...@cn.fujitsu.com
At the point of up_out label in kvmppc_hv_setup_htab_rma(),
srcu read lock is still held.
We have to release it before return.
Signed-off-by: Lai Jiangshan la...@cn.fujitsu.com
Cc: Marcelo Tosatti mtosa...@redhat.com
Cc: Gleb Natapov g...@redhat.com
Cc:
On Tue, May 14, 2013 at 03:13:30PM +0100, Marc Zyngier wrote:
Add the necessary infrastructure for identity-mapped HYP page
tables. Idmap-ed code must be in the .hyp.idmap.text linker
section.
The rest of the HYP ends up in .hyp.text.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
...
On Tue, May 14, 2013 at 03:13:31PM +0100, Marc Zyngier wrote:
Define all the useful bitfields for EL2 registers.
Reviewed-by: Christopher Covington c...@codeaurora.org
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
Reviewed-by: Catalin Marinas catalin.mari...@arm.com
--
To unsubscribe from
On Tue, May 14, 2013 at 03:13:32PM +0100, Marc Zyngier wrote:
Define the saved/restored registers for 64bit guests.
Reviewed-by: Christopher Covington c...@codeaurora.org
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
Reviewed-by: Catalin Marinas catalin.mari...@arm.com
--
To unsubscribe
On Tue, May 14, 2013 at 03:13:33PM +0100, Marc Zyngier wrote:
Implements helpers for dealing with the EL2 syndrome register as
well as accessing the vcpu registers.
Reviewed-by: Christopher Covington c...@codeaurora.org
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
...
+static inline
On 20/05/13 16:31, Catalin Marinas wrote:
On Tue, May 14, 2013 at 03:13:30PM +0100, Marc Zyngier wrote:
Add the necessary infrastructure for identity-mapped HYP page
tables. Idmap-ed code must be in the .hyp.idmap.text linker
section.
The rest of the HYP ends up in .hyp.text.
On 20/05/13 16:41, Catalin Marinas wrote:
On Tue, May 14, 2013 at 03:13:33PM +0100, Marc Zyngier wrote:
Implements helpers for dealing with the EL2 syndrome register as
well as accessing the vcpu registers.
Reviewed-by: Christopher Covington c...@codeaurora.org
Signed-off-by: Marc Zyngier
On 05/18/2013 10:47 PM, Sanjay Lal wrote:
The following patch set adds support for the recently announced virtualization
extensions for the MIPS32 architecture and allows running unmodified kernels in
Guest Mode.
For more info please refer to :
MIPS Document #: MD00846
Volume
On Tue, May 14, 2013 at 03:13:34PM +0100, Marc Zyngier wrote:
Implement the injection of a fault (undefined, data abort or
prefetch abort) into a 64bit guest.
Reviewed-by: Christopher Covington c...@codeaurora.org
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
Reviewed-by: Catalin Marinas
On Tue, May 14, 2013 at 03:13:35PM +0100, Marc Zyngier wrote:
+static inline bool kvm_is_write_fault(unsigned long esr)
+{
+ unsigned long esr_ec = esr ESR_EL2_EC_SHIFT;
Not that it would make much difference but for consistency - we use esr
as an 'unsigned int' in the arm64 code (only
On Tue, May 14, 2013 at 03:13:36PM +0100, Marc Zyngier wrote:
Provide the kvm.h file that defines the user space visible
interface.
Reviewed-by: Christopher Covington c...@codeaurora.org
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
Reviewed-by: Catalin Marinas catalin.mari...@arm.com
--
On 20/05/13 16:57, Catalin Marinas wrote:
On Tue, May 14, 2013 at 03:13:35PM +0100, Marc Zyngier wrote:
+static inline bool kvm_is_write_fault(unsigned long esr)
+{
+unsigned long esr_ec = esr ESR_EL2_EC_SHIFT;
Not that it would make much difference but for consistency - we use esr
as
On Tue, May 14, 2013 at 03:13:37PM +0100, Marc Zyngier wrote:
Provide 64bit system register handling, modeled after the cp15
handling for ARM.
Reviewed-by: Christopher Covington c...@codeaurora.org
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
Reviewed-by: Catalin Marinas
On Mon, May 20, 2013 at 05:17:31PM +0100, Marc Zyngier wrote:
On 20/05/13 16:57, Catalin Marinas wrote:
On Tue, May 14, 2013 at 03:13:35PM +0100, Marc Zyngier wrote:
+static inline bool kvm_is_write_fault(unsigned long esr)
+{
+ unsigned long esr_ec = esr ESR_EL2_EC_SHIFT;
Not that
On Tue, May 14, 2013 at 03:13:38PM +0100, Marc Zyngier wrote:
Add the support code for CPU specific system registers. Not much
here yet.
Reviewed-by: Christopher Covington c...@codeaurora.org
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
Reviewed-by: Catalin Marinas
On 20/05/13 17:25, Catalin Marinas wrote:
On Mon, May 20, 2013 at 05:17:31PM +0100, Marc Zyngier wrote:
On 20/05/13 16:57, Catalin Marinas wrote:
On Tue, May 14, 2013 at 03:13:35PM +0100, Marc Zyngier wrote:
+static inline bool kvm_is_write_fault(unsigned long esr)
+{
+ unsigned long esr_ec
On Tue, May 14, 2013 at 03:13:39PM +0100, Marc Zyngier wrote:
Provide the reset code for a virtual CPU booted in 64bit mode.
Reviewed-by: Christopher Covington c...@codeaurora.org
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
Reviewed-by: Catalin Marinas catalin.mari...@arm.com
--
To
On Tue, May 14, 2013 at 03:13:40PM +0100, Marc Zyngier wrote:
Provide the architecture dependent structures for VM and
vcpu abstractions.
Reviewed-by: Christopher Covington c...@codeaurora.org
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
Reviewed-by: Catalin Marinas
On May 20, 2013, at 8:50 AM, David Daney wrote:
On 05/18/2013 10:47 PM, Sanjay Lal wrote:
The following patch set adds support for the recently announced
virtualization
extensions for the MIPS32 architecture and allows running unmodified kernels
in
Guest Mode.
For more info please
On 05/20/2013 09:58 AM, Sanjay Lal wrote:
On May 20, 2013, at 8:50 AM, David Daney wrote:
On 05/18/2013 10:47 PM, Sanjay Lal wrote:
The following patch set adds support for the recently announced virtualization
extensions for the MIPS32 architecture and allows running unmodified kernels in
On May 20, 2013, at 10:29 AM, David Daney wrote:
On 05/20/2013 09:58 AM, Sanjay Lal wrote:
On May 20, 2013, at 8:50 AM, David Daney wrote:
On 05/18/2013 10:47 PM, Sanjay Lal wrote:
The following patch set adds support for the recently announced
virtualization
extensions for the MIPS32
On Mon, 20 May 2013, Sanjay Lal wrote:
(1) Newer versions of the MIPS architecture define scratch registers for
just this purpose, but since we have to support standard MIPS32R2
processors, we use the DDataLo Register (CP0 Register 28, Select 3) as a
scratch register to save k0 and save k1
On 05/20/2013 11:36 AM, Maciej W. Rozycki wrote:
On Mon, 20 May 2013, Sanjay Lal wrote:
(1) Newer versions of the MIPS architecture define scratch registers for
just this purpose, but since we have to support standard MIPS32R2
processors, we use the DDataLo Register (CP0 Register 28, Select 3)
On Fri, May 17, 2013 at 05:12:58AM +0800, Xiao Guangrong wrote:
The current kvm_mmu_zap_all is really slow - it is holding mmu-lock to
walk and zap all shadow pages one by one, also it need to zap all guest
page's rmap and all shadow page's parent spte list. Particularly, things
become worse
On Mon, May 20, 2013 at 04:46:24PM -0300, Marcelo Tosatti wrote:
On Fri, May 17, 2013 at 05:12:58AM +0800, Xiao Guangrong wrote:
The current kvm_mmu_zap_all is really slow - it is holding mmu-lock to
walk and zap all shadow pages one by one, also it need to zap all guest
page's rmap and all
On Mon, May 20, 2013 at 11:15:45PM +0300, Gleb Natapov wrote:
On Mon, May 20, 2013 at 04:46:24PM -0300, Marcelo Tosatti wrote:
On Fri, May 17, 2013 at 05:12:58AM +0800, Xiao Guangrong wrote:
The current kvm_mmu_zap_all is really slow - it is holding mmu-lock to
walk and zap all shadow
On Sun, 2013-05-19 at 23:26 +0400, Maik Broemme wrote:
Hi Knut,
Knut Omang kn...@ifi.uio.no wrote:
On Mon, 2013-05-13 at 16:23 -0600, Alex Williamson wrote:
On Mon, 2013-05-13 at 22:55 +0200, Knut Omang wrote:
Hi all,
Perfect timing from my perspective, thanks Alex!
From: David Daney david.da...@cavium.com
Signed-off-by: David Daney david.da...@cavium.com
---
arch/mips/include/asm/kvm.h | 3 ++-
arch/mips/kvm/kvm_mips.c| 4 ++--
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/arch/mips/include/asm/kvm.h b/arch/mips/include/asm/kvm.h
index
From: David Daney david.da...@cavium.com
The initial patch set implementing MIPS KVM does not handle 64-bit
guests or use of the FPU. This patch set corrects these ABI issues,
and does some very minor clean up.
Changes from v2: Split into five parts, no code change.
David Daney (5):
From: David Daney david.da...@cavium.com
All registers are 64-bits wide, 32-bit guests use the least
significant portion of the register storage fields.
Signed-off-by: David Daney david.da...@cavium.com
---
arch/mips/include/asm/kvm.h | 16 +++-
1 file changed, 11 insertions(+), 5
On Sun, 2013-05-19 at 22:15 -0600, Alex Williamson wrote:
On Sun, 2013-05-19 at 17:35 +0200, Knut Omang wrote:
On Mon, 2013-05-13 at 16:23 -0600, Alex Williamson wrote:
On Mon, 2013-05-13 at 22:55 +0200, Knut Omang wrote:
Hi all,
Perfect timing from my perspective, thanks Alex!
From: David Daney david.da...@cavium.com
Because not all 256 CP0 registers are ever implemented, we need a
different method of manipulating them. Use the
KVM_GET_MSRS/KVM_SET_MSRS mechanism as x86 does for its MSRs.
Code related to implementing KVM_GET_MSRS/KVM_SET_MSRS is consolidated
in to
From: David Daney david.da...@cavium.com
Define a non-empty struct kvm_fpu.
Signed-off-by: David Daney david.da...@cavium.com
---
arch/mips/include/asm/kvm.h | 29 +
1 file changed, 21 insertions(+), 8 deletions(-)
diff --git a/arch/mips/include/asm/kvm.h
From: David Daney david.da...@cavium.com
Also we cannot set special zero register, so force it to zero.
Signed-off-by: David Daney david.da...@cavium.com
---
arch/mips/kvm/kvm_mips.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/mips/kvm/kvm_mips.c
ioperm() inheritance across threads is different in KVM then when run
on physical hardware. The following program runs on physical hardware
but get SEGV under KVM.
It appears that the I/O permission bits are not shared between threads
in the same way.
/* Original Copyright 2011, Kees Cook
-Original Message-
From: Michael S. Tsirkin [mailto:m...@redhat.com]
Sent: Monday, May 20, 2013 2:59 AM
To: Narasimhan, Sriram
Cc: ru...@rustcorp.com.au; virtualizat...@lists.linux-foundation.org;
kvm@vger.kernel.org; net...@vger.kernel.org; linux-ker...@vger.kernel.org;
Jason Wang
From: Chuanyu Qin qinchua...@huawei.com
Subject: [PATCH] get 2% or more performance improved by reducing spin_lock race
in vhost_work_queue
the wake_up_process func is included by spin_lock/unlock in vhost_work_queue,
but it could be done outside the spin_lock.
I have test it with kernel
This accelerates IOMMU operations in real and virtual
mode in the host kernel for the KVM guest.
The first patch with multitce support is useful for emulated devices as is.
The other patches are designed for VFIO although this series
does not contain any VFIO related code as the connection
This adds real mode handlers for the H_PUT_TCE_INDIRECT and
H_STUFF_TCE hypercalls for QEMU emulated devices such as virtio
devices or emulated PCI. These calls allow adding multiple entries
(up to 512) into the TCE table in one call which saves time on
transition to/from real mode.
This adds a
The current VFIO-on-POWER implementation supports only user mode
driven mapping, i.e. QEMU is sending requests to map/unmap pages.
However this approach is really slow, so we want to move that to KVM.
Since H_PUT_TCE can be extremely performance sensitive (especially with
network adapters where
This allows the host kernel to handle H_PUT_TCE, H_PUT_TCE_INDIRECT
and H_STUFF_TCE requests without passing them to QEMU, which should
save time on switching to QEMU and back.
Both real and virtual modes are supported - whenever the kernel
fails to handle TCE request, it passes it to the virtual
This adds special support for huge pages (16MB). The reference
counting cannot be easily done for such pages in real mode (when
MMU is off) so we added a list of huge pages. It is populated in
virtual mode and get_page is called just once per a huge page.
Real mode handlers check if the
VFIO implements platform independent stuff such as
a PCI driver, BAR access (via read/write on a file descriptor
or direct mapping when possible) and IRQ signaling.
The platform dependent part includes IOMMU initialization
and handling. This implements an IOMMU driver for VFIO
which does
The series adds support for VFIO on POWERPC in user space (such as QEMU).
The in-kernel real mode IOMMU support is added by another series posted
separately.
As the first and main aim of this series is the POWERNV platform support,
the Enable on POWERNV platform patch goes first and introduces an
This initializes IOMMU groups based on the IOMMU configuration
discovered during the PCI scan on POWERNV (POWER non virtualized)
platform. The IOMMU groups are to be used later by the VFIO driver,
which is used for PCI pass through.
It also implements an API for mapping/unmapping pages for
guest
The enables VFIO on the pSeries platform, enabling user space
programs to access PCI devices directly.
Signed-off-by: Alexey Kardashevskiy a...@ozlabs.ru
Cc: David Gibson da...@gibson.dropbear.id.au
Signed-off-by: Paul Mackerras pau...@samba.org
---
arch/powerpc/platforms/pseries/iommu.c |4
Oops, wrong subject (cut-n-paste) :)
There are 3 patches, not 5.
On 05/21/2013 01:33 PM, Alexey Kardashevskiy wrote:
The series adds support for VFIO on POWERPC in user space (such as QEMU).
The in-kernel real mode IOMMU support is added by another series posted
separately.
As the first
On 05/21/2013 04:40 AM, Marcelo Tosatti wrote:
On Mon, May 20, 2013 at 11:15:45PM +0300, Gleb Natapov wrote:
On Mon, May 20, 2013 at 04:46:24PM -0300, Marcelo Tosatti wrote:
On Fri, May 17, 2013 at 05:12:58AM +0800, Xiao Guangrong wrote:
The current kvm_mmu_zap_all is really slow - it is
On 05/21/2013 09:26 AM, Narasimhan, Sriram wrote:
-Original Message-
From: Michael S. Tsirkin [mailto:m...@redhat.com]
Sent: Monday, May 20, 2013 2:59 AM
To: Narasimhan, Sriram
Cc: ru...@rustcorp.com.au; virtualizat...@lists.linux-foundation.org;
kvm@vger.kernel.org;
From: Lai Jiangshan la...@cn.fujitsu.com
At the point of up_out label in kvmppc_hv_setup_htab_rma(),
srcu read lock is still held.
We have to release it before return.
Signed-off-by: Lai Jiangshan la...@cn.fujitsu.com
Cc: Marcelo Tosatti mtosa...@redhat.com
Cc: Gleb Natapov g...@redhat.com
Cc:
This adds real mode handlers for the H_PUT_TCE_INDIRECT and
H_STUFF_TCE hypercalls for QEMU emulated devices such as virtio
devices or emulated PCI. These calls allow adding multiple entries
(up to 512) into the TCE table in one call which saves time on
transition to/from real mode.
This adds a
The current VFIO-on-POWER implementation supports only user mode
driven mapping, i.e. QEMU is sending requests to map/unmap pages.
However this approach is really slow, so we want to move that to KVM.
Since H_PUT_TCE can be extremely performance sensitive (especially with
network adapters where
This accelerates IOMMU operations in real and virtual
mode in the host kernel for the KVM guest.
The first patch with multitce support is useful for emulated devices as is.
The other patches are designed for VFIO although this series
does not contain any VFIO related code as the connection
This allows the host kernel to handle H_PUT_TCE, H_PUT_TCE_INDIRECT
and H_STUFF_TCE requests without passing them to QEMU, which should
save time on switching to QEMU and back.
Both real and virtual modes are supported - whenever the kernel
fails to handle TCE request, it passes it to the virtual
This adds special support for huge pages (16MB). The reference
counting cannot be easily done for such pages in real mode (when
MMU is off) so we added a list of huge pages. It is populated in
virtual mode and get_page is called just once per a huge page.
Real mode handlers check if the
92 matches
Mail list logo
