On 12/9/22 23:28, Oliver Upton wrote:
> On Fri, Dec 09, 2022 at 04:44:46PM +, James Clark wrote:
>> ARMV8_PMU_PMCR_N_MASK is an unshifted value which results in the wrong
>> reset value for PMCR_EL0, so shift it to fix it.
>
> That's just mean. *_MASK tends to be a shifted mask, although
...@lists.infradead.org
Cc: kvmarm@lists.cs.columbia.edu
Cc: linux-ker...@vger.kernel.org
Signed-off-by: Anshuman Khandual
---
arch/arm64/kvm/arm.c | 4
1 file changed, 4 deletions(-)
diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c
index ee9b1166f330..d779a29c5607 100644
--- a/arch/arm64/kvm/arm.c
Poulose
Cc: Catalin Marinas
Cc: Will Deacon
Cc: linux-arm-ker...@lists.infradead.org
Cc: kvmarm@lists.cs.columbia.edu
Cc: linux-ker...@vger.kernel.org
Acked-by: Will Deacon
Signed-off-by: Anshuman Khandual
---
arch/arm64/include/asm/kvm_host.h | 2 +-
arch/arm64/kvm/arm.c | 16
@lists.cs.columbia.edu
Cc: linux-ker...@vger.kernel.org
Signed-off-by: Anshuman Khandual
---
arch/arm64/kvm/arm.c | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c
index e9a2b8f27792..19560e457c11 100644
--- a/arch/arm64/kvm/arm.c
...@lists.infradead.org
Cc: kvmarm@lists.cs.columbia.edu
Cc: linux-ker...@vger.kernel.org
Signed-off-by: Anshuman Khandual
---
arch/arm64/kvm/reset.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/kvm/reset.c b/arch/arm64/kvm/reset.c
index cba7872d69a8..acf309698f33 100644
--- a/arch
PA
range which could be supported on a given platform.
Cc: Marc Zyngier
Cc: Catalin Marinas
Cc: Will Deacon
Cc: linux-arm-ker...@lists.infradead.org
Cc: kvmarm@lists.cs.columbia.edu
Cc: linux-ker...@vger.kernel.org
Signed-off-by: Anshuman Khandual
---
arch/arm64/include/asm/cpufeature.h | 14
: Alexandru Elisei
Cc: Suzuki K Poulose
Cc: Catalin Marinas
Cc: Will Deacon
Cc: linux-arm-ker...@lists.infradead.org
Cc: kvmarm@lists.cs.columbia.edu
Cc: linux-ker...@vger.kernel.org
Anshuman Khandual (5):
arm64/mm: Add remaining ID_AA64MMFR0_PARANGE_ macros
KVM: arm64: Use ARM64_MIN_PARANGE_BITS
oulose
Cc: Catalin Marinas
Cc: Will Deacon
Cc: linux-arm-ker...@lists.infradead.org
Cc: kvmarm@lists.cs.columbia.edu
Cc: linux-ker...@vger.kernel.org
Fixes: c9b69a0cf0b4 ("KVM: arm64: Don't constrain maximum IPA size based on
host configuration")
Signed-off-by: Anshuman Khandual
---
T
On 8/11/21 3:06 PM, Marc Zyngier wrote:
> On Wed, 11 Aug 2021 05:52:29 +0100,
> Anshuman Khandual wrote:
>>
>> Even though ID_AA64MMFR0.PARANGE reports 52 bit PA size support, it cannot
>> be enabled as guest IPA size on 4K or 16K page size configurations. Hen
On 8/11/21 1:41 PM, Marc Zyngier wrote:
> On Wed, 11 Aug 2021 06:34:46 +0100,
> Anshuman Khandual wrote:
>>
>>
>>
>> On 8/10/21 7:03 PM, Marc Zyngier wrote:
>>> On 2021-08-10 08:02, Anshuman Khandual wrote:
>>>> All instances here coul
On 8/10/21 6:58 PM, Will Deacon wrote:
> On Tue, Aug 10, 2021 at 12:32:39PM +0530, Anshuman Khandual wrote:
>> kvm_target_cpu() never returns a negative error code, so check_kvm_target()
>> would never have 'ret' filled with a negative error code. Hence the perc
On 8/10/21 7:03 PM, Marc Zyngier wrote:
> On 2021-08-10 08:02, Anshuman Khandual wrote:
>> All instances here could just directly test against CONFIG_ARM64_XXK_PAGES
>> instead of evaluating via PAGE_SHIFT or PAGE_SIZE. With this change, there
>> will be no such usage
On 8/10/21 6:50 PM, Will Deacon wrote:
> On Tue, Aug 10, 2021 at 12:32:37PM +0530, Anshuman Khandual wrote:
>> All instances here could just directly test against CONFIG_ARM64_XXK_PAGES
>> instead of evaluating via PAGE_SHIFT or PAGE_SIZE. With this change, there
>> will
oulose
Cc: Catalin Marinas
Cc: Will Deacon
Cc: linux-arm-ker...@lists.infradead.org
Cc: kvmarm@lists.cs.columbia.edu
Cc: linux-ker...@vger.kernel.org
Fixes: c9b69a0cf0b4 ("KVM: arm64: Don't constrain maximum IPA size based on
host configuration")
Signed-off-by: Anshuman Khandual
---
T
Zyngier
Cc: linux-perf-us...@vger.kernel.org
Cc: linux-arm-ker...@lists.infradead.org
Cc: kvmarm@lists.cs.columbia.edu
Cc: linux-ker...@vger.kernel.org
Signed-off-by: Anshuman Khandual
---
This applies on v5.14-rc5
Changes in V2:
- Split out the KVM part
Changes in V1:
https://lore.kernel.org/linux
On 8/10/21 6:59 PM, Marc Zyngier wrote:
> On 2021-08-10 08:02, Anshuman Khandual wrote:
>> Drop the hard coded value for the minimum IPA range i.e 32 bit. Instead
>> define a macro KVM_PHYS_SHIFT_MIN which improves the code readability.
>>
>> Cc: Marc Zyngier
On 8/10/21 6:51 PM, Will Deacon wrote:
> On Tue, Aug 10, 2021 at 12:32:38PM +0530, Anshuman Khandual wrote:
>> Could do without this additional indirection via init_common_resources() by
>> just calling kvm_set_ipa_limit() directly instead. This change saves memory
>>
On 8/10/21 7:01 PM, Will Deacon wrote:
> On Tue, Aug 10, 2021 at 10:36:38AM +0530, Anshuman Khandual wrote:
>> ID_AA64DFR0_PMUVER_IMP_DEF which indicate implementation defined PMU, never
>> actually gets used although there are '0xf' instances scattered all around.
>&
...@lists.infradead.org
Cc: kvmarm@lists.cs.columbia.edu
Cc: linux-ker...@vger.kernel.org
Signed-off-by: Anshuman Khandual
---
arch/arm64/include/asm/kvm_mmu.h | 3 ++-
arch/arm64/kvm/reset.c | 2 +-
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/include/asm/kvm_mmu.h b/arch/arm64
...@lists.infradead.org
Cc: kvmarm@lists.cs.columbia.edu
Cc: linux-ker...@vger.kernel.org
Signed-off-by: Anshuman Khandual
---
arch/arm64/kvm/arm.c | 4
1 file changed, 4 deletions(-)
diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c
index 16f93678c17e..bae22d2bdca9 100644
--- a/arch/arm64/kvm/arm.c
...@vger.kernel.org
Signed-off-by: Anshuman Khandual
---
arch/arm64/kvm/arm.c | 14 --
1 file changed, 14 deletions(-)
diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c
index 19560e457c11..16f93678c17e 100644
--- a/arch/arm64/kvm/arm.c
+++ b/arch/arm64/kvm/arm.c
@@ -2010,11 +2010,6 @@ static int
-ker...@lists.infradead.org
Cc: kvmarm@lists.cs.columbia.edu
Cc: linux-ker...@vger.kernel.org
Signed-off-by: Anshuman Khandual
---
arch/arm64/kvm/arm.c | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c
index e9a2b8f27792
: linux-arm-ker...@lists.infradead.org
Cc: kvmarm@lists.cs.columbia.edu
Cc: linux-ker...@vger.kernel.org
Signed-off-by: Anshuman Khandual
---
arch/arm64/kvm/hyp/pgtable.c | 6 +++---
arch/arm64/mm/mmu.c | 2 +-
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/kvm
...@lists.infradead.org
Cc: kvmarm@lists.cs.columbia.edu
Cc: linux-ker...@vger.kernel.org
Anshuman Khandual (5):
KVM: arm64: Drop direct PAGE_[SHIFT|SIZE] usage as page size
KVM: arm64: Drop init_common_resources()
KVM: arm64: Drop check_kvm_target_cpu() based percpu probe
KVM: arm64: Drop unused
Zyngier
Cc: linux-perf-us...@vger.kernel.org
Cc: linux-arm-ker...@lists.infradead.org
Cc: kvmarm@lists.cs.columbia.edu
Cc: linux-ker...@vger.kernel.org
Signed-off-by: Anshuman Khandual
---
This applies on v5.14-rc5
arch/arm64/include/asm/cpufeature.h | 2 +-
arch/arm64/kernel/perf_event.c | 2
...@lists.infradead.org
Cc: kvmarm@lists.cs.columbia.edu
Cc: linux-ker...@vger.kernel.org
Signed-off-by: Anshuman Khandual
---
This applies on v5.14-rc5.
arch/arm64/include/asm/sysreg.h | 3 +++
arch/arm64/kvm/reset.c | 17 ++---
2 files changed, 5 insertions(+), 15 deletions(-)
diff
On 4/21/21 5:54 PM, Mike Rapoport wrote:
> On Wed, Apr 21, 2021 at 04:36:46PM +0530, Anshuman Khandual wrote:
>>
>> On 4/21/21 12:21 PM, Mike Rapoport wrote:
>>> From: Mike Rapoport
>>>
>>> The arm64's version of pfn_valid() differs from the generic b
On 4/21/21 5:49 PM, Mike Rapoport wrote:
> On Wed, Apr 21, 2021 at 04:29:48PM +0530, Anshuman Khandual wrote:
>>
>> On 4/21/21 12:21 PM, Mike Rapoport wrote:
>>> From: Mike Rapoport
>>>
>>> The intended semantics of pfn_valid() is to verify whet
On 4/21/21 12:21 PM, Mike Rapoport wrote:
> From: Mike Rapoport
>
> The arm64's version of pfn_valid() differs from the generic because of two
> reasons:
>
> * Parts of the memory map are freed during boot. This makes it necessary to
> verify that there is actual physical memory that
On 4/21/21 12:21 PM, Mike Rapoport wrote:
> From: Mike Rapoport
>
> The intended semantics of pfn_valid() is to verify whether there is a
> struct page for the pfn in question and nothing else.
>
> Yet, on arm64 it is used to distinguish memory areas that are mapped in the
> linear map vs
_init free_low_memory_core_early(void)
> {
> unsigned long count = 0;
> @@ -2010,8 +2035,7 @@ static unsigned long __init
> free_low_memory_core_early(void)
>
> memblock_clear_hotplug(0, -1);
>
> - for_each_reserved_mem_range(i, , )
> -
acking that PFN.
>
> The most "generic" version of pfn_valid() used by the configurations with
> SPARSEMEM enabled resides in include/linux/mmzone.h so this is the most
> suitable place for documentation about semantics of pfn_valid().
>
> Suggested-by: Anshuman Khandual
Adding James here.
+ James Morse
On 4/7/21 10:56 PM, Mike Rapoport wrote:
> From: Mike Rapoport
>
> Hi,
>
> These patches aim to remove CONFIG_HOLES_IN_ZONE and essentially hardwire
> pfn_valid_within() to 1.
That would be really great for arm64 platform as it will save CPU cycles on
many
On 4/7/21 10:56 PM, Mike Rapoport wrote:
> From: Mike Rapoport
>
> The struct pages representing a reserved memory region are initialized
> using reserve_bootmem_range() function. This function is called for each
> reserved region just before the memory is freed from memblock to the buddy
>
On 4/7/21 10:56 PM, Mike Rapoport wrote:
> From: Mike Rapoport
>
> The intended semantics of pfn_valid() is to verify whether there is a
> struct page for the pfn in question and nothing else.
Should there be a comment affirming this semantics interpretation, above the
generic pfn_valid() in
On 4/7/21 10:56 PM, Mike Rapoport wrote:
> From: Mike Rapoport
>
> The arm64's version of pfn_valid() differs from the generic because of two
> reasons:
>
> * Parts of the memory map are freed during boot. This makes it necessary to
> verify that there is actual physical memory that
Morse
Cc: Suzuki K Poulose
Cc: Ard Biesheuvel
Cc: Mark Rutland
Cc: linux-arm-ker...@lists.infradead.org
Cc: kvmarm@lists.cs.columbia.edu
Cc: linux-...@vger.kernel.org
Cc: linux-ker...@vger.kernel.org
Acked-by: Marc Zyngier
Signed-off-by: James Morse
Signed-off-by: Anshuman Khandual
---
Changes
On 3/9/21 7:35 PM, Will Deacon wrote:
> On Mon, Mar 08, 2021 at 02:42:00PM +, Marc Zyngier wrote:
>> On Fri, 05 Mar 2021 14:36:09 +,
>> Anshuman Khandual wrote:
>>> - switch (cpuid_feature_extract_unsigned_field(mmfr0, tgran_2)) {
>>> - default
On 3/5/21 8:21 PM, Mark Rutland wrote:
> On Fri, Mar 05, 2021 at 08:06:09PM +0530, Anshuman Khandual wrote:
>> From: James Morse
>>
>> As per ARM ARM DDI 0487G.a, when FEAT_LPA2 is implemented, ID_AA64MMFR0_EL1
>> might contain a range of values to describe sup
Morse
Cc: Suzuki K Poulose
Cc: Ard Biesheuvel
Cc: Mark Rutland
Cc: linux-arm-ker...@lists.infradead.org
Cc: kvmarm@lists.cs.columbia.edu
Cc: linux-...@vger.kernel.org
Cc: linux-ker...@vger.kernel.org
Signed-off-by: James Morse
Signed-off-by: Anshuman Khandual
---
arch/arm64/include/asm/sysreg.h
On 1/5/21 3:38 PM, Catalin Marinas wrote:
> On Tue, Jan 05, 2021 at 05:22:21PM +0800, Keqian Zhu wrote:
>> The local variable irq is added in commit a26388152531 ("arm64:
>> Remove custom IRQ stat accounting"), but forget to remove in
>> commit 5089bc51f81f ("arm64/smp: Use irq_desc_kstat_cpu()
On 07/02/2020 11:04 PM, Catalin Marinas wrote:
> On Wed, May 27, 2020 at 08:33:35AM +0530, Anshuman Khandual wrote:
>> These are remaining patches from V4 series which had some pending reviews
>> from Suzuki (https://patchwork.kernel.org/cover/11557333/). Also dropped
FTR_STRICT -> FTR_NONSTRICT) as 64 bit registers per
Will
- Changed ID_PFR0.CSV2 (FTR_STRICT -> FTR_NONSTRICT) as 64 bit registers per
Will
- Changed some commit messages
Changes in V1:
(https://patchwork.kernel.org/project/linux-arm-kernel/list/?series=234093)
Anshuman Khandual (4):
ill
- Changed ID_PFR0.CSV2 (FTR_STRICT -> FTR_NONSTRICT) as 64 bit registers per
Will
- Changed some commit messages
Changes in V1:
(https://patchwork.kernel.org/project/linux-arm-kernel/list/?series=234093)
Anshuman Khandual (4):
arm64/cpufeature: Add remaining feature bits in ID_AA
On 05/21/2020 08:49 PM, Will Deacon wrote:
> On Tue, 19 May 2020 15:10:37 +0530, Anshuman Khandual wrote:
>> This series is primarily motivated from an adhoc list from Mark Rutland
>> during our previous ID_ISAR6 discussion [1]. The current proposal also
>> accommodates
On 05/20/2020 11:24 PM, Will Deacon wrote:
> On Tue, 12 May 2020 07:27:27 +0530, Anshuman Khandual wrote:
>> This validates hypervisor capabilities like VMID width, IPA range for any
>> hot plug CPU against system finalized values. KVM's view of the IPA space
>> is used w
Zyngier
Cc: Mark Rutland
Cc: James Morse
Cc: Suzuki K Poulose
Cc: kvmarm@lists.cs.columbia.edu
Cc: linux-arm-ker...@lists.infradead.org
Cc: linux-ker...@vger.kernel.org
Suggested-by: Mark Rutland
Reviewed-by: Suzuki K Poulose
Signed-off-by: Anshuman Khandual
---
arch/arm64/include/asm/cpu.h
Rutland
Cc: James Morse
Cc: Suzuki K Poulose
Cc: kvmarm@lists.cs.columbia.edu
Cc: linux-arm-ker...@lists.infradead.org
Cc: linux-ker...@vger.kernel.org
Suggested-by: Will Deacon
Signed-off-by: Anshuman Khandual
---
arch/arm64/include/asm/cpu.h| 1 +
arch/arm64/include/asm/sysreg.h | 3
kernel/list/?series=234093)
Anshuman Khandual (17):
arm64/cpufeature: Add explicit ftr_id_isar0[] for ID_ISAR0 register
arm64/cpufeature: Drop TraceFilt feature exposure from ID_DFR0 register
arm64/cpufeature: Make doublelock a signed feature in ID_AA64DFR0
arm64/cpufeature: Introduce ID_PF
Poulose
Cc: kvmarm@lists.cs.columbia.edu
Cc: linux-arm-ker...@lists.infradead.org
Cc: linux-ker...@vger.kernel.org
Suggested-by: Will Deacon
Signed-off-by: Anshuman Khandual
---
arch/arm64/include/asm/cpu.h| 1 +
arch/arm64/include/asm/sysreg.h | 3 +++
arch/arm64/kernel/cpufeature.c
with cpuid_feature_extract_unsigned_field()
which can extract given standard feature (4 bits width i.e 0xf mask) field.
Cc: Catalin Marinas
Cc: Will Deacon
Cc: Marc Zyngier
Cc: James Morse
Cc: kvmarm@lists.cs.columbia.edu
Cc: linux-arm-ker...@lists.infradead.org
Cc: linux-ker...@vger.kernel.org
Signed-off-by: Anshuman Khandual
: James Morse
Cc: linux-arm-ker...@lists.infradead.org
Cc: linux-ker...@vger.kernel.org
Cc: kvmarm@lists.cs.columbia.edu
Signed-off-by: Anshuman Khandual
---
This applies after (https://patchwork.kernel.org/patch/11541893/).
arch/arm64/include/asm/cpufeature.h | 11 ++-
arch/arm64
: Marc Zyngier
Cc: Mark Rutland
Cc: James Morse
Cc: Suzuki K Poulose
Cc: linux-arm-ker...@lists.infradead.org
Cc: kvmarm@lists.cs.columbia.edu
Cc: linux-ker...@vger.kernel.org
Reviewed-by: Marc Zyngier
Suggested-by: Suzuki Poulose
Signed-off-by: Anshuman Khandual
---
Changes in V3:
- Dropped
On 05/09/2020 04:29 PM, Marc Zyngier wrote:
> On Fri, 08 May 2020 03:52:38 +0100,
> Anshuman Khandual wrote:
>>
>> This validates hypervisor capabilities like VMID width, IPA range for any
>> hot plug CPU against system finalized values. While here, it fact
On 05/05/2020 04:42 PM, Will Deacon wrote:
> On Sat, May 02, 2020 at 07:03:53PM +0530, Anshuman Khandual wrote:
>> This adds basic building blocks required for ID_PFR2 CPU register which
>> provides information about the AArch32 programmers model which must be
>> interpret
Cc: James Morse
Cc: Suzuki K Poulose
Cc: linux-arm-ker...@lists.infradead.org
Cc: kvmarm@lists.cs.columbia.edu
Cc: linux-ker...@vger.kernel.org
Suggested-by: Suzuki Poulose
Signed-off-by: Anshuman Khandual
---
Changes in V2:
- Added is_hyp_mode_available() check per Marc
- Moved
On 05/07/2020 03:50 PM, Marc Zyngier wrote:
> On Thu, 7 May 2020 11:49:47 +0530
> Anshuman Khandual wrote:
>
> Hi Anshuman,
Hi Marc,
>
>> This validates KVM capabilities like VMID width, IPA range for hotplug CPU
>> against system finalized values. While here, i
Morse
Cc: Suzuki K Poulose
Cc: linux-arm-ker...@lists.infradead.org
Cc: kvmarm@lists.cs.columbia.edu
Cc: linux-ker...@vger.kernel.org
Suggested-by: Suzuki Poulose
Signed-off-by: Anshuman Khandual
---
arch/arm64/include/asm/cpufeature.h | 22 +++
arch/arm64/include/asm/kvm_mmu.h
On 05/05/2020 02:03 AM, Will Deacon wrote:
> On Sat, May 02, 2020 at 07:03:55PM +0530, Anshuman Khandual wrote:
>> This adds basic building blocks required for ID_MMFR5 CPU register which
>> provides information about the implemented memory model and memory
>> manageme
Poulose
Cc: kvmarm@lists.cs.columbia.edu
Cc: linux-arm-ker...@lists.infradead.org
Cc: linux-ker...@vger.kernel.org
Suggested-by: Will Deacon
Signed-off-by: Anshuman Khandual
---
arch/arm64/include/asm/cpu.h| 1 +
arch/arm64/include/asm/sysreg.h | 3 +++
arch/arm64/kernel/cpufeature.c
Rutland
Cc: James Morse
Cc: Suzuki K Poulose
Cc: kvmarm@lists.cs.columbia.edu
Cc: linux-arm-ker...@lists.infradead.org
Cc: linux-ker...@vger.kernel.org
Suggested-by: Will Deacon
Signed-off-by: Anshuman Khandual
---
arch/arm64/include/asm/cpu.h| 1 +
arch/arm64/include/asm/sysreg.h | 3
Zyngier
Cc: Mark Rutland
Cc: James Morse
Cc: Suzuki K Poulose
Cc: kvmarm@lists.cs.columbia.edu
Cc: linux-arm-ker...@lists.infradead.org
Cc: linux-ker...@vger.kernel.org
Suggested-by: Mark Rutland
Reviewed-by: Suzuki K Poulose
Signed-off-by: Anshuman Khandual
---
arch/arm64/include/asm/cpu.h
ssages
Changes in V1:
(https://patchwork.kernel.org/project/linux-arm-kernel/list/?series=234093)
Anshuman Khandual (16):
arm64/cpufeature: Add explicit ftr_id_isar0[] for ID_ISAR0 register
arm64/cpufeature: Drop TraceFilt feature exposure from ID_DFR0 register
arm64/cpufeature: Make doub
On 04/30/2020 02:56 AM, Will Deacon wrote:
> Hi Anshuman,
>
> On Wed, Apr 29, 2020 at 03:07:15PM +0530, Anshuman Khandual wrote:
>> On 04/14/2020 03:18 PM, Anshuman Khandual wrote:
>>> This series is primarily motivated from an adhoc list from Mark Rutland
>>
On 04/14/2020 03:18 PM, Anshuman Khandual wrote:
> This series is primarily motivated from an adhoc list from Mark Rutland
> during our previous ID_ISAR6 discussion [1]. The current proposal also
> accommodates some more suggestions from Will and Suzuki.
>
> This series adds
Poulose
Cc: kvmarm@lists.cs.columbia.edu
Cc: linux-arm-ker...@lists.infradead.org
Cc: linux-ker...@vger.kernel.org
Suggested-by: Will Deacon
Signed-off-by: Anshuman Khandual
---
arch/arm64/include/asm/cpu.h| 1 +
arch/arm64/include/asm/sysreg.h | 3 +++
arch/arm64/kernel/cpufeature.c
Rutland
Cc: James Morse
Cc: Suzuki K Poulose
Cc: kvmarm@lists.cs.columbia.edu
Cc: linux-arm-ker...@lists.infradead.org
Cc: linux-ker...@vger.kernel.org
Suggested-by: Will Deacon
Signed-off-by: Anshuman Khandual
---
arch/arm64/include/asm/cpu.h| 1 +
arch/arm64/include/asm/sysreg.h | 3
Zyngier
Cc: Mark Rutland
Cc: James Morse
Cc: Suzuki K Poulose
Cc: kvmarm@lists.cs.columbia.edu
Cc: linux-arm-ker...@lists.infradead.org
Cc: linux-ker...@vger.kernel.org
Suggested-by: Mark Rutland
Reviewed-by: Suzuki K Poulose
Signed-off-by: Anshuman Khandual
---
arch/arm64/include/asm/cpu.h
SV2 (FTR_STRICT -> FTR_NONSTRICT) as 64 bit registers per
Will
- Changed some commit messages
Changes in V1:
(https://patchwork.kernel.org/project/linux-arm-kernel/list/?series=234093)
Anshuman Khandual (16):
arm64/cpufeature: Add explicit ftr_id_isar0[] for ID_ISAR0 register
arm64/cpufeature
On 04/09/2020 06:24 PM, Will Deacon wrote:
> On Tue, Jan 28, 2020 at 06:09:04PM +0530, Anshuman Khandual wrote:
>> This adds basic building blocks required for ID_PFR2 CPU register which
>> provides information about the AArch32 programmers model which must be
>> interpret
On 04/06/2020 10:39 PM, Will Deacon wrote:
> On Tue, Jan 28, 2020 at 06:09:03PM +0530, Anshuman Khandual wrote:
>> This series is primarily motivated from an adhoc list from Mark Rutland
>> during our ID_ISAR6 discussion [1]. Besides, it also includes a patch
>> which d
On 02/14/2020 09:28 PM, Peter Maydell wrote:
> On Fri, 14 Feb 2020 at 04:23, Anshuman Khandual
> wrote:
>>
>>
>>
>> On 01/28/2020 06:09 PM, Anshuman Khandual wrote:
>>> This series is primarily motivated from an adhoc list from Mark Rutland
>>> duri
On 01/28/2020 06:09 PM, Anshuman Khandual wrote:
> This series is primarily motivated from an adhoc list from Mark Rutland
> during our ID_ISAR6 discussion [1]. Besides, it also includes a patch
> which does macro replacement for various open bits shift encodings in
> various CPU
Cc: Mark Rutland
Cc: kvmarm@lists.cs.columbia.edu
Cc: linux-ker...@vger.kernel.org
Signed-off-by: Anshuman Khandual
---
arch/arm64/include/asm/cpu.h| 1 +
arch/arm64/include/asm/sysreg.h | 4
arch/arm64/kernel/cpufeature.c | 11 +++
arch/arm64/kernel/cpuinfo.c | 1 +
arch
@lists.cs.columbia.edu
Cc: linux-ker...@vger.kernel.org
Anshuman Khandual (6):
arm64/cpufeature: Introduce ID_PFR2 CPU register
arm64/cpufeature: Add DIT and CSV2 feature bits in ID_PFR0 register
arm64/cpufeature: Add remaining feature bits in ID_MMFR4 register
arm64/cpufeature: Define an explicit
On 12/30/2019 01:57 PM, Mike Rapoport wrote:
> From: Mike Rapoport
>
> Implement primitives necessary for the 4th level folding, add walks of p4d
> level where appropriate, replace 5level-fixup.h with pgtable-nop4d.h and
> remove __ARCH_USE_5LEVEL_HACK.
>
> Since arm and arm64 share kvm
On 12/30/2019 01:57 PM, Mike Rapoport wrote:
> From: Mike Rapoport
>
> Hi,
Hello Mike,
>
> This is a part of clean up of the page table manipulation code that aims to
> remove asm-generic/5level-fixup.h and asm-generic/pgtable-nop4d-hack.h
>
> There is a single patch for both arm and
On 12/12/2019 10:01 PM, Mark Rutland wrote:
> On Thu, Dec 12, 2019 at 03:22:13PM +, Suzuki Kuruppassery Poulose wrote:
>> On 12/12/2019 14:46, Mark Rutland wrote:
>>> On Thu, Dec 12, 2019 at 03:44:23PM +0530, Anshuman Khandual wrote:
>>>> +#define ID_IS
: kvmarm@lists.cs.columbia.edu
Acked-by: Marc Zyngier
Signed-off-by: Anshuman Khandual
---
Changes in V2:
- Added an explicit ftr_id_isar6[] instead of using ftr_generic_32bits per Mark
- Dropped ID_ISAR6_SPECRES_SHIFT exposure in ftr_id_isar6[] per Mark
- Reversed ID_ISAR6_* definitions sequence
On 12/12/2019 08:52 PM, Suzuki Kuruppassery Poulose wrote:
> On 12/12/2019 14:46, Mark Rutland wrote:
>> On Thu, Dec 12, 2019 at 03:44:23PM +0530, Anshuman Khandual wrote:
>>> +#define ID_ISAR6_JSCVT_SHIFT 0
>>> +#define ID_ISAR6_DP_SHIFT 4
>>>
On 12/12/2019 05:13 PM, Marc Zyngier wrote:
> On 2019-12-12 10:14, Anshuman Khandual wrote:
>> This adds basic building blocks required for ISAR6 CPU ID register which
>> identifies support for various instruction implementation on AArch32 state.
>
> nit: the register na
: kvmarm@lists.cs.columbia.edu
Signed-off-by: Anshuman Khandual
---
arch/arm64/include/asm/cpu.h| 1 +
arch/arm64/include/asm/sysreg.h | 9 +
arch/arm64/kernel/cpufeature.c | 7 ++-
arch/arm64/kernel/cpuinfo.c | 1 +
arch/arm64/kvm/sys_regs.c | 2 +-
5 files changed, 18
while running 100
> KVM
> guest instances.
>
> This patch fixes the issue by ensuring that the page belongs to a valid PFN
> when we fallback to using the lower limit of the scan range upon failure in
> fast_isolate_freepages().
>
> Fixes: 5a811889de10f1eb ("mm, compact
On 05/24/2019 06:00 PM, Mel Gorman wrote:
> On Fri, May 24, 2019 at 04:26:16PM +0530, Anshuman Khandual wrote:
>>
>>
>> On 05/24/2019 02:50 PM, Suzuki K Poulose wrote:
>>> Hi,
>>>
>>> We are hitting NULL pointer dereferences while running stress
On 05/24/2019 02:50 PM, Suzuki K Poulose wrote:
> Hi,
>
> We are hitting NULL pointer dereferences while running stress tests with KVM.
> See splat [0]. The test is to spawn 100 VMs all doing standard debian
> installation (Thanks to Marc's automated scripts, available here [1] ).
> The
On 01/16/2019 06:14 PM, Michal Hocko wrote:
> On Wed 16-01-19 04:30:18, Matthew Wilcox wrote:
>> On Wed, Jan 16, 2019 at 07:57:03AM +0100, Michal Hocko wrote:
>>> On Wed 16-01-19 11:51:32, Anshuman Khandual wrote:
>>>> All architectures have been defining their
On 01/16/2019 06:00 PM, Matthew Wilcox wrote:
> On Wed, Jan 16, 2019 at 07:57:03AM +0100, Michal Hocko wrote:
>> On Wed 16-01-19 11:51:32, Anshuman Khandual wrote:
>>> All architectures have been defining their own PGALLOC_GFP as (GFP_KERNEL |
>>> __GFP_ZERO) and u
On 01/16/2019 12:25 PM, Mike Rapoport wrote:
> On Wed, Jan 16, 2019 at 11:51:32AM +0530, Anshuman Khandual wrote:
>> All architectures have been defining their own PGALLOC_GFP as (GFP_KERNEL |
>> __GFP_ZERO) and using it for allocating page table pages. This causes some
>
On 01/16/2019 12:40 PM, Christophe Leroy wrote:
>
>
> Le 16/01/2019 à 07:21, Anshuman Khandual a écrit :
>> All architectures have been defining their own PGALLOC_GFP as (GFP_KERNEL |
>> __GFP_ZERO) and using it for allocating page table pages. This causes some
>>
allocation flag if included in include/linux/gfp.h.
Signed-off-by: Anshuman Khandual
---
Build tested on arm, arm64, powerpc, powerpc64le and x86.
Boot tested on arm64 and x86.
Changes in V2:
- Moved GFP_PGTABLE into include/asm-generic/pgtable.h
- On X86 added __GFP_ACCOUNT into GFP_PGTABLE
On 01/14/2019 12:31 PM, Michal Hocko wrote:
> On Mon 14-01-19 09:30:55, Anshuman Khandual wrote:
>>
>>
>> On 01/13/2019 11:05 PM, Michal Hocko wrote:
>>> On Sat 12-01-19 15:56:38, Anshuman Khandual wrote:
>>>> All architectures have been def
On 01/12/2019 09:19 PM, Matthew Wilcox wrote:
> On Sat, Jan 12, 2019 at 02:49:29PM +0100, Christophe Leroy wrote:
>> As far as I can see,
>>
>> #define GFP_KERNEL_ACCOUNT (GFP_KERNEL | __GFP_ACCOUNT)
>>
>> So what's the difference between:
>>
>> (GFP_KERNEL_ACCOUNT | __GFP_ZERO) &
On 01/12/2019 10:18 PM, Shakeel Butt wrote:
>> --- a/arch/x86/kernel/espfix_64.c
>> +++ b/arch/x86/kernel/espfix_64.c
>> @@ -57,8 +57,6 @@
>> # error "Need more virtual address space for the ESPFIX hack"
>> #endif
>>
>> -#define PGALLOC_GFP (GFP_KERNEL | __GFP_ZERO)
>> -
>> /* This contains
On 01/13/2019 11:05 PM, Michal Hocko wrote:
> On Sat 12-01-19 15:56:38, Anshuman Khandual wrote:
>> All architectures have been defining their own PGALLOC_GFP as (GFP_KERNEL |
>> __GFP_ZERO) and using it for allocating page table pages. This causes some
>> code duplicatio
On 01/12/2019 05:42 PM, Matthew Wilcox wrote:
> On Sat, Jan 12, 2019 at 03:56:38PM +0530, Anshuman Khandual wrote:
>> All architectures have been defining their own PGALLOC_GFP as (GFP_KERNEL |
>> __GFP_ZERO) and using it for allocating page table pages.
>
> Except that's
architecture. This creates a new generic GFP flag flag which can be used
for any page table page allocation. Does not cause any functional change.
Signed-off-by: Anshuman Khandual
---
arch/arm/include/asm/pgalloc.h | 8 +++-
arch/arm/mm/mmu.c| 2
On 10/31/2018 11:27 PM, Punit Agrawal wrote:
> KVM only supports PMD hugepages at stage 2. Now that the various page
> handling routines are updated, extend the stage 2 fault handling to
> map in PUD hugepages.
>
> Addition of PUD hugepage support enables additional page sizes (e.g.,
> 1G with
On 10/31/2018 11:27 PM, Punit Agrawal wrote:
> In preparation for creating PUD hugepages at stage 2, add support for
> write protecting PUD hugepages when they are encountered. Write
> protecting guest tables is used to track dirty pages when migrating
> VMs.
>
> Also, provide trivial
On 10/31/2018 11:27 PM, Punit Agrawal wrote:
> In preparation for creating larger hugepages at Stage 2, add support
> to the age handling notifiers for PUD hugepages when encountered.
>
> Provide trivial helpers for arm32 to allow sharing code.
>
> Signed-off-by: Punit Agrawal
> Reviewed-by:
On 10/31/2018 11:27 PM, Punit Agrawal wrote:
> Introduce helpers to abstract architectural handling of the conversion
> of pfn to page table entries and marking a PMD page table entry as a
> block entry.
Why is this necessary ? we would still need to access PMD, PUD as is
without any
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