Hello guys!
Currently on ARM, irqfd supports routing an host eventfd towards a
virtual SPI:
eventfd - vSPI = gsi+32
parameters of irqfd are the eventfd and the gsi.
Yes, but this works only with GICv2m, because it actually turns MSI data into
SPI number.
ITS works in a completely
Hi,
On 06/10/2015 10:31 AM, Pavel Fedin wrote:
Hello guys!
Currently on ARM, irqfd supports routing an host eventfd towards a
virtual SPI:
eventfd - vSPI = gsi+32
parameters of irqfd are the eventfd and the gsi.
Yes, but this works only with GICv2m, because it actually turns MSI data
Hi!
indeed in newly added qemu kvm-all.c kvm_arch_msi_data_to_gsi we could
call a new ioctl that translates the data + deviceid? into an LPI and
program irqfd with that LPI. This is done once when setting irqfd up.
This also means extending irqfd support to lpi injection, gsi being the
LPI
Hello!
KVM GSI routing, even if only used for MSI routing then mandates to
build entries for non MSI IRQs, using irqchip routing entries. Then you
draw the irqchip.c kvm_irq_routing_table
chip[KVM_NR_IRQCHIPS][KVM_IRQCHIP_NUM_PINS] static allocation issue.
Sorry for this add-on, needed
On 08/06/15 11:54, Pavel Fedin wrote:
Hi!
I'm afraid this is not enough. A write to GICR_TRANSLATER (DID+EID)
results in a (LPI,CPU) pair. Can you easily express the CPU part in
irqfd (this is a genuine question, I'm not familiar enough with that
part of the core)?
But... As far as i
Hello everybody!
The GICv3 ITS (Interrupt Translation Service) is a part of the
ARM GICv3 interrupt controller used for implementing MSIs.
It specifies a new kind of interrupts (LPIs), which are mapped to
establish a connection between a device, its MSI payload value and
the target
Hi!
I'm afraid this is not enough. A write to GICR_TRANSLATER (DID+EID)
results in a (LPI,CPU) pair. Can you easily express the CPU part in
irqfd (this is a genuine question, I'm not familiar enough with that
part of the core)?
But... As far as i could understand, LPI is added to a
